sys/dev/ixgbe/ixgbe_phy.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2008, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #include "ixgbe_api.h"
  36 #include "ixgbe_common.h"
  37 #include "ixgbe_phy.h"
  38
  39 /**
  40  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
  41  *  @hw: pointer to the hardware structure
  42  *
  43  *  Initialize the function pointers.
  44  **/
  45 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
  46 {
  47         struct ixgbe_phy_info *phy = &hw->phy;
  48
  49         /* PHY */
  50         phy->ops.identify = &ixgbe_identify_phy_generic;
  51         phy->ops.reset = &ixgbe_reset_phy_generic;
  52         phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
  53         phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
  54         phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
  55         phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
  56         phy->ops.check_link = NULL;
  57         phy->ops.get_firmware_version = NULL;
  58
  59         return IXGBE_SUCCESS;
  60 }
  61
  62 /**
  63  *  ixgbe_identify_phy_generic - Get physical layer module
  64  *  @hw: pointer to hardware structure
  65  *
  66  *  Determines the physical layer module found on the current adapter.
  67  **/
  68 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  69 {
  70         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  71         u32 phy_addr;
  72
  73         if (hw->phy.type == ixgbe_phy_unknown) {
  74                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  75                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
  76                                 hw->phy.addr = phy_addr;
  77                                 ixgbe_get_phy_id(hw);
  78                                 hw->phy.type =
  79                                         ixgbe_get_phy_type_from_id(hw->phy.id);
  80                                 status = IXGBE_SUCCESS;
  81                                 break;
  82                         }
  83                 }
  84         } else {
  85                 status = IXGBE_SUCCESS;
  86         }
  87
  88         return status;
  89 }
  90
  91 /**
  92  *  ixgbe_validate_phy_addr - Determines phy address is valid
  93  *  @hw: pointer to hardware structure
  94  *
  95  **/
  96 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
  97 {
  98         u16 phy_id = 0;
  99         bool valid = FALSE;
 100
 101         hw->phy.addr = phy_addr;
 102         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 103                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 104
 105         if (phy_id != 0xFFFF && phy_id != 0x0)
 106                 valid = TRUE;
 107
 108         return valid;
 109 }
 110
 111 /**
 112  *  ixgbe_get_phy_id - Get the phy type
 113  *  @hw: pointer to hardware structure
 114  *
 115  **/
 116 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 117 {
 118         u32 status;
 119         u16 phy_id_high = 0;
 120         u16 phy_id_low = 0;
 121
 122         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 123                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 124                                       &phy_id_high);
 125
 126         if (status == IXGBE_SUCCESS) {
 127                 hw->phy.id = (u32)(phy_id_high << 16);
 128                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 129                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 130                                               &phy_id_low);
 131                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 132                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 133         }
 134
 135         return status;
 136 }
 137
 138 /**
 139  *  ixgbe_get_phy_type_from_id - Get the phy type
 140  *  @hw: pointer to hardware structure
 141  *
 142  **/
 143 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 144 {
 145         enum ixgbe_phy_type phy_type;
 146
 147         switch (phy_id) {
 148         case TN1010_PHY_ID:
 149                 phy_type = ixgbe_phy_tn;
 150                 break;
 151         case QT2022_PHY_ID:
 152                 phy_type = ixgbe_phy_qt;
 153                 break;
 154         default:
 155                 phy_type = ixgbe_phy_unknown;
 156                 break;
 157         }
 158
 159         DEBUGOUT1("phy type found is %d\n", phy_type);
 160         return phy_type;
 161 }
 162
 163 /**
 164  *  ixgbe_reset_phy_generic - Performs a PHY reset
 165  *  @hw: pointer to hardware structure
 166  **/
 167 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 168 {
 169         /*
 170          * Perform soft PHY reset to the PHY_XS.
 171          * This will cause a soft reset to the PHY
 172          */
 173         return hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 174                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
 175                                      IXGBE_MDIO_PHY_XS_RESET);
 176 }
 177
 178 /**
 179  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 180  *  @hw: pointer to hardware structure
 181  *  @reg_addr: 32 bit address of PHY register to read
 182  *  @phy_data: Pointer to read data from PHY register
 183  **/
 184 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 185                                u32 device_type, u16 *phy_data)
 186 {
 187         u32 command;
 188         u32 i;
 189         u32 data;
 190         s32 status = IXGBE_SUCCESS;
 191         u16 gssr;
 192
 193         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 194                 gssr = IXGBE_GSSR_PHY1_SM;
 195         else
 196                 gssr = IXGBE_GSSR_PHY0_SM;
 197
 198         if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
 199                 status = IXGBE_ERR_SWFW_SYNC;
 200
 201         if (status == IXGBE_SUCCESS) {
 202                 /* Setup and write the address cycle command */
 203                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 204                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 205                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 206                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 207
 208                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 209
 210                 /*
 211                  * Check every 10 usec to see if the address cycle completed.
 212                  * The MDI Command bit will clear when the operation is
 213                  * complete
 214                  */
 215                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 216                         usec_delay(10);
 217
 218                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 219
 220                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) {
 221                                 break;
 222                         }
 223                 }
 224
 225                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 226                         DEBUGOUT("PHY address command did not complete.\n");
 227                         status = IXGBE_ERR_PHY;
 228                 }
 229
 230                 if (status == IXGBE_SUCCESS) {
 231                         /*
 232                          * Address cycle complete, setup and write the read
 233                          * command
 234                          */
 235                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 236                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 237                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 238                                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 239
 240                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 241
 242                         /*
 243                          * Check every 10 usec to see if the address cycle
 244                          * completed. The MDI Command bit will clear when the
 245                          * operation is complete
 246                          */
 247                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 248                                 usec_delay(10);
 249
 250                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 251
 252                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 253                                         break;
 254                         }
 255
 256                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 257                                 DEBUGOUT("PHY read command didn't complete\n");
 258                                 status = IXGBE_ERR_PHY;
 259                         } else {
 260                                 /*
 261                                  * Read operation is complete.  Get the data
 262                                  * from MSRWD
 263                                  */
 264                                 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 265                                 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 266                                 *phy_data = (u16)(data);
 267                         }
 268                 }
 269
 270                 ixgbe_release_swfw_sync(hw, gssr);
 271         }
 272
 273         return status;
 274 }
 275
 276 /**
 277  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 278  *  @hw: pointer to hardware structure
 279  *  @reg_addr: 32 bit PHY register to write
 280  *  @device_type: 5 bit device type
 281  *  @phy_data: Data to write to the PHY register
 282  **/
 283 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 284                                 u32 device_type, u16 phy_data)
 285 {
 286         u32 command;
 287         u32 i;
 288         s32 status = IXGBE_SUCCESS;
 289         u16 gssr;
 290
 291         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 292                 gssr = IXGBE_GSSR_PHY1_SM;
 293         else
 294                 gssr = IXGBE_GSSR_PHY0_SM;
 295
 296         if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
 297                 status = IXGBE_ERR_SWFW_SYNC;
 298
 299         if (status == IXGBE_SUCCESS) {
 300                 /* Put the data in the MDI single read and write data register*/
 301                 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 302
 303                 /* Setup and write the address cycle command */
 304                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 305                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 306                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 307                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 308
 309                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 310
 311                 /*
 312                  * Check every 10 usec to see if the address cycle completed.
 313                  * The MDI Command bit will clear when the operation is
 314                  * complete
 315                  */
 316                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 317                         usec_delay(10);
 318
 319                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 320
 321                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 322                                 break;
 323                 }
 324
 325                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 326                         DEBUGOUT("PHY address cmd didn't complete\n");
 327                         status = IXGBE_ERR_PHY;
 328                 }
 329
 330                 if (status == IXGBE_SUCCESS) {
 331                         /*
 332                          * Address cycle complete, setup and write the write
 333                          * command
 334                          */
 335                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 336                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 337                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 338                                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 339
 340                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 341
 342                         /*
 343                          * Check every 10 usec to see if the address cycle
 344                          * completed. The MDI Command bit will clear when the
 345                          * operation is complete
 346                          */
 347                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 348                                 usec_delay(10);
 349
 350                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 351
 352                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 353                                         break;
 354                         }
 355
 356                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 357                                 DEBUGOUT("PHY address cmd didn't complete\n");
 358                                 status = IXGBE_ERR_PHY;
 359                         }
 360                 }
 361
 362                 ixgbe_release_swfw_sync(hw, gssr);
 363         }
 364
 365         return status;
 366 }
 367
 368 /**
 369  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 370  *  @hw: pointer to hardware structure
 371  *
 372  *  Restart autonegotiation and PHY and waits for completion.
 373  **/
 374 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 375 {
 376         s32 status = IXGBE_NOT_IMPLEMENTED;
 377         u32 time_out;
 378         u32 max_time_out = 10;
 379         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 380
 381         /*
 382          * Set advertisement settings in PHY based on autoneg_advertised
 383          * settings. If autoneg_advertised = 0, then advertise default values
 384          * tnx devices cannot be "forced" to a autoneg 10G and fail.  But can
 385          * for a 1G.
 386          */
 387         hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
 388                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 389
 390         if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
 391                 autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */
 392         else
 393                 autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */
 394
 395         hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
 396                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 397
 398         /* Restart PHY autonegotiation and wait for completion */
 399         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 400                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 401
 402         autoneg_reg |= IXGBE_MII_RESTART;
 403
 404         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 405                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 406
 407         /* Wait for autonegotiation to finish */
 408         for (time_out = 0; time_out < max_time_out; time_out++) {
 409                 usec_delay(10);
 410                 /* Restart PHY autonegotiation and wait for completion */
 411                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 412                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 413                                               &autoneg_reg);
 414
 415                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 416                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
 417                         status = IXGBE_SUCCESS;
 418                         break;
 419                 }
 420         }
 421
 422         if (time_out == max_time_out)
 423                 status = IXGBE_ERR_LINK_SETUP;
 424
 425         return status;
 426 }
 427
 428 /**
 429  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 430  *  @hw: pointer to hardware structure
 431  *  @speed: new link speed
 432  *  @autoneg: TRUE if autonegotiation enabled
 433  **/
 434 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 435                                        ixgbe_link_speed speed,
 436                                        bool autoneg,
 437                                        bool autoneg_wait_to_complete)
 438 {
 439         UNREFERENCED_PARAMETER(autoneg);
 440         UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
 441
 442         /*
 443          * Clear autoneg_advertised and set new values based on input link
 444          * speed.
 445          */
 446         hw->phy.autoneg_advertised = 0;
 447
 448         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 449                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 450         }
 451         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 452                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 453         }
 454
 455         /* Setup link based on the new speed settings */
 456         hw->phy.ops.setup_link(hw);
 457
 458         return IXGBE_SUCCESS;
 459 }
 460
 461 /**
 462  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 463  *  @hw: pointer to hardware structure
 464  *
 465  *  Reads the VS1 register to determine if link is up and the current speed for
 466  *  the PHY.
 467  **/
 468 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 469                              bool *link_up)
 470 {
 471         s32 status = IXGBE_SUCCESS;
 472         u32 time_out;
 473         u32 max_time_out = 10;
 474         u16 phy_link = 0;
 475         u16 phy_speed = 0;
 476         u16 phy_data = 0;
 477
 478         /* Initialize speed and link to default case */
 479         *link_up = FALSE;
 480         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 481
 482         /*
 483          * Check current speed and link status of the PHY register.
 484          * This is a vendor specific register and may have to
 485          * be changed for other copper PHYs.
 486          */
 487         for (time_out = 0; time_out < max_time_out; time_out++) {
 488                 usec_delay(10);
 489                 status = hw->phy.ops.read_reg(hw,
 490                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 491                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 492                                         &phy_data);
 493                 phy_link = phy_data &
 494                            IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 495                 phy_speed = phy_data &
 496                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 497                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 498                         *link_up = TRUE;
 499                         if (phy_speed ==
 500                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 501                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 502                         break;
 503                 }
 504         }
 505
 506         return status;
 507 }
 508
 509 /**
 510  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 511  *  @hw: pointer to hardware structure
 512  *  @firmware_version: pointer to the PHY Firmware Version
 513  **/
 514 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 515                                        u16 *firmware_version)
 516 {
 517         s32 status = IXGBE_SUCCESS;
 518
 519         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 520                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 521                                       firmware_version);
 522
 523         return status;
 524 }
 525