sys/dev/ixgbe/ixgbe_phy.c

   1 /******************************************************************************
   2   SPDX-License-Identifier: BSD-3-Clause
   3
   4   Copyright (c) 2001-2020, Intel Corporation
   5   All rights reserved.
   6
   7   Redistribution and use in source and binary forms, with or without
   8   modification, are permitted provided that the following conditions are met:
   9
  10    1. Redistributions of source code must retain the above copyright notice,
  11       this list of conditions and the following disclaimer.
  12
  13    2. Redistributions in binary form must reproduce the above copyright
  14       notice, this list of conditions and the following disclaimer in the
  15       documentation and/or other materials provided with the distribution.
  16
  17    3. Neither the name of the Intel Corporation nor the names of its
  18       contributors may be used to endorse or promote products derived from
  19       this software without specific prior written permission.
  20
  21   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31   POSSIBILITY OF SUCH DAMAGE.
  32
  33 ******************************************************************************/
  34 /*$FreeBSD$*/
  35
  36 #include "ixgbe_api.h"
  37 #include "ixgbe_common.h"
  38 #include "ixgbe_phy.h"
  39
  40 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  42 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  45 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  50 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  51 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  52                                           u8 *sff8472_data);
  53
  54 /**
  55  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  56  * @hw: pointer to the hardware structure
  57  * @byte: byte to send
  58  *
  59  * Returns an error code on error.
  60  */
  61 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  62 {
  63         s32 status;
  64
  65         status = ixgbe_clock_out_i2c_byte(hw, byte);
  66         if (status)
  67                 return status;
  68         return ixgbe_get_i2c_ack(hw);
  69 }
  70
  71 /**
  72  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  73  * @hw: pointer to the hardware structure
  74  * @byte: pointer to a u8 to receive the byte
  75  *
  76  * Returns an error code on error.
  77  */
  78 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  79 {
  80         s32 status;
  81
  82         status = ixgbe_clock_in_i2c_byte(hw, byte);
  83         if (status)
  84                 return status;
  85         /* ACK */
  86         return ixgbe_clock_out_i2c_bit(hw, false);
  87 }
  88
  89 /**
  90  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  91  * @add1: addend 1
  92  * @add2: addend 2
  93  *
  94  * Returns one's complement 8-bit sum.
  95  */
  96 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  97 {
  98         u16 sum = add1 + add2;
  99
 100         sum = (sum & 0xFF) + (sum >> 8);
 101         return sum & 0xFF;
 102 }
 103
 104 /**
 105  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 106  * @hw: pointer to the hardware structure
 107  * @addr: I2C bus address to read from
 108  * @reg: I2C device register to read from
 109  * @val: pointer to location to receive read value
 110  * @lock: true if to take and release semaphore
 111  *
 112  * Returns an error code on error.
 113  */
 114 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 115                                         u16 *val, bool lock)
 116 {
 117         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 118         int max_retry = 3;
 119         int retry = 0;
 120         u8 csum_byte;
 121         u8 high_bits;
 122         u8 low_bits;
 123         u8 reg_high;
 124         u8 csum;
 125
 126         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 127         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 128         csum = ~csum;
 129         do {
 130                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 131                         return IXGBE_ERR_SWFW_SYNC;
 132                 ixgbe_i2c_start(hw);
 133                 /* Device Address and write indication */
 134                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 135                         goto fail;
 136                 /* Write bits 14:8 */
 137                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 138                         goto fail;
 139                 /* Write bits 7:0 */
 140                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 141                         goto fail;
 142                 /* Write csum */
 143                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 144                         goto fail;
 145                 /* Re-start condition */
 146                 ixgbe_i2c_start(hw);
 147                 /* Device Address and read indication */
 148                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 149                         goto fail;
 150                 /* Get upper bits */
 151                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 152                         goto fail;
 153                 /* Get low bits */
 154                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 155                         goto fail;
 156                 /* Get csum */
 157                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 158                         goto fail;
 159                 /* NACK */
 160                 if (ixgbe_clock_out_i2c_bit(hw, false))
 161                         goto fail;
 162                 ixgbe_i2c_stop(hw);
 163                 if (lock)
 164                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 165                 *val = (high_bits << 8) | low_bits;
 166                 return 0;
 167
 168 fail:
 169                 ixgbe_i2c_bus_clear(hw);
 170                 if (lock)
 171                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 172                 if (retry < max_retry)
 173                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 174                 else
 175                         DEBUGOUT("I2C byte read combined error.\n");
 176                 retry++;
 177         } while (retry <= max_retry);
 178
 179         return IXGBE_ERR_I2C;
 180 }
 181
 182 /**
 183  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 184  * @hw: pointer to the hardware structure
 185  * @addr: I2C bus address to write to
 186  * @reg: I2C device register to write to
 187  * @val: value to write
 188  * @lock: true if to take and release semaphore
 189  *
 190  * Returns an error code on error.
 191  */
 192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 193                                          u16 val, bool lock)
 194 {
 195         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 196         int max_retry = 1;
 197         int retry = 0;
 198         u8 reg_high;
 199         u8 csum;
 200
 201         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 202         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 203         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 204         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 205         csum = ~csum;
 206         do {
 207                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 208                         return IXGBE_ERR_SWFW_SYNC;
 209                 ixgbe_i2c_start(hw);
 210                 /* Device Address and write indication */
 211                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 212                         goto fail;
 213                 /* Write bits 14:8 */
 214                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 215                         goto fail;
 216                 /* Write bits 7:0 */
 217                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 218                         goto fail;
 219                 /* Write data 15:8 */
 220                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 221                         goto fail;
 222                 /* Write data 7:0 */
 223                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 224                         goto fail;
 225                 /* Write csum */
 226                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 227                         goto fail;
 228                 ixgbe_i2c_stop(hw);
 229                 if (lock)
 230                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 231                 return 0;
 232
 233 fail:
 234                 ixgbe_i2c_bus_clear(hw);
 235                 if (lock)
 236                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 237                 if (retry < max_retry)
 238                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 239                 else
 240                         DEBUGOUT("I2C byte write combined error.\n");
 241                 retry++;
 242         } while (retry <= max_retry);
 243
 244         return IXGBE_ERR_I2C;
 245 }
 246
 247 /**
 248  * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 249  * @hw: pointer to the hardware structure
 250  *
 251  * Initialize the function pointers.
 252  **/
 253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 254 {
 255         struct ixgbe_phy_info *phy = &hw->phy;
 256
 257         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 258
 259         /* PHY */
 260         phy->ops.identify = ixgbe_identify_phy_generic;
 261         phy->ops.reset = ixgbe_reset_phy_generic;
 262         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 263         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 264         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 265         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 266         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 267         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 268         phy->ops.check_link = NULL;
 269         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 270         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 271         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 272         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 273         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 274         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 275         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 276         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 277         phy->sfp_type = ixgbe_sfp_type_unknown;
 278         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 279         phy->ops.write_i2c_byte_unlocked =
 280                                 ixgbe_write_i2c_byte_generic_unlocked;
 281         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 282         return IXGBE_SUCCESS;
 283 }
 284
 285 /**
 286  * ixgbe_probe_phy - Probe a single address for a PHY
 287  * @hw: pointer to hardware structure
 288  * @phy_addr: PHY address to probe
 289  *
 290  * Returns true if PHY found
 291  */
 292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 293 {
 294         u16 ext_ability = 0;
 295
 296         if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
 297                 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
 298                         phy_addr);
 299                 return false;
 300         }
 301
 302         if (ixgbe_get_phy_id(hw))
 303                 return false;
 304
 305         hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 306
 307         if (hw->phy.type == ixgbe_phy_unknown) {
 308                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 309                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 310                 if (ext_ability &
 311                     (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 312                      IXGBE_MDIO_PHY_1000BASET_ABILITY))
 313                         hw->phy.type = ixgbe_phy_cu_unknown;
 314                 else
 315                         hw->phy.type = ixgbe_phy_generic;
 316         }
 317
 318         return true;
 319 }
 320
 321 /**
 322  * ixgbe_identify_phy_generic - Get physical layer module
 323  * @hw: pointer to hardware structure
 324  *
 325  * Determines the physical layer module found on the current adapter.
 326  **/
 327 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 328 {
 329         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 330         u16 phy_addr;
 331
 332         DEBUGFUNC("ixgbe_identify_phy_generic");
 333
 334         if (!hw->phy.phy_semaphore_mask) {
 335                 if (hw->bus.lan_id)
 336                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 337                 else
 338                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 339         }
 340
 341         if (hw->phy.type != ixgbe_phy_unknown)
 342                 return IXGBE_SUCCESS;
 343
 344         if (hw->phy.nw_mng_if_sel) {
 345                 phy_addr = (hw->phy.nw_mng_if_sel &
 346                             IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 347                            IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 348                 if (ixgbe_probe_phy(hw, phy_addr))
 349                         return IXGBE_SUCCESS;
 350                 else
 351                         return IXGBE_ERR_PHY_ADDR_INVALID;
 352         }
 353
 354         for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 355                 if (ixgbe_probe_phy(hw, phy_addr)) {
 356                         status = IXGBE_SUCCESS;
 357                         break;
 358                 }
 359         }
 360
 361         /* Certain media types do not have a phy so an address will not
 362          * be found and the code will take this path.  Caller has to
 363          * decide if it is an error or not.
 364          */
 365         if (status != IXGBE_SUCCESS)
 366                 hw->phy.addr = 0;
 367
 368         return status;
 369 }
 370
 371 /**
 372  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 373  * @hw: pointer to the hardware structure
 374  *
 375  * This function checks the MMNGC.MNG_VETO bit to see if there are
 376  * any constraints on link from manageability.  For MAC's that don't
 377  * have this bit just return faluse since the link can not be blocked
 378  * via this method.
 379  **/
 380 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 381 {
 382         u32 mmngc;
 383
 384         DEBUGFUNC("ixgbe_check_reset_blocked");
 385
 386         /* If we don't have this bit, it can't be blocking */
 387         if (hw->mac.type == ixgbe_mac_82598EB)
 388                 return false;
 389
 390         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 391         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 392                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 393                               "MNG_VETO bit detected.\n");
 394                 return true;
 395         }
 396
 397         return false;
 398 }
 399
 400 /**
 401  * ixgbe_validate_phy_addr - Determines phy address is valid
 402  * @hw: pointer to hardware structure
 403  * @phy_addr: PHY address
 404  *
 405  **/
 406 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 407 {
 408         u16 phy_id = 0;
 409         bool valid = false;
 410
 411         DEBUGFUNC("ixgbe_validate_phy_addr");
 412
 413         hw->phy.addr = phy_addr;
 414         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 415                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 416
 417         if (phy_id != 0xFFFF && phy_id != 0x0)
 418                 valid = true;
 419
 420         DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
 421
 422         return valid;
 423 }
 424
 425 /**
 426  * ixgbe_get_phy_id - Get the phy type
 427  * @hw: pointer to hardware structure
 428  *
 429  **/
 430 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 431 {
 432         u32 status;
 433         u16 phy_id_high = 0;
 434         u16 phy_id_low = 0;
 435
 436         DEBUGFUNC("ixgbe_get_phy_id");
 437
 438         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 439                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 440                                       &phy_id_high);
 441
 442         if (status == IXGBE_SUCCESS) {
 443                 hw->phy.id = (u32)(phy_id_high << 16);
 444                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 445                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 446                                               &phy_id_low);
 447                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 448                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 449         }
 450         DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
 451                   phy_id_high, phy_id_low);
 452
 453         return status;
 454 }
 455
 456 /**
 457  * ixgbe_get_phy_type_from_id - Get the phy type
 458  * @phy_id: PHY ID information
 459  *
 460  **/
 461 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 462 {
 463         enum ixgbe_phy_type phy_type;
 464
 465         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 466
 467         switch (phy_id) {
 468         case TN1010_PHY_ID:
 469                 phy_type = ixgbe_phy_tn;
 470                 break;
 471         case X550_PHY_ID2:
 472         case X550_PHY_ID3:
 473         case X540_PHY_ID:
 474                 phy_type = ixgbe_phy_aq;
 475                 break;
 476         case QT2022_PHY_ID:
 477                 phy_type = ixgbe_phy_qt;
 478                 break;
 479         case ATH_PHY_ID:
 480                 phy_type = ixgbe_phy_nl;
 481                 break;
 482         case X557_PHY_ID:
 483         case X557_PHY_ID2:
 484                 phy_type = ixgbe_phy_x550em_ext_t;
 485                 break;
 486         case IXGBE_M88E1500_E_PHY_ID:
 487         case IXGBE_M88E1543_E_PHY_ID:
 488                 phy_type = ixgbe_phy_ext_1g_t;
 489                 break;
 490         default:
 491                 phy_type = ixgbe_phy_unknown;
 492                 break;
 493         }
 494         return phy_type;
 495 }
 496
 497 /**
 498  * ixgbe_reset_phy_generic - Performs a PHY reset
 499  * @hw: pointer to hardware structure
 500  **/
 501 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 502 {
 503         u32 i;
 504         u16 ctrl = 0;
 505         s32 status = IXGBE_SUCCESS;
 506
 507         DEBUGFUNC("ixgbe_reset_phy_generic");
 508
 509         if (hw->phy.type == ixgbe_phy_unknown)
 510                 status = ixgbe_identify_phy_generic(hw);
 511
 512         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 513                 goto out;
 514
 515         /* Don't reset PHY if it's shut down due to overtemp. */
 516         if (!hw->phy.reset_if_overtemp &&
 517             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 518                 goto out;
 519
 520         /* Blocked by MNG FW so bail */
 521         if (ixgbe_check_reset_blocked(hw))
 522                 goto out;
 523
 524         /*
 525          * Perform soft PHY reset to the PHY_XS.
 526          * This will cause a soft reset to the PHY
 527          */
 528         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 529                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 530                               IXGBE_MDIO_PHY_XS_RESET);
 531
 532         /*
 533          * Poll for reset bit to self-clear indicating reset is complete.
 534          * Some PHYs could take up to 3 seconds to complete and need about
 535          * 1.7 usec delay after the reset is complete.
 536          */
 537         for (i = 0; i < 30; i++) {
 538                 msec_delay(100);
 539                 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
 540                         status = hw->phy.ops.read_reg(hw,
 541                                                   IXGBE_MDIO_TX_VENDOR_ALARMS_3,
 542                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 543                                                   &ctrl);
 544                         if (status != IXGBE_SUCCESS)
 545                                 return status;
 546
 547                         if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
 548                                 usec_delay(2);
 549                                 break;
 550                         }
 551                 } else {
 552                         status = hw->phy.ops.read_reg(hw,
 553                                                      IXGBE_MDIO_PHY_XS_CONTROL,
 554                                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
 555                                                      &ctrl);
 556                         if (status != IXGBE_SUCCESS)
 557                                 return status;
 558
 559                         if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 560                                 usec_delay(2);
 561                                 break;
 562                         }
 563                 }
 564         }
 565
 566         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 567                 status = IXGBE_ERR_RESET_FAILED;
 568                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 569                              "PHY reset polling failed to complete.\n");
 570         }
 571
 572 out:
 573         return status;
 574 }
 575
 576 /**
 577  * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY
 578  * @hw: pointer to hardware structure
 579  **/
 580 void ixgbe_restart_auto_neg(struct ixgbe_hw *hw)
 581 {
 582         u16 autoneg_reg;
 583
 584         /* Check if PHY reset is blocked by MNG FW */
 585         if (ixgbe_check_reset_blocked(hw))
 586                 return;
 587
 588         /* Restart PHY auto-negotiation. */
 589         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 590                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 591         autoneg_reg |= IXGBE_MII_RESTART;
 592         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 593                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 594 }
 595
 596 /**
 597  * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 598  * the SWFW lock
 599  * @hw: pointer to hardware structure
 600  * @reg_addr: 32 bit address of PHY register to read
 601  * @device_type: 5 bit device type
 602  * @phy_data: Pointer to read data from PHY register
 603  **/
 604 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 605                            u16 *phy_data)
 606 {
 607         u32 i, data, command;
 608
 609         /* Setup and write the address cycle command */
 610         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 611                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 612                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 613                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 614
 615         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 616
 617         /*
 618          * Check every 10 usec to see if the address cycle completed.
 619          * The MDI Command bit will clear when the operation is
 620          * complete
 621          */
 622         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 623                 usec_delay(10);
 624
 625                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 626                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 627                         break;
 628         }
 629
 630
 631         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 632                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 633                 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
 634                 return IXGBE_ERR_PHY;
 635         }
 636
 637         /*
 638          * Address cycle complete, setup and write the read
 639          * command
 640          */
 641         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 642                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 643                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 644                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 645
 646         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 647
 648         /*
 649          * Check every 10 usec to see if the address cycle
 650          * completed. The MDI Command bit will clear when the
 651          * operation is complete
 652          */
 653         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 654                 usec_delay(10);
 655
 656                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 657                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 658                         break;
 659         }
 660
 661         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 662                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 663                 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
 664                 return IXGBE_ERR_PHY;
 665         }
 666
 667         /*
 668          * Read operation is complete.  Get the data
 669          * from MSRWD
 670          */
 671         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 672         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 673         *phy_data = (u16)(data);
 674
 675         return IXGBE_SUCCESS;
 676 }
 677
 678 /**
 679  * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 680  * using the SWFW lock - this function is needed in most cases
 681  * @hw: pointer to hardware structure
 682  * @reg_addr: 32 bit address of PHY register to read
 683  * @device_type: 5 bit device type
 684  * @phy_data: Pointer to read data from PHY register
 685  **/
 686 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 687                                u32 device_type, u16 *phy_data)
 688 {
 689         s32 status;
 690         u32 gssr = hw->phy.phy_semaphore_mask;
 691
 692         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 693
 694         if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 695                 return IXGBE_ERR_SWFW_SYNC;
 696
 697         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
 698
 699         hw->mac.ops.release_swfw_sync(hw, gssr);
 700
 701         return status;
 702 }
 703
 704 /**
 705  * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 706  * without SWFW lock
 707  * @hw: pointer to hardware structure
 708  * @reg_addr: 32 bit PHY register to write
 709  * @device_type: 5 bit device type
 710  * @phy_data: Data to write to the PHY register
 711  **/
 712 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 713                                 u32 device_type, u16 phy_data)
 714 {
 715         u32 i, command;
 716
 717         /* Put the data in the MDI single read and write data register*/
 718         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 719
 720         /* Setup and write the address cycle command */
 721         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 722                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 723                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 724                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 725
 726         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 727
 728         /*
 729          * Check every 10 usec to see if the address cycle completed.
 730          * The MDI Command bit will clear when the operation is
 731          * complete
 732          */
 733         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 734                 usec_delay(10);
 735
 736                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 737                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 738                         break;
 739         }
 740
 741         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 742                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 743                 return IXGBE_ERR_PHY;
 744         }
 745
 746         /*
 747          * Address cycle complete, setup and write the write
 748          * command
 749          */
 750         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 751                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 752                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 753                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 754
 755         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 756
 757         /*
 758          * Check every 10 usec to see if the address cycle
 759          * completed. The MDI Command bit will clear when the
 760          * operation is complete
 761          */
 762         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 763                 usec_delay(10);
 764
 765                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 766                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 767                         break;
 768         }
 769
 770         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 771                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 772                 return IXGBE_ERR_PHY;
 773         }
 774
 775         return IXGBE_SUCCESS;
 776 }
 777
 778 /**
 779  * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 780  * using SWFW lock- this function is needed in most cases
 781  * @hw: pointer to hardware structure
 782  * @reg_addr: 32 bit PHY register to write
 783  * @device_type: 5 bit device type
 784  * @phy_data: Data to write to the PHY register
 785  **/
 786 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 787                                 u32 device_type, u16 phy_data)
 788 {
 789         s32 status;
 790         u32 gssr = hw->phy.phy_semaphore_mask;
 791
 792         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 793
 794         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 795                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
 796                                                  phy_data);
 797                 hw->mac.ops.release_swfw_sync(hw, gssr);
 798         } else {
 799                 status = IXGBE_ERR_SWFW_SYNC;
 800         }
 801
 802         return status;
 803 }
 804
 805 /**
 806  * ixgbe_setup_phy_link_generic - Set and restart auto-neg
 807  * @hw: pointer to hardware structure
 808  *
 809  * Restart auto-negotiation and PHY and waits for completion.
 810  **/
 811 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 812 {
 813         s32 status = IXGBE_SUCCESS;
 814         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 815         bool autoneg = false;
 816         ixgbe_link_speed speed;
 817
 818         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 819
 820         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 821
 822         /* Set or unset auto-negotiation 10G advertisement */
 823         hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 824                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 825                              &autoneg_reg);
 826
 827         autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 828         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
 829             (speed & IXGBE_LINK_SPEED_10GB_FULL))
 830                 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 831
 832         hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 833                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 834                               autoneg_reg);
 835
 836         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 837                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 838                              &autoneg_reg);
 839
 840         if (hw->mac.type == ixgbe_mac_X550) {
 841                 /* Set or unset auto-negotiation 5G advertisement */
 842                 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 843                 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
 844                     (speed & IXGBE_LINK_SPEED_5GB_FULL))
 845                         autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 846
 847                 /* Set or unset auto-negotiation 2.5G advertisement */
 848                 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 849                 if ((hw->phy.autoneg_advertised &
 850                      IXGBE_LINK_SPEED_2_5GB_FULL) &&
 851                     (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
 852                         autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 853         }
 854
 855         /* Set or unset auto-negotiation 1G advertisement */
 856         autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 857         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
 858             (speed & IXGBE_LINK_SPEED_1GB_FULL))
 859                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 860
 861         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 862                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 863                               autoneg_reg);
 864
 865         /* Set or unset auto-negotiation 100M advertisement */
 866         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 867                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 868                              &autoneg_reg);
 869
 870         autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 871                          IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 872         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
 873             (speed & IXGBE_LINK_SPEED_100_FULL))
 874                 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 875
 876         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 877                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 878                               autoneg_reg);
 879
 880         ixgbe_restart_auto_neg(hw);
 881         return status;
 882 }
 883
 884 /**
 885  * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 886  * @hw: pointer to hardware structure
 887  * @speed: new link speed
 888  * @autoneg_wait_to_complete: unused
 889  **/
 890 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 891                                        ixgbe_link_speed speed,
 892                                        bool autoneg_wait_to_complete)
 893 {
 894         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 895
 896         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 897
 898         /*
 899          * Clear autoneg_advertised and set new values based on input link
 900          * speed.
 901          */
 902         hw->phy.autoneg_advertised = 0;
 903
 904         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 905                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 906
 907         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 908                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 909
 910         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 911                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 912
 913         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 914                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 915
 916         if (speed & IXGBE_LINK_SPEED_100_FULL)
 917                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 918
 919         if (speed & IXGBE_LINK_SPEED_10_FULL)
 920                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
 921
 922         /* Setup link based on the new speed settings */
 923         ixgbe_setup_phy_link(hw);
 924
 925         return IXGBE_SUCCESS;
 926 }
 927
 928 /**
 929  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 930  * @hw: pointer to hardware structure
 931  *
 932  * Determines the supported link capabilities by reading the PHY auto
 933  * negotiation register.
 934  **/
 935 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 936 {
 937         s32 status;
 938         u16 speed_ability;
 939
 940         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 941                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 942                                       &speed_ability);
 943         if (status)
 944                 return status;
 945
 946         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 947                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 948         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 949                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 950         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 951                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 952
 953         switch (hw->mac.type) {
 954         case ixgbe_mac_X550:
 955                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 956                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 957                 break;
 958         case ixgbe_mac_X550EM_x:
 959         case ixgbe_mac_X550EM_a:
 960                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 961                 break;
 962         default:
 963                 break;
 964         }
 965
 966         return status;
 967 }
 968
 969 /**
 970  * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 971  * @hw: pointer to hardware structure
 972  * @speed: pointer to link speed
 973  * @autoneg: boolean auto-negotiation value
 974  **/
 975 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 976                                                ixgbe_link_speed *speed,
 977                                                bool *autoneg)
 978 {
 979         s32 status = IXGBE_SUCCESS;
 980
 981         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 982
 983         *autoneg = true;
 984         if (!hw->phy.speeds_supported)
 985                 status = ixgbe_get_copper_speeds_supported(hw);
 986
 987         *speed = hw->phy.speeds_supported;
 988         return status;
 989 }
 990
 991 /**
 992  * ixgbe_check_phy_link_tnx - Determine link and speed status
 993  * @hw: pointer to hardware structure
 994  * @speed: current link speed
 995  * @link_up: true is link is up, false otherwise
 996  *
 997  * Reads the VS1 register to determine if link is up and the current speed for
 998  * the PHY.
 999  **/
1000 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1001                              bool *link_up)
1002 {
1003         s32 status = IXGBE_SUCCESS;
1004         u32 time_out;
1005         u32 max_time_out = 10;
1006         u16 phy_link = 0;
1007         u16 phy_speed = 0;
1008         u16 phy_data = 0;
1009
1010         DEBUGFUNC("ixgbe_check_phy_link_tnx");
1011
1012         /* Initialize speed and link to default case */
1013         *link_up = false;
1014         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1015
1016         /*
1017          * Check current speed and link status of the PHY register.
1018          * This is a vendor specific register and may have to
1019          * be changed for other copper PHYs.
1020          */
1021         for (time_out = 0; time_out < max_time_out; time_out++) {
1022                 usec_delay(10);
1023                 status = hw->phy.ops.read_reg(hw,
1024                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1025                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1026                                         &phy_data);
1027                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1028                 phy_speed = phy_data &
1029                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1030                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1031                         *link_up = true;
1032                         if (phy_speed ==
1033                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1034                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1035                         break;
1036                 }
1037         }
1038
1039         return status;
1040 }
1041
1042 /**
1043  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1044  *      @hw: pointer to hardware structure
1045  *
1046  *      Restart auto-negotiation and PHY and waits for completion.
1047  **/
1048 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1049 {
1050         s32 status = IXGBE_SUCCESS;
1051         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1052         bool autoneg = false;
1053         ixgbe_link_speed speed;
1054
1055         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1056
1057         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1058
1059         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1060                 /* Set or unset auto-negotiation 10G advertisement */
1061                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1062                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1063                                      &autoneg_reg);
1064
1065                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1066                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1067                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1068
1069                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1070                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1071                                       autoneg_reg);
1072         }
1073
1074         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1075                 /* Set or unset auto-negotiation 1G advertisement */
1076                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1077                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1078                                      &autoneg_reg);
1079
1080                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1081                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1082                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1083
1084                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1085                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1086                                       autoneg_reg);
1087         }
1088
1089         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1090                 /* Set or unset auto-negotiation 100M advertisement */
1091                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1092                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1093                                      &autoneg_reg);
1094
1095                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1096                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1097                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1098
1099                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1100                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1101                                       autoneg_reg);
1102         }
1103
1104         ixgbe_restart_auto_neg(hw);
1105         return status;
1106 }
1107
1108 /**
1109  * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1110  * @hw: pointer to hardware structure
1111  * @firmware_version: pointer to the PHY Firmware Version
1112  **/
1113 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1114                                        u16 *firmware_version)
1115 {
1116         s32 status;
1117
1118         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1119
1120         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1121                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1122                                       firmware_version);
1123
1124         return status;
1125 }
1126
1127 /**
1128  * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1129  * @hw: pointer to hardware structure
1130  * @firmware_version: pointer to the PHY Firmware Version
1131  **/
1132 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1133                                            u16 *firmware_version)
1134 {
1135         s32 status;
1136
1137         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1138
1139         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1140                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1141                                       firmware_version);
1142
1143         return status;
1144 }
1145
1146 /**
1147  * ixgbe_reset_phy_nl - Performs a PHY reset
1148  * @hw: pointer to hardware structure
1149  **/
1150 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1151 {
1152         u16 phy_offset, control, eword, edata, block_crc;
1153         bool end_data = false;
1154         u16 list_offset, data_offset;
1155         u16 phy_data = 0;
1156         s32 ret_val = IXGBE_SUCCESS;
1157         u32 i;
1158
1159         DEBUGFUNC("ixgbe_reset_phy_nl");
1160
1161         /* Blocked by MNG FW so bail */
1162         if (ixgbe_check_reset_blocked(hw))
1163                 goto out;
1164
1165         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1166                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1167
1168         /* reset the PHY and poll for completion */
1169         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1170                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1171                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1172
1173         for (i = 0; i < 100; i++) {
1174                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1175                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1176                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1177                         break;
1178                 msec_delay(10);
1179         }
1180
1181         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1182                 DEBUGOUT("PHY reset did not complete.\n");
1183                 ret_val = IXGBE_ERR_PHY;
1184                 goto out;
1185         }
1186
1187         /* Get init offsets */
1188         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1189                                                       &data_offset);
1190         if (ret_val != IXGBE_SUCCESS)
1191                 goto out;
1192
1193         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1194         data_offset++;
1195         while (!end_data) {
1196                 /*
1197                  * Read control word from PHY init contents offset
1198                  */
1199                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1200                 if (ret_val)
1201                         goto err_eeprom;
1202                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1203                            IXGBE_CONTROL_SHIFT_NL;
1204                 edata = eword & IXGBE_DATA_MASK_NL;
1205                 switch (control) {
1206                 case IXGBE_DELAY_NL:
1207                         data_offset++;
1208                         DEBUGOUT1("DELAY: %d MS\n", edata);
1209                         msec_delay(edata);
1210                         break;
1211                 case IXGBE_DATA_NL:
1212                         DEBUGOUT("DATA:\n");
1213                         data_offset++;
1214                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1215                                                       &phy_offset);
1216                         if (ret_val)
1217                                 goto err_eeprom;
1218                         data_offset++;
1219                         for (i = 0; i < edata; i++) {
1220                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1221                                                               &eword);
1222                                 if (ret_val)
1223                                         goto err_eeprom;
1224                                 hw->phy.ops.write_reg(hw, phy_offset,
1225                                                       IXGBE_TWINAX_DEV, eword);
1226                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1227                                           phy_offset);
1228                                 data_offset++;
1229                                 phy_offset++;
1230                         }
1231                         break;
1232                 case IXGBE_CONTROL_NL:
1233                         data_offset++;
1234                         DEBUGOUT("CONTROL:\n");
1235                         if (edata == IXGBE_CONTROL_EOL_NL) {
1236                                 DEBUGOUT("EOL\n");
1237                                 end_data = true;
1238                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1239                                 DEBUGOUT("SOL\n");
1240                         } else {
1241                                 DEBUGOUT("Bad control value\n");
1242                                 ret_val = IXGBE_ERR_PHY;
1243                                 goto out;
1244                         }
1245                         break;
1246                 default:
1247                         DEBUGOUT("Bad control type\n");
1248                         ret_val = IXGBE_ERR_PHY;
1249                         goto out;
1250                 }
1251         }
1252
1253 out:
1254         return ret_val;
1255
1256 err_eeprom:
1257         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1258                       "eeprom read at offset %d failed", data_offset);
1259         return IXGBE_ERR_PHY;
1260 }
1261
1262 /**
1263  * ixgbe_identify_module_generic - Identifies module type
1264  * @hw: pointer to hardware structure
1265  *
1266  * Determines HW type and calls appropriate function.
1267  **/
1268 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1269 {
1270         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1271
1272         DEBUGFUNC("ixgbe_identify_module_generic");
1273
1274         switch (hw->mac.ops.get_media_type(hw)) {
1275         case ixgbe_media_type_fiber:
1276                 status = ixgbe_identify_sfp_module_generic(hw);
1277                 break;
1278
1279         case ixgbe_media_type_fiber_qsfp:
1280                 status = ixgbe_identify_qsfp_module_generic(hw);
1281                 break;
1282
1283         default:
1284                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1285                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1286                 break;
1287         }
1288
1289         return status;
1290 }
1291
1292 /**
1293  * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1294  * @hw: pointer to hardware structure
1295  *
1296  * Searches for and identifies the SFP module and assigns appropriate PHY type.
1297  **/
1298 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1299 {
1300         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1301         u32 vendor_oui = 0;
1302         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1303         u8 identifier = 0;
1304         u8 comp_codes_1g = 0;
1305         u8 comp_codes_10g = 0;
1306         u8 oui_bytes[3] = {0, 0, 0};
1307         u8 cable_tech = 0;
1308         u8 cable_spec = 0;
1309         u16 enforce_sfp = 0;
1310
1311         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1312
1313         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1314                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1315                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1316                 goto out;
1317         }
1318
1319         /* LAN ID is needed for I2C access */
1320         hw->mac.ops.set_lan_id(hw);
1321
1322         status = hw->phy.ops.read_i2c_eeprom(hw,
1323                                              IXGBE_SFF_IDENTIFIER,
1324                                              &identifier);
1325
1326         if (status != IXGBE_SUCCESS)
1327                 goto err_read_i2c_eeprom;
1328
1329         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1330                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1331                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1332         } else {
1333                 status = hw->phy.ops.read_i2c_eeprom(hw,
1334                                                      IXGBE_SFF_1GBE_COMP_CODES,
1335                                                      &comp_codes_1g);
1336
1337                 if (status != IXGBE_SUCCESS)
1338                         goto err_read_i2c_eeprom;
1339
1340                 status = hw->phy.ops.read_i2c_eeprom(hw,
1341                                                      IXGBE_SFF_10GBE_COMP_CODES,
1342                                                      &comp_codes_10g);
1343
1344                 if (status != IXGBE_SUCCESS)
1345                         goto err_read_i2c_eeprom;
1346                 status = hw->phy.ops.read_i2c_eeprom(hw,
1347                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1348                                                      &cable_tech);
1349
1350                 if (status != IXGBE_SUCCESS)
1351                         goto err_read_i2c_eeprom;
1352
1353                  /* ID Module
1354                   * =========
1355                   * 0   SFP_DA_CU
1356                   * 1   SFP_SR
1357                   * 2   SFP_LR
1358                   * 3   SFP_DA_CORE0 - 82599-specific
1359                   * 4   SFP_DA_CORE1 - 82599-specific
1360                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1361                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1362                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1363                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1364                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1365                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1366                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1367                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1368                   */
1369                 if (hw->mac.type == ixgbe_mac_82598EB) {
1370                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1371                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1372                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1373                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1374                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1375                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1376                         else
1377                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1378                 } else {
1379                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1380                                 if (hw->bus.lan_id == 0)
1381                                         hw->phy.sfp_type =
1382                                                      ixgbe_sfp_type_da_cu_core0;
1383                                 else
1384                                         hw->phy.sfp_type =
1385                                                      ixgbe_sfp_type_da_cu_core1;
1386                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1387                                 hw->phy.ops.read_i2c_eeprom(
1388                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1389                                                 &cable_spec);
1390                                 if (cable_spec &
1391                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1392                                         if (hw->bus.lan_id == 0)
1393                                                 hw->phy.sfp_type =
1394                                                 ixgbe_sfp_type_da_act_lmt_core0;
1395                                         else
1396                                                 hw->phy.sfp_type =
1397                                                 ixgbe_sfp_type_da_act_lmt_core1;
1398                                 } else {
1399                                         hw->phy.sfp_type =
1400                                                         ixgbe_sfp_type_unknown;
1401                                 }
1402                         } else if (comp_codes_10g &
1403                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1404                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1405                                 if (hw->bus.lan_id == 0)
1406                                         hw->phy.sfp_type =
1407                                                       ixgbe_sfp_type_srlr_core0;
1408                                 else
1409                                         hw->phy.sfp_type =
1410                                                       ixgbe_sfp_type_srlr_core1;
1411                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1412                                 if (hw->bus.lan_id == 0)
1413                                         hw->phy.sfp_type =
1414                                                 ixgbe_sfp_type_1g_cu_core0;
1415                                 else
1416                                         hw->phy.sfp_type =
1417                                                 ixgbe_sfp_type_1g_cu_core1;
1418                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1419                                 if (hw->bus.lan_id == 0)
1420                                         hw->phy.sfp_type =
1421                                                 ixgbe_sfp_type_1g_sx_core0;
1422                                 else
1423                                         hw->phy.sfp_type =
1424                                                 ixgbe_sfp_type_1g_sx_core1;
1425                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1426                                 if (hw->bus.lan_id == 0)
1427                                         hw->phy.sfp_type =
1428                                                 ixgbe_sfp_type_1g_lx_core0;
1429                                 else
1430                                         hw->phy.sfp_type =
1431                                                 ixgbe_sfp_type_1g_lx_core1;
1432                         } else {
1433                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1434                         }
1435                 }
1436
1437                 if (hw->phy.sfp_type != stored_sfp_type)
1438                         hw->phy.sfp_setup_needed = true;
1439
1440                 /* Determine if the SFP+ PHY is dual speed or not. */
1441                 hw->phy.multispeed_fiber = false;
1442                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1443                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1444                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1445                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1446                         hw->phy.multispeed_fiber = true;
1447
1448                 /* Determine PHY vendor */
1449                 if (hw->phy.type != ixgbe_phy_nl) {
1450                         hw->phy.id = identifier;
1451                         status = hw->phy.ops.read_i2c_eeprom(hw,
1452                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1453                                                     &oui_bytes[0]);
1454
1455                         if (status != IXGBE_SUCCESS)
1456                                 goto err_read_i2c_eeprom;
1457
1458                         status = hw->phy.ops.read_i2c_eeprom(hw,
1459                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1460                                                     &oui_bytes[1]);
1461
1462                         if (status != IXGBE_SUCCESS)
1463                                 goto err_read_i2c_eeprom;
1464
1465                         status = hw->phy.ops.read_i2c_eeprom(hw,
1466                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1467                                                     &oui_bytes[2]);
1468
1469                         if (status != IXGBE_SUCCESS)
1470                                 goto err_read_i2c_eeprom;
1471
1472                         vendor_oui =
1473                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1474                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1475                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1476
1477                         switch (vendor_oui) {
1478                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1479                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1480                                         hw->phy.type =
1481                                                     ixgbe_phy_sfp_passive_tyco;
1482                                 break;
1483                         case IXGBE_SFF_VENDOR_OUI_FTL:
1484                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1485                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1486                                 else
1487                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1488                                 break;
1489                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1490                                 hw->phy.type = ixgbe_phy_sfp_avago;
1491                                 break;
1492                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1493                                 hw->phy.type = ixgbe_phy_sfp_intel;
1494                                 break;
1495                         default:
1496                                 hw->phy.type = ixgbe_phy_sfp_unknown;
1497                                 break;
1498                         }
1499                 }
1500
1501                 /* Allow any DA cable vendor */
1502                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1503                         IXGBE_SFF_DA_ACTIVE_CABLE)) {
1504                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1505                                 hw->phy.type = ixgbe_phy_sfp_passive_unknown;
1506                         else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1507                                 hw->phy.type = ixgbe_phy_sfp_active_unknown;
1508                         status = IXGBE_SUCCESS;
1509                         goto out;
1510                 }
1511
1512                 /* Verify supported 1G SFP modules */
1513                 if (comp_codes_10g == 0 &&
1514                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1515                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1516                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1517                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1518                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1519                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1520                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1521                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1522                         goto out;
1523                 }
1524
1525                 /* Anything else 82598-based is supported */
1526                 if (hw->mac.type == ixgbe_mac_82598EB) {
1527                         status = IXGBE_SUCCESS;
1528                         goto out;
1529                 }
1530
1531                 ixgbe_get_device_caps(hw, &enforce_sfp);
1532                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1533                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1534                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1535                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1536                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1537                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1538                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1539                         /* Make sure we're a supported PHY type */
1540                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1541                                 status = IXGBE_SUCCESS;
1542                         } else {
1543                                 if (hw->allow_unsupported_sfp == true) {
1544                                         EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1545                                         status = IXGBE_SUCCESS;
1546                                 } else {
1547                                         DEBUGOUT("SFP+ module not supported\n");
1548                                         hw->phy.type =
1549                                                 ixgbe_phy_sfp_unsupported;
1550                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1551                                 }
1552                         }
1553                 } else {
1554                         status = IXGBE_SUCCESS;
1555                 }
1556         }
1557
1558 out:
1559         return status;
1560
1561 err_read_i2c_eeprom:
1562         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1563         if (hw->phy.type != ixgbe_phy_nl) {
1564                 hw->phy.id = 0;
1565                 hw->phy.type = ixgbe_phy_unknown;
1566         }
1567         return IXGBE_ERR_SFP_NOT_PRESENT;
1568 }
1569
1570 /**
1571  * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1572  * @hw: pointer to hardware structure
1573  *
1574  * Determines physical layer capabilities of the current SFP.
1575  */
1576 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1577 {
1578         u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1579         u8 comp_codes_10g = 0;
1580         u8 comp_codes_1g = 0;
1581
1582         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1583
1584         hw->phy.ops.identify_sfp(hw);
1585         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1586                 return physical_layer;
1587
1588         switch (hw->phy.type) {
1589         case ixgbe_phy_sfp_passive_tyco:
1590         case ixgbe_phy_sfp_passive_unknown:
1591         case ixgbe_phy_qsfp_passive_unknown:
1592                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1593                 break;
1594         case ixgbe_phy_sfp_ftl_active:
1595         case ixgbe_phy_sfp_active_unknown:
1596         case ixgbe_phy_qsfp_active_unknown:
1597                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1598                 break;
1599         case ixgbe_phy_sfp_avago:
1600         case ixgbe_phy_sfp_ftl:
1601         case ixgbe_phy_sfp_intel:
1602         case ixgbe_phy_sfp_unknown:
1603                 hw->phy.ops.read_i2c_eeprom(hw,
1604                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1605                 hw->phy.ops.read_i2c_eeprom(hw,
1606                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1607                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1608                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1609                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1610                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1611                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1612                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1613                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1614                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1615                 break;
1616         case ixgbe_phy_qsfp_intel:
1617         case ixgbe_phy_qsfp_unknown:
1618                 hw->phy.ops.read_i2c_eeprom(hw,
1619                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1620                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1621                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1622                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1623                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1624                 break;
1625         default:
1626                 break;
1627         }
1628
1629         return physical_layer;
1630 }
1631
1632 /**
1633  * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1634  * @hw: pointer to hardware structure
1635  *
1636  * Searches for and identifies the QSFP module and assigns appropriate PHY type
1637  **/
1638 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1639 {
1640         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1641         u32 vendor_oui = 0;
1642         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1643         u8 identifier = 0;
1644         u8 comp_codes_1g = 0;
1645         u8 comp_codes_10g = 0;
1646         u8 oui_bytes[3] = {0, 0, 0};
1647         u16 enforce_sfp = 0;
1648         u8 connector = 0;
1649         u8 cable_length = 0;
1650         u8 device_tech = 0;
1651         bool active_cable = false;
1652
1653         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1654
1655         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1656                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1657                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1658                 goto out;
1659         }
1660
1661         /* LAN ID is needed for I2C access */
1662         hw->mac.ops.set_lan_id(hw);
1663
1664         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1665                                              &identifier);
1666
1667         if (status != IXGBE_SUCCESS)
1668                 goto err_read_i2c_eeprom;
1669
1670         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1671                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1672                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1673                 goto out;
1674         }
1675
1676         hw->phy.id = identifier;
1677
1678         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1679                                              &comp_codes_10g);
1680
1681         if (status != IXGBE_SUCCESS)
1682                 goto err_read_i2c_eeprom;
1683
1684         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1685                                              &comp_codes_1g);
1686
1687         if (status != IXGBE_SUCCESS)
1688                 goto err_read_i2c_eeprom;
1689
1690         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1691                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1692                 if (hw->bus.lan_id == 0)
1693                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1694                 else
1695                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1696         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1697                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1698                 if (hw->bus.lan_id == 0)
1699                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1700                 else
1701                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1702         } else {
1703                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1704                         active_cable = true;
1705
1706                 if (!active_cable) {
1707                         /* check for active DA cables that pre-date
1708                          * SFF-8436 v3.6 */
1709                         hw->phy.ops.read_i2c_eeprom(hw,
1710                                         IXGBE_SFF_QSFP_CONNECTOR,
1711                                         &connector);
1712
1713                         hw->phy.ops.read_i2c_eeprom(hw,
1714                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1715                                         &cable_length);
1716
1717                         hw->phy.ops.read_i2c_eeprom(hw,
1718                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1719                                         &device_tech);
1720
1721                         if ((connector ==
1722                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1723                             (cable_length > 0) &&
1724                             ((device_tech >> 4) ==
1725                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1726                                 active_cable = true;
1727                 }
1728
1729                 if (active_cable) {
1730                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1731                         if (hw->bus.lan_id == 0)
1732                                 hw->phy.sfp_type =
1733                                                 ixgbe_sfp_type_da_act_lmt_core0;
1734                         else
1735                                 hw->phy.sfp_type =
1736                                                 ixgbe_sfp_type_da_act_lmt_core1;
1737                 } else {
1738                         /* unsupported module type */
1739                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1740                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1741                         goto out;
1742                 }
1743         }
1744
1745         if (hw->phy.sfp_type != stored_sfp_type)
1746                 hw->phy.sfp_setup_needed = true;
1747
1748         /* Determine if the QSFP+ PHY is dual speed or not. */
1749         hw->phy.multispeed_fiber = false;
1750         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1751            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1752            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1753            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1754                 hw->phy.multispeed_fiber = true;
1755
1756         /* Determine PHY vendor for optical modules */
1757         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1758                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1759                 status = hw->phy.ops.read_i2c_eeprom(hw,
1760                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1761                                             &oui_bytes[0]);
1762
1763                 if (status != IXGBE_SUCCESS)
1764                         goto err_read_i2c_eeprom;
1765
1766                 status = hw->phy.ops.read_i2c_eeprom(hw,
1767                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1768                                             &oui_bytes[1]);
1769
1770                 if (status != IXGBE_SUCCESS)
1771                         goto err_read_i2c_eeprom;
1772
1773                 status = hw->phy.ops.read_i2c_eeprom(hw,
1774                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1775                                             &oui_bytes[2]);
1776
1777                 if (status != IXGBE_SUCCESS)
1778                         goto err_read_i2c_eeprom;
1779
1780                 vendor_oui =
1781                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1782                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1783                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1784
1785                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1786                         hw->phy.type = ixgbe_phy_qsfp_intel;
1787                 else
1788                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1789
1790                 ixgbe_get_device_caps(hw, &enforce_sfp);
1791                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1792                         /* Make sure we're a supported PHY type */
1793                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1794                                 status = IXGBE_SUCCESS;
1795                         } else {
1796                                 if (hw->allow_unsupported_sfp == true) {
1797                                         EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1798                                         status = IXGBE_SUCCESS;
1799                                 } else {
1800                                         DEBUGOUT("QSFP module not supported\n");
1801                                         hw->phy.type =
1802                                                 ixgbe_phy_sfp_unsupported;
1803                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1804                                 }
1805                         }
1806                 } else {
1807                         status = IXGBE_SUCCESS;
1808                 }
1809         }
1810
1811 out:
1812         return status;
1813
1814 err_read_i2c_eeprom:
1815         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1816         hw->phy.id = 0;
1817         hw->phy.type = ixgbe_phy_unknown;
1818
1819         return IXGBE_ERR_SFP_NOT_PRESENT;
1820 }
1821
1822 /**
1823  * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1824  * @hw: pointer to hardware structure
1825  * @list_offset: offset to the SFP ID list
1826  * @data_offset: offset to the SFP data block
1827  *
1828  * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1829  * so it returns the offsets to the phy init sequence block.
1830  **/
1831 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1832                                         u16 *list_offset,
1833                                         u16 *data_offset)
1834 {
1835         u16 sfp_id;
1836         u16 sfp_type = hw->phy.sfp_type;
1837
1838         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1839
1840         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1841                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1842
1843         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1844                 return IXGBE_ERR_SFP_NOT_PRESENT;
1845
1846         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1847             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1848                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1849
1850         /*
1851          * Limiting active cables and 1G Phys must be initialized as
1852          * SR modules
1853          */
1854         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1855             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1856             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1857             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1858                 sfp_type = ixgbe_sfp_type_srlr_core0;
1859         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1860                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1861                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1862                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1863                 sfp_type = ixgbe_sfp_type_srlr_core1;
1864
1865         /* Read offset to PHY init contents */
1866         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1867                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1868                               "eeprom read at offset %d failed",
1869                               IXGBE_PHY_INIT_OFFSET_NL);
1870                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1871         }
1872
1873         if ((!*list_offset) || (*list_offset == 0xFFFF))
1874                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1875
1876         /* Shift offset to first ID word */
1877         (*list_offset)++;
1878
1879         /*
1880          * Find the matching SFP ID in the EEPROM
1881          * and program the init sequence
1882          */
1883         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1884                 goto err_phy;
1885
1886         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1887                 if (sfp_id == sfp_type) {
1888                         (*list_offset)++;
1889                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1890                                 goto err_phy;
1891                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1892                                 DEBUGOUT("SFP+ module not supported\n");
1893                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1894                         } else {
1895                                 break;
1896                         }
1897                 } else {
1898                         (*list_offset) += 2;
1899                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1900                                 goto err_phy;
1901                 }
1902         }
1903
1904         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1905                 DEBUGOUT("No matching SFP+ module found\n");
1906                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1907         }
1908
1909         return IXGBE_SUCCESS;
1910
1911 err_phy:
1912         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1913                       "eeprom read at offset %d failed", *list_offset);
1914         return IXGBE_ERR_PHY;
1915 }
1916
1917 /**
1918  * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1919  * @hw: pointer to hardware structure
1920  * @byte_offset: EEPROM byte offset to read
1921  * @eeprom_data: value read
1922  *
1923  * Performs byte read operation to SFP module's EEPROM over I2C interface.
1924  **/
1925 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1926                                   u8 *eeprom_data)
1927 {
1928         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1929
1930         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1931                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1932                                          eeprom_data);
1933 }
1934
1935 /**
1936  * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1937  * @hw: pointer to hardware structure
1938  * @byte_offset: byte offset at address 0xA2
1939  * @sff8472_data: value read
1940  *
1941  * Performs byte read operation to SFP module's SFF-8472 data over I2C
1942  **/
1943 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1944                                           u8 *sff8472_data)
1945 {
1946         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1947                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1948                                          sff8472_data);
1949 }
1950
1951 /**
1952  * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1953  * @hw: pointer to hardware structure
1954  * @byte_offset: EEPROM byte offset to write
1955  * @eeprom_data: value to write
1956  *
1957  * Performs byte write operation to SFP module's EEPROM over I2C interface.
1958  **/
1959 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1960                                    u8 eeprom_data)
1961 {
1962         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1963
1964         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1965                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1966                                           eeprom_data);
1967 }
1968
1969 /**
1970  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1971  * @hw: pointer to hardware structure
1972  * @offset: eeprom offset to be read
1973  * @addr: I2C address to be read
1974  */
1975 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1976 {
1977         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1978             offset == IXGBE_SFF_IDENTIFIER &&
1979             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1980                 return true;
1981         return false;
1982 }
1983
1984 /**
1985  * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1986  * @hw: pointer to hardware structure
1987  * @byte_offset: byte offset to read
1988  * @dev_addr: address to read from
1989  * @data: value read
1990  * @lock: true if to take and release semaphore
1991  *
1992  * Performs byte read operation to SFP module's EEPROM over I2C interface at
1993  * a specified device address.
1994  **/
1995 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1996                                            u8 dev_addr, u8 *data, bool lock)
1997 {
1998         s32 status;
1999         u32 max_retry = 10;
2000         u32 retry = 0;
2001         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2002         bool nack = 1;
2003         *data = 0;
2004
2005         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2006
2007         if (hw->mac.type >= ixgbe_mac_X550)
2008                 max_retry = 3;
2009         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2010                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2011
2012         do {
2013                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2014                         return IXGBE_ERR_SWFW_SYNC;
2015
2016                 ixgbe_i2c_start(hw);
2017
2018                 /* Device Address and write indication */
2019                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2020                 if (status != IXGBE_SUCCESS)
2021                         goto fail;
2022
2023                 status = ixgbe_get_i2c_ack(hw);
2024                 if (status != IXGBE_SUCCESS)
2025                         goto fail;
2026
2027                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2028                 if (status != IXGBE_SUCCESS)
2029                         goto fail;
2030
2031                 status = ixgbe_get_i2c_ack(hw);
2032                 if (status != IXGBE_SUCCESS)
2033                         goto fail;
2034
2035                 ixgbe_i2c_start(hw);
2036
2037                 /* Device Address and read indication */
2038                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2039                 if (status != IXGBE_SUCCESS)
2040                         goto fail;
2041
2042                 status = ixgbe_get_i2c_ack(hw);
2043                 if (status != IXGBE_SUCCESS)
2044                         goto fail;
2045
2046                 status = ixgbe_clock_in_i2c_byte(hw, data);
2047                 if (status != IXGBE_SUCCESS)
2048                         goto fail;
2049
2050                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2051                 if (status != IXGBE_SUCCESS)
2052                         goto fail;
2053
2054                 ixgbe_i2c_stop(hw);
2055                 if (lock)
2056                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2057                 return IXGBE_SUCCESS;
2058
2059 fail:
2060                 ixgbe_i2c_bus_clear(hw);
2061                 if (lock) {
2062                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2063                         msec_delay(100);
2064                 }
2065                 if (retry < max_retry)
2066                         DEBUGOUT("I2C byte read error - Retrying.\n");
2067                 else
2068                         DEBUGOUT("I2C byte read error.\n");
2069                 retry++;
2070         } while (retry <= max_retry);
2071
2072         return status;
2073 }
2074
2075 /**
2076  * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2077  * @hw: pointer to hardware structure
2078  * @byte_offset: byte offset to read
2079  * @dev_addr: address to read from
2080  * @data: value read
2081  *
2082  * Performs byte read operation to SFP module's EEPROM over I2C interface at
2083  * a specified device address.
2084  **/
2085 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2086                                 u8 dev_addr, u8 *data)
2087 {
2088         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2089                                                data, true);
2090 }
2091
2092 /**
2093  * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2094  * @hw: pointer to hardware structure
2095  * @byte_offset: byte offset to read
2096  * @dev_addr: address to read from
2097  * @data: value read
2098  *
2099  * Performs byte read operation to SFP module's EEPROM over I2C interface at
2100  * a specified device address.
2101  **/
2102 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2103                                          u8 dev_addr, u8 *data)
2104 {
2105         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2106                                                data, false);
2107 }
2108
2109 /**
2110  * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2111  * @hw: pointer to hardware structure
2112  * @byte_offset: byte offset to write
2113  * @dev_addr: address to write to
2114  * @data: value to write
2115  * @lock: true if to take and release semaphore
2116  *
2117  * Performs byte write operation to SFP module's EEPROM over I2C interface at
2118  * a specified device address.
2119  **/
2120 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2121                                             u8 dev_addr, u8 data, bool lock)
2122 {
2123         s32 status;
2124         u32 max_retry = 1;
2125         u32 retry = 0;
2126         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2127
2128         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2129
2130         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2131             IXGBE_SUCCESS)
2132                 return IXGBE_ERR_SWFW_SYNC;
2133
2134         do {
2135                 ixgbe_i2c_start(hw);
2136
2137                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2138                 if (status != IXGBE_SUCCESS)
2139                         goto fail;
2140
2141                 status = ixgbe_get_i2c_ack(hw);
2142                 if (status != IXGBE_SUCCESS)
2143                         goto fail;
2144
2145                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2146                 if (status != IXGBE_SUCCESS)
2147                         goto fail;
2148
2149                 status = ixgbe_get_i2c_ack(hw);
2150                 if (status != IXGBE_SUCCESS)
2151                         goto fail;
2152
2153                 status = ixgbe_clock_out_i2c_byte(hw, data);
2154                 if (status != IXGBE_SUCCESS)
2155                         goto fail;
2156
2157                 status = ixgbe_get_i2c_ack(hw);
2158                 if (status != IXGBE_SUCCESS)
2159                         goto fail;
2160
2161                 ixgbe_i2c_stop(hw);
2162                 if (lock)
2163                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2164                 return IXGBE_SUCCESS;
2165
2166 fail:
2167                 ixgbe_i2c_bus_clear(hw);
2168                 if (retry < max_retry)
2169                         DEBUGOUT("I2C byte write error - Retrying.\n");
2170                 else
2171                         DEBUGOUT("I2C byte write error.\n");
2172                 retry++;
2173         } while (retry <= max_retry);
2174
2175         if (lock)
2176                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2177
2178         return status;
2179 }
2180
2181 /**
2182  * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2183  * @hw: pointer to hardware structure
2184  * @byte_offset: byte offset to write
2185  * @dev_addr: address to write to
2186  * @data: value to write
2187  *
2188  * Performs byte write operation to SFP module's EEPROM over I2C interface at
2189  * a specified device address.
2190  **/
2191 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2192                                  u8 dev_addr, u8 data)
2193 {
2194         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2195                                                 data, true);
2196 }
2197
2198 /**
2199  * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2200  * @hw: pointer to hardware structure
2201  * @byte_offset: byte offset to write
2202  * @dev_addr: address to write to
2203  * @data: value to write
2204  *
2205  * Performs byte write operation to SFP module's EEPROM over I2C interface at
2206  * a specified device address.
2207  **/
2208 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2209                                           u8 dev_addr, u8 data)
2210 {
2211         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2212                                                 data, false);
2213 }
2214
2215 /**
2216  * ixgbe_i2c_start - Sets I2C start condition
2217  * @hw: pointer to hardware structure
2218  *
2219  * Sets I2C start condition (High -> Low on SDA while SCL is High)
2220  * Set bit-bang mode on X550 hardware.
2221  **/
2222 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2223 {
2224         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2225
2226         DEBUGFUNC("ixgbe_i2c_start");
2227
2228         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2229
2230         /* Start condition must begin with data and clock high */
2231         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2232         ixgbe_raise_i2c_clk(hw, &i2cctl);
2233
2234         /* Setup time for start condition (4.7us) */
2235         usec_delay(IXGBE_I2C_T_SU_STA);
2236
2237         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2238
2239         /* Hold time for start condition (4us) */
2240         usec_delay(IXGBE_I2C_T_HD_STA);
2241
2242         ixgbe_lower_i2c_clk(hw, &i2cctl);
2243
2244         /* Minimum low period of clock is 4.7 us */
2245         usec_delay(IXGBE_I2C_T_LOW);
2246
2247 }
2248
2249 /**
2250  * ixgbe_i2c_stop - Sets I2C stop condition
2251  * @hw: pointer to hardware structure
2252  *
2253  * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2254  * Disables bit-bang mode and negates data output enable on X550
2255  * hardware.
2256  **/
2257 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2258 {
2259         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2260         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2261         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2262         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2263
2264         DEBUGFUNC("ixgbe_i2c_stop");
2265
2266         /* Stop condition must begin with data low and clock high */
2267         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2268         ixgbe_raise_i2c_clk(hw, &i2cctl);
2269
2270         /* Setup time for stop condition (4us) */
2271         usec_delay(IXGBE_I2C_T_SU_STO);
2272
2273         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2274
2275         /* bus free time between stop and start (4.7us)*/
2276         usec_delay(IXGBE_I2C_T_BUF);
2277
2278         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2279                 i2cctl &= ~bb_en_bit;
2280                 i2cctl |= data_oe_bit | clk_oe_bit;
2281                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2282                 IXGBE_WRITE_FLUSH(hw);
2283         }
2284 }
2285
2286 /**
2287  * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2288  * @hw: pointer to hardware structure
2289  * @data: data byte to clock in
2290  *
2291  * Clocks in one byte data via I2C data/clock
2292  **/
2293 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2294 {
2295         s32 i;
2296         bool bit = 0;
2297
2298         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2299
2300         *data = 0;
2301         for (i = 7; i >= 0; i--) {
2302                 ixgbe_clock_in_i2c_bit(hw, &bit);
2303                 *data |= bit << i;
2304         }
2305
2306         return IXGBE_SUCCESS;
2307 }
2308
2309 /**
2310  * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2311  * @hw: pointer to hardware structure
2312  * @data: data byte clocked out
2313  *
2314  * Clocks out one byte data via I2C data/clock
2315  **/
2316 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2317 {
2318         s32 status = IXGBE_SUCCESS;
2319         s32 i;
2320         u32 i2cctl;
2321         bool bit;
2322
2323         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2324
2325         for (i = 7; i >= 0; i--) {
2326                 bit = (data >> i) & 0x1;
2327                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2328
2329                 if (status != IXGBE_SUCCESS)
2330                         break;
2331         }
2332
2333         /* Release SDA line (set high) */
2334         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2335         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2336         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2337         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2338         IXGBE_WRITE_FLUSH(hw);
2339
2340         return status;
2341 }
2342
2343 /**
2344  * ixgbe_get_i2c_ack - Polls for I2C ACK
2345  * @hw: pointer to hardware structure
2346  *
2347  * Clocks in/out one bit via I2C data/clock
2348  **/
2349 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2350 {
2351         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2352         s32 status = IXGBE_SUCCESS;
2353         u32 i = 0;
2354         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2355         u32 timeout = 10;
2356         bool ack = 1;
2357
2358         DEBUGFUNC("ixgbe_get_i2c_ack");
2359
2360         if (data_oe_bit) {
2361                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2362                 i2cctl |= data_oe_bit;
2363                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2364                 IXGBE_WRITE_FLUSH(hw);
2365         }
2366         ixgbe_raise_i2c_clk(hw, &i2cctl);
2367
2368         /* Minimum high period of clock is 4us */
2369         usec_delay(IXGBE_I2C_T_HIGH);
2370
2371         /* Poll for ACK.  Note that ACK in I2C spec is
2372          * transition from 1 to 0 */
2373         for (i = 0; i < timeout; i++) {
2374                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2375                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2376
2377                 usec_delay(1);
2378                 if (!ack)
2379                         break;
2380         }
2381
2382         if (ack) {
2383                 DEBUGOUT("I2C ack was not received.\n");
2384                 status = IXGBE_ERR_I2C;
2385         }
2386
2387         ixgbe_lower_i2c_clk(hw, &i2cctl);
2388
2389         /* Minimum low period of clock is 4.7 us */
2390         usec_delay(IXGBE_I2C_T_LOW);
2391
2392         return status;
2393 }
2394
2395 /**
2396  * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2397  * @hw: pointer to hardware structure
2398  * @data: read data value
2399  *
2400  * Clocks in one bit via I2C data/clock
2401  **/
2402 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2403 {
2404         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2405         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2406
2407         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2408
2409         if (data_oe_bit) {
2410                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2411                 i2cctl |= data_oe_bit;
2412                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2413                 IXGBE_WRITE_FLUSH(hw);
2414         }
2415         ixgbe_raise_i2c_clk(hw, &i2cctl);
2416
2417         /* Minimum high period of clock is 4us */
2418         usec_delay(IXGBE_I2C_T_HIGH);
2419
2420         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2421         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2422
2423         ixgbe_lower_i2c_clk(hw, &i2cctl);
2424
2425         /* Minimum low period of clock is 4.7 us */
2426         usec_delay(IXGBE_I2C_T_LOW);
2427
2428         return IXGBE_SUCCESS;
2429 }
2430
2431 /**
2432  * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2433  * @hw: pointer to hardware structure
2434  * @data: data value to write
2435  *
2436  * Clocks out one bit via I2C data/clock
2437  **/
2438 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2439 {
2440         s32 status;
2441         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2442
2443         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2444
2445         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2446         if (status == IXGBE_SUCCESS) {
2447                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2448
2449                 /* Minimum high period of clock is 4us */
2450                 usec_delay(IXGBE_I2C_T_HIGH);
2451
2452                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2453
2454                 /* Minimum low period of clock is 4.7 us.
2455                  * This also takes care of the data hold time.
2456                  */
2457                 usec_delay(IXGBE_I2C_T_LOW);
2458         } else {
2459                 status = IXGBE_ERR_I2C;
2460                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2461                              "I2C data was not set to %X\n", data);
2462         }
2463
2464         return status;
2465 }
2466
2467 /**
2468  * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2469  * @hw: pointer to hardware structure
2470  * @i2cctl: Current value of I2CCTL register
2471  *
2472  * Raises the I2C clock line '0'->'1'
2473  * Negates the I2C clock output enable on X550 hardware.
2474  **/
2475 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2476 {
2477         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2478         u32 i = 0;
2479         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2480         u32 i2cctl_r = 0;
2481
2482         DEBUGFUNC("ixgbe_raise_i2c_clk");
2483
2484         if (clk_oe_bit) {
2485                 *i2cctl |= clk_oe_bit;
2486                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2487         }
2488
2489         for (i = 0; i < timeout; i++) {
2490                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2491
2492                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2493                 IXGBE_WRITE_FLUSH(hw);
2494                 /* SCL rise time (1000ns) */
2495                 usec_delay(IXGBE_I2C_T_RISE);
2496
2497                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2498                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2499                         break;
2500         }
2501 }
2502
2503 /**
2504  * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2505  * @hw: pointer to hardware structure
2506  * @i2cctl: Current value of I2CCTL register
2507  *
2508  * Lowers the I2C clock line '1'->'0'
2509  * Asserts the I2C clock output enable on X550 hardware.
2510  **/
2511 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2512 {
2513         DEBUGFUNC("ixgbe_lower_i2c_clk");
2514
2515         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2516         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2517
2518         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2519         IXGBE_WRITE_FLUSH(hw);
2520
2521         /* SCL fall time (300ns) */
2522         usec_delay(IXGBE_I2C_T_FALL);
2523 }
2524
2525 /**
2526  * ixgbe_set_i2c_data - Sets the I2C data bit
2527  * @hw: pointer to hardware structure
2528  * @i2cctl: Current value of I2CCTL register
2529  * @data: I2C data value (0 or 1) to set
2530  *
2531  * Sets the I2C data bit
2532  * Asserts the I2C data output enable on X550 hardware.
2533  **/
2534 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2535 {
2536         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2537         s32 status = IXGBE_SUCCESS;
2538
2539         DEBUGFUNC("ixgbe_set_i2c_data");
2540
2541         if (data)
2542                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2543         else
2544                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2545         *i2cctl &= ~data_oe_bit;
2546
2547         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2548         IXGBE_WRITE_FLUSH(hw);
2549
2550         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2551         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2552
2553         if (!data)      /* Can't verify data in this case */
2554                 return IXGBE_SUCCESS;
2555         if (data_oe_bit) {
2556                 *i2cctl |= data_oe_bit;
2557                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2558                 IXGBE_WRITE_FLUSH(hw);
2559         }
2560
2561         /* Verify data was set correctly */
2562         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2563         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2564                 status = IXGBE_ERR_I2C;
2565                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2566                              "Error - I2C data was not set to %X.\n",
2567                              data);
2568         }
2569
2570         return status;
2571 }
2572
2573 /**
2574  * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2575  * @hw: pointer to hardware structure
2576  * @i2cctl: Current value of I2CCTL register
2577  *
2578  * Returns the I2C data bit value
2579  * Negates the I2C data output enable on X550 hardware.
2580  **/
2581 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2582 {
2583         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2584         bool data;
2585         UNREFERENCED_1PARAMETER(hw);
2586
2587         DEBUGFUNC("ixgbe_get_i2c_data");
2588
2589         if (data_oe_bit) {
2590                 *i2cctl |= data_oe_bit;
2591                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2592                 IXGBE_WRITE_FLUSH(hw);
2593                 usec_delay(IXGBE_I2C_T_FALL);
2594         }
2595
2596         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2597                 data = 1;
2598         else
2599                 data = 0;
2600
2601         return data;
2602 }
2603
2604 /**
2605  * ixgbe_i2c_bus_clear - Clears the I2C bus
2606  * @hw: pointer to hardware structure
2607  *
2608  * Clears the I2C bus by sending nine clock pulses.
2609  * Used when data line is stuck low.
2610  **/
2611 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2612 {
2613         u32 i2cctl;
2614         u32 i;
2615
2616         DEBUGFUNC("ixgbe_i2c_bus_clear");
2617
2618         ixgbe_i2c_start(hw);
2619         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2620
2621         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2622
2623         for (i = 0; i < 9; i++) {
2624                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2625
2626                 /* Min high period of clock is 4us */
2627                 usec_delay(IXGBE_I2C_T_HIGH);
2628
2629                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2630
2631                 /* Min low period of clock is 4.7us*/
2632                 usec_delay(IXGBE_I2C_T_LOW);
2633         }
2634
2635         ixgbe_i2c_start(hw);
2636
2637         /* Put the i2c bus back to default state */
2638         ixgbe_i2c_stop(hw);
2639 }
2640
2641 /**
2642  * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2643  * @hw: pointer to hardware structure
2644  *
2645  * Checks if the LASI temp alarm status was triggered due to overtemp
2646  **/
2647 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2648 {
2649         s32 status = IXGBE_SUCCESS;
2650         u16 phy_data = 0;
2651
2652         DEBUGFUNC("ixgbe_tn_check_overtemp");
2653
2654         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2655                 goto out;
2656
2657         /* Check that the LASI temp alarm status was triggered */
2658         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2659                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2660
2661         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2662                 goto out;
2663
2664         status = IXGBE_ERR_OVERTEMP;
2665         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2666 out:
2667         return status;
2668 }
2669
2670 /**
2671  * ixgbe_set_copper_phy_power - Control power for copper phy
2672  * @hw: pointer to hardware structure
2673  * @on: true for on, false for off
2674  */
2675 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2676 {
2677         u32 status;
2678         u16 reg;
2679
2680         if (!on && ixgbe_mng_present(hw))
2681                 return 0;
2682
2683         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2684                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2685                                       &reg);
2686         if (status)
2687                 return status;
2688
2689         if (on) {
2690                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2691         } else {
2692                 if (ixgbe_check_reset_blocked(hw))
2693                         return 0;
2694                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2695         }
2696
2697         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2698                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2699                                        reg);
2700         return status;
2701 }