1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2017, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
33 ******************************************************************************/
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
42 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
45 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
50 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
51 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
55 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
56 * @hw: pointer to the hardware structure
59 * Returns an error code on error.
61 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
65 status = ixgbe_clock_out_i2c_byte(hw, byte);
68 return ixgbe_get_i2c_ack(hw);
72 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
73 * @hw: pointer to the hardware structure
74 * @byte: pointer to a u8 to receive the byte
76 * Returns an error code on error.
78 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
82 status = ixgbe_clock_in_i2c_byte(hw, byte);
86 return ixgbe_clock_out_i2c_bit(hw, FALSE);
90 * ixgbe_ones_comp_byte_add - Perform one's complement addition
94 * Returns one's complement 8-bit sum.
96 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
98 u16 sum = add1 + add2;
100 sum = (sum & 0xFF) + (sum >> 8);
105 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
106 * @hw: pointer to the hardware structure
107 * @addr: I2C bus address to read from
108 * @reg: I2C device register to read from
109 * @val: pointer to location to receive read value
110 * @lock: TRUE if to take and release semaphore
112 * Returns an error code on error.
114 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
117 u32 swfw_mask = hw->phy.phy_semaphore_mask;
126 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
127 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
130 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
131 return IXGBE_ERR_SWFW_SYNC;
133 /* Device Address and write indication */
134 if (ixgbe_out_i2c_byte_ack(hw, addr))
136 /* Write bits 14:8 */
137 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
140 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
143 if (ixgbe_out_i2c_byte_ack(hw, csum))
145 /* Re-start condition */
147 /* Device Address and read indication */
148 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
151 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
154 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
157 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
160 if (ixgbe_clock_out_i2c_bit(hw, FALSE))
164 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
165 *val = (high_bits << 8) | low_bits;
169 ixgbe_i2c_bus_clear(hw);
171 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
173 if (retry < max_retry)
174 DEBUGOUT("I2C byte read combined error - Retrying.\n");
176 DEBUGOUT("I2C byte read combined error.\n");
177 } while (retry < max_retry);
179 return IXGBE_ERR_I2C;
183 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
184 * @hw: pointer to the hardware structure
185 * @addr: I2C bus address to write to
186 * @reg: I2C device register to write to
187 * @val: value to write
188 * @lock: TRUE if to take and release semaphore
190 * Returns an error code on error.
192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
195 u32 swfw_mask = hw->phy.phy_semaphore_mask;
201 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
202 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
203 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
204 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
207 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
208 return IXGBE_ERR_SWFW_SYNC;
210 /* Device Address and write indication */
211 if (ixgbe_out_i2c_byte_ack(hw, addr))
213 /* Write bits 14:8 */
214 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
217 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
219 /* Write data 15:8 */
220 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
223 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
226 if (ixgbe_out_i2c_byte_ack(hw, csum))
230 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
234 ixgbe_i2c_bus_clear(hw);
236 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
238 if (retry < max_retry)
239 DEBUGOUT("I2C byte write combined error - Retrying.\n");
241 DEBUGOUT("I2C byte write combined error.\n");
242 } while (retry < max_retry);
244 return IXGBE_ERR_I2C;
248 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
249 * @hw: pointer to the hardware structure
251 * Initialize the function pointers.
253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
255 struct ixgbe_phy_info *phy = &hw->phy;
257 DEBUGFUNC("ixgbe_init_phy_ops_generic");
260 phy->ops.identify = ixgbe_identify_phy_generic;
261 phy->ops.reset = ixgbe_reset_phy_generic;
262 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
263 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
264 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
265 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
266 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
267 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
268 phy->ops.check_link = NULL;
269 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
270 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
271 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
272 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
273 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
274 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
275 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
276 phy->ops.identify_sfp = ixgbe_identify_module_generic;
277 phy->sfp_type = ixgbe_sfp_type_unknown;
278 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
279 phy->ops.write_i2c_byte_unlocked =
280 ixgbe_write_i2c_byte_generic_unlocked;
281 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
282 return IXGBE_SUCCESS;
286 * ixgbe_probe_phy - Probe a single address for a PHY
287 * @hw: pointer to hardware structure
288 * @phy_addr: PHY address to probe
290 * Returns TRUE if PHY found
292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
296 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
297 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
302 if (ixgbe_get_phy_id(hw))
305 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
307 if (hw->phy.type == ixgbe_phy_unknown) {
308 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
309 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
311 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
312 IXGBE_MDIO_PHY_1000BASET_ABILITY))
313 hw->phy.type = ixgbe_phy_cu_unknown;
315 hw->phy.type = ixgbe_phy_generic;
322 * ixgbe_identify_phy_generic - Get physical layer module
323 * @hw: pointer to hardware structure
325 * Determines the physical layer module found on the current adapter.
327 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
329 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
332 DEBUGFUNC("ixgbe_identify_phy_generic");
334 if (!hw->phy.phy_semaphore_mask) {
336 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
338 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
341 if (hw->phy.type != ixgbe_phy_unknown)
342 return IXGBE_SUCCESS;
344 if (hw->phy.nw_mng_if_sel) {
345 phy_addr = (hw->phy.nw_mng_if_sel &
346 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
347 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
348 if (ixgbe_probe_phy(hw, phy_addr))
349 return IXGBE_SUCCESS;
351 return IXGBE_ERR_PHY_ADDR_INVALID;
354 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
355 if (ixgbe_probe_phy(hw, phy_addr)) {
356 status = IXGBE_SUCCESS;
361 /* Certain media types do not have a phy so an address will not
362 * be found and the code will take this path. Caller has to
363 * decide if it is an error or not.
365 if (status != IXGBE_SUCCESS)
372 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
373 * @hw: pointer to the hardware structure
375 * This function checks the MMNGC.MNG_VETO bit to see if there are
376 * any constraints on link from manageability. For MAC's that don't
377 * have this bit just return faluse since the link can not be blocked
380 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
384 DEBUGFUNC("ixgbe_check_reset_blocked");
386 /* If we don't have this bit, it can't be blocking */
387 if (hw->mac.type == ixgbe_mac_82598EB)
390 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
391 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
392 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
393 "MNG_VETO bit detected.\n");
401 * ixgbe_validate_phy_addr - Determines phy address is valid
402 * @hw: pointer to hardware structure
405 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
410 DEBUGFUNC("ixgbe_validate_phy_addr");
412 hw->phy.addr = phy_addr;
413 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
414 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
416 if (phy_id != 0xFFFF && phy_id != 0x0)
419 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
425 * ixgbe_get_phy_id - Get the phy type
426 * @hw: pointer to hardware structure
429 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
435 DEBUGFUNC("ixgbe_get_phy_id");
437 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
438 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
441 if (status == IXGBE_SUCCESS) {
442 hw->phy.id = (u32)(phy_id_high << 16);
443 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
444 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
446 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
447 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
449 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
450 phy_id_high, phy_id_low);
456 * ixgbe_get_phy_type_from_id - Get the phy type
457 * @phy_id: PHY ID information
460 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
462 enum ixgbe_phy_type phy_type;
464 DEBUGFUNC("ixgbe_get_phy_type_from_id");
468 phy_type = ixgbe_phy_tn;
473 phy_type = ixgbe_phy_aq;
476 phy_type = ixgbe_phy_qt;
479 phy_type = ixgbe_phy_nl;
483 phy_type = ixgbe_phy_x550em_ext_t;
485 case IXGBE_M88E1500_E_PHY_ID:
486 case IXGBE_M88E1543_E_PHY_ID:
487 phy_type = ixgbe_phy_ext_1g_t;
490 phy_type = ixgbe_phy_unknown;
497 * ixgbe_reset_phy_generic - Performs a PHY reset
498 * @hw: pointer to hardware structure
500 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
504 s32 status = IXGBE_SUCCESS;
506 DEBUGFUNC("ixgbe_reset_phy_generic");
508 if (hw->phy.type == ixgbe_phy_unknown)
509 status = ixgbe_identify_phy_generic(hw);
511 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
514 /* Don't reset PHY if it's shut down due to overtemp. */
515 if (!hw->phy.reset_if_overtemp &&
516 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
519 /* Blocked by MNG FW so bail */
520 if (ixgbe_check_reset_blocked(hw))
524 * Perform soft PHY reset to the PHY_XS.
525 * This will cause a soft reset to the PHY
527 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
528 IXGBE_MDIO_PHY_XS_DEV_TYPE,
529 IXGBE_MDIO_PHY_XS_RESET);
532 * Poll for reset bit to self-clear indicating reset is complete.
533 * Some PHYs could take up to 3 seconds to complete and need about
534 * 1.7 usec delay after the reset is complete.
536 for (i = 0; i < 30; i++) {
538 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
539 status = hw->phy.ops.read_reg(hw,
540 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
541 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
543 if (status != IXGBE_SUCCESS)
546 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
551 status = hw->phy.ops.read_reg(hw,
552 IXGBE_MDIO_PHY_XS_CONTROL,
553 IXGBE_MDIO_PHY_XS_DEV_TYPE,
555 if (status != IXGBE_SUCCESS)
558 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
565 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
566 status = IXGBE_ERR_RESET_FAILED;
567 ERROR_REPORT1(IXGBE_ERROR_POLLING,
568 "PHY reset polling failed to complete.\n");
576 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
578 * @hw: pointer to hardware structure
579 * @reg_addr: 32 bit address of PHY register to read
580 * @phy_data: Pointer to read data from PHY register
582 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
585 u32 i, data, command;
587 /* Setup and write the address cycle command */
588 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
589 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
590 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
591 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
593 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
596 * Check every 10 usec to see if the address cycle completed.
597 * The MDI Command bit will clear when the operation is
600 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
603 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
604 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
609 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
610 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
611 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
612 return IXGBE_ERR_PHY;
616 * Address cycle complete, setup and write the read
619 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
620 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
621 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
622 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
624 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
627 * Check every 10 usec to see if the address cycle
628 * completed. The MDI Command bit will clear when the
629 * operation is complete
631 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
634 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
635 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
639 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
640 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
641 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
642 return IXGBE_ERR_PHY;
646 * Read operation is complete. Get the data
649 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
650 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
651 *phy_data = (u16)(data);
653 return IXGBE_SUCCESS;
657 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
658 * using the SWFW lock - this function is needed in most cases
659 * @hw: pointer to hardware structure
660 * @reg_addr: 32 bit address of PHY register to read
661 * @phy_data: Pointer to read data from PHY register
663 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
664 u32 device_type, u16 *phy_data)
667 u32 gssr = hw->phy.phy_semaphore_mask;
669 DEBUGFUNC("ixgbe_read_phy_reg_generic");
671 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
672 return IXGBE_ERR_SWFW_SYNC;
674 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
676 hw->mac.ops.release_swfw_sync(hw, gssr);
682 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
684 * @hw: pointer to hardware structure
685 * @reg_addr: 32 bit PHY register to write
686 * @device_type: 5 bit device type
687 * @phy_data: Data to write to the PHY register
689 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
690 u32 device_type, u16 phy_data)
694 /* Put the data in the MDI single read and write data register*/
695 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
697 /* Setup and write the address cycle command */
698 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
699 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
700 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
701 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
703 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
706 * Check every 10 usec to see if the address cycle completed.
707 * The MDI Command bit will clear when the operation is
710 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
713 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
714 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
718 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
719 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
720 return IXGBE_ERR_PHY;
724 * Address cycle complete, setup and write the write
727 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
728 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
729 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
730 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
732 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
735 * Check every 10 usec to see if the address cycle
736 * completed. The MDI Command bit will clear when the
737 * operation is complete
739 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
742 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
743 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
747 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
748 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
749 return IXGBE_ERR_PHY;
752 return IXGBE_SUCCESS;
756 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
757 * using SWFW lock- this function is needed in most cases
758 * @hw: pointer to hardware structure
759 * @reg_addr: 32 bit PHY register to write
760 * @device_type: 5 bit device type
761 * @phy_data: Data to write to the PHY register
763 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
764 u32 device_type, u16 phy_data)
767 u32 gssr = hw->phy.phy_semaphore_mask;
769 DEBUGFUNC("ixgbe_write_phy_reg_generic");
771 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
772 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
774 hw->mac.ops.release_swfw_sync(hw, gssr);
776 status = IXGBE_ERR_SWFW_SYNC;
783 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
784 * @hw: pointer to hardware structure
786 * Restart auto-negotiation and PHY and waits for completion.
788 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
790 s32 status = IXGBE_SUCCESS;
791 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
792 bool autoneg = FALSE;
793 ixgbe_link_speed speed;
795 DEBUGFUNC("ixgbe_setup_phy_link_generic");
797 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
799 /* Set or unset auto-negotiation 10G advertisement */
800 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
801 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
804 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
805 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
806 (speed & IXGBE_LINK_SPEED_10GB_FULL))
807 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
809 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
810 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
813 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
814 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
817 if (hw->mac.type == ixgbe_mac_X550) {
818 /* Set or unset auto-negotiation 5G advertisement */
819 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
820 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
821 (speed & IXGBE_LINK_SPEED_5GB_FULL))
822 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
824 /* Set or unset auto-negotiation 2.5G advertisement */
825 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
826 if ((hw->phy.autoneg_advertised &
827 IXGBE_LINK_SPEED_2_5GB_FULL) &&
828 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
829 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
832 /* Set or unset auto-negotiation 1G advertisement */
833 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
834 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
835 (speed & IXGBE_LINK_SPEED_1GB_FULL))
836 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
838 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
839 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
842 /* Set or unset auto-negotiation 100M advertisement */
843 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
844 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
847 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
848 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
849 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
850 (speed & IXGBE_LINK_SPEED_100_FULL))
851 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
853 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
854 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
857 /* Blocked by MNG FW so don't reset PHY */
858 if (ixgbe_check_reset_blocked(hw))
861 /* Restart PHY auto-negotiation. */
862 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
863 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
865 autoneg_reg |= IXGBE_MII_RESTART;
867 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
868 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
874 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
875 * @hw: pointer to hardware structure
876 * @speed: new link speed
878 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
879 ixgbe_link_speed speed,
880 bool autoneg_wait_to_complete)
882 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
884 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
887 * Clear autoneg_advertised and set new values based on input link
890 hw->phy.autoneg_advertised = 0;
892 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
893 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
895 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
896 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
898 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
899 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
901 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
902 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
904 if (speed & IXGBE_LINK_SPEED_100_FULL)
905 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
907 if (speed & IXGBE_LINK_SPEED_10_FULL)
908 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
910 /* Setup link based on the new speed settings */
911 ixgbe_setup_phy_link(hw);
913 return IXGBE_SUCCESS;
917 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
918 * @hw: pointer to hardware structure
920 * Determines the supported link capabilities by reading the PHY auto
921 * negotiation register.
923 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
928 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
929 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
934 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
935 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
936 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
937 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
938 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
939 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
941 switch (hw->mac.type) {
943 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
946 case ixgbe_mac_X550EM_x:
947 case ixgbe_mac_X550EM_a:
948 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
958 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
959 * @hw: pointer to hardware structure
960 * @speed: pointer to link speed
961 * @autoneg: boolean auto-negotiation value
963 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
964 ixgbe_link_speed *speed,
967 s32 status = IXGBE_SUCCESS;
969 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
972 if (!hw->phy.speeds_supported)
973 status = ixgbe_get_copper_speeds_supported(hw);
975 *speed = hw->phy.speeds_supported;
980 * ixgbe_check_phy_link_tnx - Determine link and speed status
981 * @hw: pointer to hardware structure
983 * Reads the VS1 register to determine if link is up and the current speed for
986 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
989 s32 status = IXGBE_SUCCESS;
991 u32 max_time_out = 10;
996 DEBUGFUNC("ixgbe_check_phy_link_tnx");
998 /* Initialize speed and link to default case */
1000 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1003 * Check current speed and link status of the PHY register.
1004 * This is a vendor specific register and may have to
1005 * be changed for other copper PHYs.
1007 for (time_out = 0; time_out < max_time_out; time_out++) {
1009 status = hw->phy.ops.read_reg(hw,
1010 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1011 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1013 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1014 phy_speed = phy_data &
1015 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1016 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1019 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1020 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1029 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1030 * @hw: pointer to hardware structure
1032 * Restart auto-negotiation and PHY and waits for completion.
1034 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1036 s32 status = IXGBE_SUCCESS;
1037 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1038 bool autoneg = FALSE;
1039 ixgbe_link_speed speed;
1041 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1043 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1045 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1046 /* Set or unset auto-negotiation 10G advertisement */
1047 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1048 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1051 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1052 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1053 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1055 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1056 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1060 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1061 /* Set or unset auto-negotiation 1G advertisement */
1062 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1063 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1066 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1067 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1068 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1070 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1071 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1075 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1076 /* Set or unset auto-negotiation 100M advertisement */
1077 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1078 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1081 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1082 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1083 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1085 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1086 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1090 /* Blocked by MNG FW so don't reset PHY */
1091 if (ixgbe_check_reset_blocked(hw))
1094 /* Restart PHY auto-negotiation. */
1095 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1096 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1098 autoneg_reg |= IXGBE_MII_RESTART;
1100 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1101 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1107 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1108 * @hw: pointer to hardware structure
1109 * @firmware_version: pointer to the PHY Firmware Version
1111 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1112 u16 *firmware_version)
1116 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1118 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1119 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1126 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1127 * @hw: pointer to hardware structure
1128 * @firmware_version: pointer to the PHY Firmware Version
1130 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1131 u16 *firmware_version)
1135 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1137 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1138 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1145 * ixgbe_reset_phy_nl - Performs a PHY reset
1146 * @hw: pointer to hardware structure
1148 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1150 u16 phy_offset, control, eword, edata, block_crc;
1151 bool end_data = FALSE;
1152 u16 list_offset, data_offset;
1154 s32 ret_val = IXGBE_SUCCESS;
1157 DEBUGFUNC("ixgbe_reset_phy_nl");
1159 /* Blocked by MNG FW so bail */
1160 if (ixgbe_check_reset_blocked(hw))
1163 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1164 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1166 /* reset the PHY and poll for completion */
1167 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1168 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1169 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1171 for (i = 0; i < 100; i++) {
1172 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1173 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1174 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1179 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1180 DEBUGOUT("PHY reset did not complete.\n");
1181 ret_val = IXGBE_ERR_PHY;
1185 /* Get init offsets */
1186 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1188 if (ret_val != IXGBE_SUCCESS)
1191 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1195 * Read control word from PHY init contents offset
1197 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1200 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1201 IXGBE_CONTROL_SHIFT_NL;
1202 edata = eword & IXGBE_DATA_MASK_NL;
1204 case IXGBE_DELAY_NL:
1206 DEBUGOUT1("DELAY: %d MS\n", edata);
1210 DEBUGOUT("DATA:\n");
1212 ret_val = hw->eeprom.ops.read(hw, data_offset,
1217 for (i = 0; i < edata; i++) {
1218 ret_val = hw->eeprom.ops.read(hw, data_offset,
1222 hw->phy.ops.write_reg(hw, phy_offset,
1223 IXGBE_TWINAX_DEV, eword);
1224 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1230 case IXGBE_CONTROL_NL:
1232 DEBUGOUT("CONTROL:\n");
1233 if (edata == IXGBE_CONTROL_EOL_NL) {
1236 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1239 DEBUGOUT("Bad control value\n");
1240 ret_val = IXGBE_ERR_PHY;
1245 DEBUGOUT("Bad control type\n");
1246 ret_val = IXGBE_ERR_PHY;
1255 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1256 "eeprom read at offset %d failed", data_offset);
1257 return IXGBE_ERR_PHY;
1261 * ixgbe_identify_module_generic - Identifies module type
1262 * @hw: pointer to hardware structure
1264 * Determines HW type and calls appropriate function.
1266 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1268 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1270 DEBUGFUNC("ixgbe_identify_module_generic");
1272 switch (hw->mac.ops.get_media_type(hw)) {
1273 case ixgbe_media_type_fiber:
1274 status = ixgbe_identify_sfp_module_generic(hw);
1277 case ixgbe_media_type_fiber_qsfp:
1278 status = ixgbe_identify_qsfp_module_generic(hw);
1282 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1283 status = IXGBE_ERR_SFP_NOT_PRESENT;
1291 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1292 * @hw: pointer to hardware structure
1294 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1296 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1298 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1300 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1302 u8 comp_codes_1g = 0;
1303 u8 comp_codes_10g = 0;
1304 u8 oui_bytes[3] = {0, 0, 0};
1307 u16 enforce_sfp = 0;
1309 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1311 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1312 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1313 status = IXGBE_ERR_SFP_NOT_PRESENT;
1317 /* LAN ID is needed for I2C access */
1318 hw->mac.ops.set_lan_id(hw);
1320 status = hw->phy.ops.read_i2c_eeprom(hw,
1321 IXGBE_SFF_IDENTIFIER,
1324 if (status != IXGBE_SUCCESS)
1325 goto err_read_i2c_eeprom;
1327 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1328 hw->phy.type = ixgbe_phy_sfp_unsupported;
1329 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1331 status = hw->phy.ops.read_i2c_eeprom(hw,
1332 IXGBE_SFF_1GBE_COMP_CODES,
1335 if (status != IXGBE_SUCCESS)
1336 goto err_read_i2c_eeprom;
1338 status = hw->phy.ops.read_i2c_eeprom(hw,
1339 IXGBE_SFF_10GBE_COMP_CODES,
1342 if (status != IXGBE_SUCCESS)
1343 goto err_read_i2c_eeprom;
1344 status = hw->phy.ops.read_i2c_eeprom(hw,
1345 IXGBE_SFF_CABLE_TECHNOLOGY,
1348 if (status != IXGBE_SUCCESS)
1349 goto err_read_i2c_eeprom;
1356 * 3 SFP_DA_CORE0 - 82599-specific
1357 * 4 SFP_DA_CORE1 - 82599-specific
1358 * 5 SFP_SR/LR_CORE0 - 82599-specific
1359 * 6 SFP_SR/LR_CORE1 - 82599-specific
1360 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1361 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1362 * 9 SFP_1g_cu_CORE0 - 82599-specific
1363 * 10 SFP_1g_cu_CORE1 - 82599-specific
1364 * 11 SFP_1g_sx_CORE0 - 82599-specific
1365 * 12 SFP_1g_sx_CORE1 - 82599-specific
1367 if (hw->mac.type == ixgbe_mac_82598EB) {
1368 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1369 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1370 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1371 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1372 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1373 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1375 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1377 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1378 if (hw->bus.lan_id == 0)
1380 ixgbe_sfp_type_da_cu_core0;
1383 ixgbe_sfp_type_da_cu_core1;
1384 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1385 hw->phy.ops.read_i2c_eeprom(
1386 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1389 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1390 if (hw->bus.lan_id == 0)
1392 ixgbe_sfp_type_da_act_lmt_core0;
1395 ixgbe_sfp_type_da_act_lmt_core1;
1398 ixgbe_sfp_type_unknown;
1400 } else if (comp_codes_10g &
1401 (IXGBE_SFF_10GBASESR_CAPABLE |
1402 IXGBE_SFF_10GBASELR_CAPABLE)) {
1403 if (hw->bus.lan_id == 0)
1405 ixgbe_sfp_type_srlr_core0;
1408 ixgbe_sfp_type_srlr_core1;
1409 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1410 if (hw->bus.lan_id == 0)
1412 ixgbe_sfp_type_1g_cu_core0;
1415 ixgbe_sfp_type_1g_cu_core1;
1416 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1417 if (hw->bus.lan_id == 0)
1419 ixgbe_sfp_type_1g_sx_core0;
1422 ixgbe_sfp_type_1g_sx_core1;
1423 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1424 if (hw->bus.lan_id == 0)
1426 ixgbe_sfp_type_1g_lx_core0;
1429 ixgbe_sfp_type_1g_lx_core1;
1431 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1435 if (hw->phy.sfp_type != stored_sfp_type)
1436 hw->phy.sfp_setup_needed = TRUE;
1438 /* Determine if the SFP+ PHY is dual speed or not. */
1439 hw->phy.multispeed_fiber = FALSE;
1440 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1441 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1442 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1443 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1444 hw->phy.multispeed_fiber = TRUE;
1446 /* Determine PHY vendor */
1447 if (hw->phy.type != ixgbe_phy_nl) {
1448 hw->phy.id = identifier;
1449 status = hw->phy.ops.read_i2c_eeprom(hw,
1450 IXGBE_SFF_VENDOR_OUI_BYTE0,
1453 if (status != IXGBE_SUCCESS)
1454 goto err_read_i2c_eeprom;
1456 status = hw->phy.ops.read_i2c_eeprom(hw,
1457 IXGBE_SFF_VENDOR_OUI_BYTE1,
1460 if (status != IXGBE_SUCCESS)
1461 goto err_read_i2c_eeprom;
1463 status = hw->phy.ops.read_i2c_eeprom(hw,
1464 IXGBE_SFF_VENDOR_OUI_BYTE2,
1467 if (status != IXGBE_SUCCESS)
1468 goto err_read_i2c_eeprom;
1471 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1472 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1473 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1475 switch (vendor_oui) {
1476 case IXGBE_SFF_VENDOR_OUI_TYCO:
1477 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1479 ixgbe_phy_sfp_passive_tyco;
1481 case IXGBE_SFF_VENDOR_OUI_FTL:
1482 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1483 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1485 hw->phy.type = ixgbe_phy_sfp_ftl;
1487 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1488 hw->phy.type = ixgbe_phy_sfp_avago;
1490 case IXGBE_SFF_VENDOR_OUI_INTEL:
1491 hw->phy.type = ixgbe_phy_sfp_intel;
1494 hw->phy.type = ixgbe_phy_sfp_unknown;
1499 /* Allow any DA cable vendor */
1500 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1501 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1502 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1503 hw->phy.type = ixgbe_phy_sfp_passive_unknown;
1504 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1505 hw->phy.type = ixgbe_phy_sfp_active_unknown;
1506 status = IXGBE_SUCCESS;
1510 /* Verify supported 1G SFP modules */
1511 if (comp_codes_10g == 0 &&
1512 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1513 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1514 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1515 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1516 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1517 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1518 hw->phy.type = ixgbe_phy_sfp_unsupported;
1519 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1523 /* Anything else 82598-based is supported */
1524 if (hw->mac.type == ixgbe_mac_82598EB) {
1525 status = IXGBE_SUCCESS;
1529 ixgbe_get_device_caps(hw, &enforce_sfp);
1530 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1531 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1532 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1533 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1534 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1535 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1536 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1537 /* Make sure we're a supported PHY type */
1538 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1539 status = IXGBE_SUCCESS;
1541 if (hw->allow_unsupported_sfp == TRUE) {
1542 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1543 status = IXGBE_SUCCESS;
1545 DEBUGOUT("SFP+ module not supported\n");
1547 ixgbe_phy_sfp_unsupported;
1548 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1552 status = IXGBE_SUCCESS;
1559 err_read_i2c_eeprom:
1560 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1561 if (hw->phy.type != ixgbe_phy_nl) {
1563 hw->phy.type = ixgbe_phy_unknown;
1565 return IXGBE_ERR_SFP_NOT_PRESENT;
1569 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1570 * @hw: pointer to hardware structure
1572 * Determines physical layer capabilities of the current SFP.
1574 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1576 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1577 u8 comp_codes_10g = 0;
1578 u8 comp_codes_1g = 0;
1580 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1582 hw->phy.ops.identify_sfp(hw);
1583 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1584 return physical_layer;
1586 switch (hw->phy.type) {
1587 case ixgbe_phy_sfp_passive_tyco:
1588 case ixgbe_phy_sfp_passive_unknown:
1589 case ixgbe_phy_qsfp_passive_unknown:
1590 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1592 case ixgbe_phy_sfp_ftl_active:
1593 case ixgbe_phy_sfp_active_unknown:
1594 case ixgbe_phy_qsfp_active_unknown:
1595 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1597 case ixgbe_phy_sfp_avago:
1598 case ixgbe_phy_sfp_ftl:
1599 case ixgbe_phy_sfp_intel:
1600 case ixgbe_phy_sfp_unknown:
1601 hw->phy.ops.read_i2c_eeprom(hw,
1602 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1603 hw->phy.ops.read_i2c_eeprom(hw,
1604 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1605 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1606 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1607 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1608 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1609 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1610 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1611 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1612 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1614 case ixgbe_phy_qsfp_intel:
1615 case ixgbe_phy_qsfp_unknown:
1616 hw->phy.ops.read_i2c_eeprom(hw,
1617 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1618 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1619 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1620 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1621 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1627 return physical_layer;
1631 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1632 * @hw: pointer to hardware structure
1634 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1636 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1638 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1640 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1642 u8 comp_codes_1g = 0;
1643 u8 comp_codes_10g = 0;
1644 u8 oui_bytes[3] = {0, 0, 0};
1645 u16 enforce_sfp = 0;
1647 u8 cable_length = 0;
1649 bool active_cable = FALSE;
1651 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1653 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1654 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1655 status = IXGBE_ERR_SFP_NOT_PRESENT;
1659 /* LAN ID is needed for I2C access */
1660 hw->mac.ops.set_lan_id(hw);
1662 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1665 if (status != IXGBE_SUCCESS)
1666 goto err_read_i2c_eeprom;
1668 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1669 hw->phy.type = ixgbe_phy_sfp_unsupported;
1670 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1674 hw->phy.id = identifier;
1676 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1679 if (status != IXGBE_SUCCESS)
1680 goto err_read_i2c_eeprom;
1682 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1685 if (status != IXGBE_SUCCESS)
1686 goto err_read_i2c_eeprom;
1688 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1689 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1690 if (hw->bus.lan_id == 0)
1691 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1693 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1694 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1695 IXGBE_SFF_10GBASELR_CAPABLE)) {
1696 if (hw->bus.lan_id == 0)
1697 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1699 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1701 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1702 active_cable = TRUE;
1704 if (!active_cable) {
1705 /* check for active DA cables that pre-date
1707 hw->phy.ops.read_i2c_eeprom(hw,
1708 IXGBE_SFF_QSFP_CONNECTOR,
1711 hw->phy.ops.read_i2c_eeprom(hw,
1712 IXGBE_SFF_QSFP_CABLE_LENGTH,
1715 hw->phy.ops.read_i2c_eeprom(hw,
1716 IXGBE_SFF_QSFP_DEVICE_TECH,
1720 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1721 (cable_length > 0) &&
1722 ((device_tech >> 4) ==
1723 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1724 active_cable = TRUE;
1728 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1729 if (hw->bus.lan_id == 0)
1731 ixgbe_sfp_type_da_act_lmt_core0;
1734 ixgbe_sfp_type_da_act_lmt_core1;
1736 /* unsupported module type */
1737 hw->phy.type = ixgbe_phy_sfp_unsupported;
1738 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1743 if (hw->phy.sfp_type != stored_sfp_type)
1744 hw->phy.sfp_setup_needed = TRUE;
1746 /* Determine if the QSFP+ PHY is dual speed or not. */
1747 hw->phy.multispeed_fiber = FALSE;
1748 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1749 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1750 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1751 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1752 hw->phy.multispeed_fiber = TRUE;
1754 /* Determine PHY vendor for optical modules */
1755 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1756 IXGBE_SFF_10GBASELR_CAPABLE)) {
1757 status = hw->phy.ops.read_i2c_eeprom(hw,
1758 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1761 if (status != IXGBE_SUCCESS)
1762 goto err_read_i2c_eeprom;
1764 status = hw->phy.ops.read_i2c_eeprom(hw,
1765 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1768 if (status != IXGBE_SUCCESS)
1769 goto err_read_i2c_eeprom;
1771 status = hw->phy.ops.read_i2c_eeprom(hw,
1772 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1775 if (status != IXGBE_SUCCESS)
1776 goto err_read_i2c_eeprom;
1779 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1780 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1781 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1783 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1784 hw->phy.type = ixgbe_phy_qsfp_intel;
1786 hw->phy.type = ixgbe_phy_qsfp_unknown;
1788 ixgbe_get_device_caps(hw, &enforce_sfp);
1789 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1790 /* Make sure we're a supported PHY type */
1791 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1792 status = IXGBE_SUCCESS;
1794 if (hw->allow_unsupported_sfp == TRUE) {
1795 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1796 status = IXGBE_SUCCESS;
1798 DEBUGOUT("QSFP module not supported\n");
1800 ixgbe_phy_sfp_unsupported;
1801 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1805 status = IXGBE_SUCCESS;
1812 err_read_i2c_eeprom:
1813 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1815 hw->phy.type = ixgbe_phy_unknown;
1817 return IXGBE_ERR_SFP_NOT_PRESENT;
1821 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1822 * @hw: pointer to hardware structure
1823 * @list_offset: offset to the SFP ID list
1824 * @data_offset: offset to the SFP data block
1826 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1827 * so it returns the offsets to the phy init sequence block.
1829 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1834 u16 sfp_type = hw->phy.sfp_type;
1836 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1838 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1839 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1841 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1842 return IXGBE_ERR_SFP_NOT_PRESENT;
1844 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1845 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1846 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1849 * Limiting active cables and 1G Phys must be initialized as
1852 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1853 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1854 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1855 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1856 sfp_type = ixgbe_sfp_type_srlr_core0;
1857 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1858 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1859 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1860 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1861 sfp_type = ixgbe_sfp_type_srlr_core1;
1863 /* Read offset to PHY init contents */
1864 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1865 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1866 "eeprom read at offset %d failed",
1867 IXGBE_PHY_INIT_OFFSET_NL);
1868 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1871 if ((!*list_offset) || (*list_offset == 0xFFFF))
1872 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1874 /* Shift offset to first ID word */
1878 * Find the matching SFP ID in the EEPROM
1879 * and program the init sequence
1881 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1884 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1885 if (sfp_id == sfp_type) {
1887 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1889 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1890 DEBUGOUT("SFP+ module not supported\n");
1891 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1896 (*list_offset) += 2;
1897 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1902 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1903 DEBUGOUT("No matching SFP+ module found\n");
1904 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1907 return IXGBE_SUCCESS;
1910 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1911 "eeprom read at offset %d failed", *list_offset);
1912 return IXGBE_ERR_PHY;
1916 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1917 * @hw: pointer to hardware structure
1918 * @byte_offset: EEPROM byte offset to read
1919 * @eeprom_data: value read
1921 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1923 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1926 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1928 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1929 IXGBE_I2C_EEPROM_DEV_ADDR,
1934 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1935 * @hw: pointer to hardware structure
1936 * @byte_offset: byte offset at address 0xA2
1937 * @eeprom_data: value read
1939 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1941 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1944 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1945 IXGBE_I2C_EEPROM_DEV_ADDR2,
1950 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1951 * @hw: pointer to hardware structure
1952 * @byte_offset: EEPROM byte offset to write
1953 * @eeprom_data: value to write
1955 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1957 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1960 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1962 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1963 IXGBE_I2C_EEPROM_DEV_ADDR,
1968 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected
1969 * @hw: pointer to hardware structure
1970 * @offset: eeprom offset to be read
1971 * @addr: I2C address to be read
1973 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1975 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1976 offset == IXGBE_SFF_IDENTIFIER &&
1977 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1983 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1984 * @hw: pointer to hardware structure
1985 * @byte_offset: byte offset to read
1987 * @lock: TRUE if to take and release semaphore
1989 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1990 * a specified device address.
1992 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1993 u8 dev_addr, u8 *data, bool lock)
1998 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2002 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2004 if (hw->mac.type >= ixgbe_mac_X550)
2006 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2007 max_retry = IXGBE_SFP_DETECT_RETRIES;
2010 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2011 return IXGBE_ERR_SWFW_SYNC;
2013 ixgbe_i2c_start(hw);
2015 /* Device Address and write indication */
2016 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2017 if (status != IXGBE_SUCCESS)
2020 status = ixgbe_get_i2c_ack(hw);
2021 if (status != IXGBE_SUCCESS)
2024 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2025 if (status != IXGBE_SUCCESS)
2028 status = ixgbe_get_i2c_ack(hw);
2029 if (status != IXGBE_SUCCESS)
2032 ixgbe_i2c_start(hw);
2034 /* Device Address and read indication */
2035 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2036 if (status != IXGBE_SUCCESS)
2039 status = ixgbe_get_i2c_ack(hw);
2040 if (status != IXGBE_SUCCESS)
2043 status = ixgbe_clock_in_i2c_byte(hw, data);
2044 if (status != IXGBE_SUCCESS)
2047 status = ixgbe_clock_out_i2c_bit(hw, nack);
2048 if (status != IXGBE_SUCCESS)
2053 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2054 return IXGBE_SUCCESS;
2057 ixgbe_i2c_bus_clear(hw);
2059 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2063 if (retry < max_retry)
2064 DEBUGOUT("I2C byte read error - Retrying.\n");
2066 DEBUGOUT("I2C byte read error.\n");
2068 } while (retry < max_retry);
2074 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2075 * @hw: pointer to hardware structure
2076 * @byte_offset: byte offset to read
2079 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2080 * a specified device address.
2082 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2083 u8 dev_addr, u8 *data)
2085 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2090 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2091 * @hw: pointer to hardware structure
2092 * @byte_offset: byte offset to read
2095 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2096 * a specified device address.
2098 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2099 u8 dev_addr, u8 *data)
2101 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2106 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2107 * @hw: pointer to hardware structure
2108 * @byte_offset: byte offset to write
2109 * @data: value to write
2110 * @lock: TRUE if to take and release semaphore
2112 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2113 * a specified device address.
2115 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2116 u8 dev_addr, u8 data, bool lock)
2121 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2123 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2125 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2127 return IXGBE_ERR_SWFW_SYNC;
2130 ixgbe_i2c_start(hw);
2132 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2133 if (status != IXGBE_SUCCESS)
2136 status = ixgbe_get_i2c_ack(hw);
2137 if (status != IXGBE_SUCCESS)
2140 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2141 if (status != IXGBE_SUCCESS)
2144 status = ixgbe_get_i2c_ack(hw);
2145 if (status != IXGBE_SUCCESS)
2148 status = ixgbe_clock_out_i2c_byte(hw, data);
2149 if (status != IXGBE_SUCCESS)
2152 status = ixgbe_get_i2c_ack(hw);
2153 if (status != IXGBE_SUCCESS)
2158 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2159 return IXGBE_SUCCESS;
2162 ixgbe_i2c_bus_clear(hw);
2164 if (retry < max_retry)
2165 DEBUGOUT("I2C byte write error - Retrying.\n");
2167 DEBUGOUT("I2C byte write error.\n");
2168 } while (retry < max_retry);
2171 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2177 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2178 * @hw: pointer to hardware structure
2179 * @byte_offset: byte offset to write
2180 * @data: value to write
2182 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2183 * a specified device address.
2185 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2186 u8 dev_addr, u8 data)
2188 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2193 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2194 * @hw: pointer to hardware structure
2195 * @byte_offset: byte offset to write
2196 * @data: value to write
2198 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2199 * a specified device address.
2201 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2202 u8 dev_addr, u8 data)
2204 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2209 * ixgbe_i2c_start - Sets I2C start condition
2210 * @hw: pointer to hardware structure
2212 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2213 * Set bit-bang mode on X550 hardware.
2215 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2217 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2219 DEBUGFUNC("ixgbe_i2c_start");
2221 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2223 /* Start condition must begin with data and clock high */
2224 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2225 ixgbe_raise_i2c_clk(hw, &i2cctl);
2227 /* Setup time for start condition (4.7us) */
2228 usec_delay(IXGBE_I2C_T_SU_STA);
2230 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2232 /* Hold time for start condition (4us) */
2233 usec_delay(IXGBE_I2C_T_HD_STA);
2235 ixgbe_lower_i2c_clk(hw, &i2cctl);
2237 /* Minimum low period of clock is 4.7 us */
2238 usec_delay(IXGBE_I2C_T_LOW);
2243 * ixgbe_i2c_stop - Sets I2C stop condition
2244 * @hw: pointer to hardware structure
2246 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2247 * Disables bit-bang mode and negates data output enable on X550
2250 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2252 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2253 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2254 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2255 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2257 DEBUGFUNC("ixgbe_i2c_stop");
2259 /* Stop condition must begin with data low and clock high */
2260 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2261 ixgbe_raise_i2c_clk(hw, &i2cctl);
2263 /* Setup time for stop condition (4us) */
2264 usec_delay(IXGBE_I2C_T_SU_STO);
2266 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2268 /* bus free time between stop and start (4.7us)*/
2269 usec_delay(IXGBE_I2C_T_BUF);
2271 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2272 i2cctl &= ~bb_en_bit;
2273 i2cctl |= data_oe_bit | clk_oe_bit;
2274 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2275 IXGBE_WRITE_FLUSH(hw);
2280 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2281 * @hw: pointer to hardware structure
2282 * @data: data byte to clock in
2284 * Clocks in one byte data via I2C data/clock
2286 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2291 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2294 for (i = 7; i >= 0; i--) {
2295 ixgbe_clock_in_i2c_bit(hw, &bit);
2299 return IXGBE_SUCCESS;
2303 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2304 * @hw: pointer to hardware structure
2305 * @data: data byte clocked out
2307 * Clocks out one byte data via I2C data/clock
2309 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2311 s32 status = IXGBE_SUCCESS;
2316 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2318 for (i = 7; i >= 0; i--) {
2319 bit = (data >> i) & 0x1;
2320 status = ixgbe_clock_out_i2c_bit(hw, bit);
2322 if (status != IXGBE_SUCCESS)
2326 /* Release SDA line (set high) */
2327 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2328 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2329 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2330 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2331 IXGBE_WRITE_FLUSH(hw);
2337 * ixgbe_get_i2c_ack - Polls for I2C ACK
2338 * @hw: pointer to hardware structure
2340 * Clocks in/out one bit via I2C data/clock
2342 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2344 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2345 s32 status = IXGBE_SUCCESS;
2347 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2351 DEBUGFUNC("ixgbe_get_i2c_ack");
2354 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2355 i2cctl |= data_oe_bit;
2356 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2357 IXGBE_WRITE_FLUSH(hw);
2359 ixgbe_raise_i2c_clk(hw, &i2cctl);
2361 /* Minimum high period of clock is 4us */
2362 usec_delay(IXGBE_I2C_T_HIGH);
2364 /* Poll for ACK. Note that ACK in I2C spec is
2365 * transition from 1 to 0 */
2366 for (i = 0; i < timeout; i++) {
2367 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2368 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2376 DEBUGOUT("I2C ack was not received.\n");
2377 status = IXGBE_ERR_I2C;
2380 ixgbe_lower_i2c_clk(hw, &i2cctl);
2382 /* Minimum low period of clock is 4.7 us */
2383 usec_delay(IXGBE_I2C_T_LOW);
2389 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2390 * @hw: pointer to hardware structure
2391 * @data: read data value
2393 * Clocks in one bit via I2C data/clock
2395 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2397 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2398 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2400 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2403 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2404 i2cctl |= data_oe_bit;
2405 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2406 IXGBE_WRITE_FLUSH(hw);
2408 ixgbe_raise_i2c_clk(hw, &i2cctl);
2410 /* Minimum high period of clock is 4us */
2411 usec_delay(IXGBE_I2C_T_HIGH);
2413 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2414 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2416 ixgbe_lower_i2c_clk(hw, &i2cctl);
2418 /* Minimum low period of clock is 4.7 us */
2419 usec_delay(IXGBE_I2C_T_LOW);
2421 return IXGBE_SUCCESS;
2425 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2426 * @hw: pointer to hardware structure
2427 * @data: data value to write
2429 * Clocks out one bit via I2C data/clock
2431 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2434 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2436 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2438 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2439 if (status == IXGBE_SUCCESS) {
2440 ixgbe_raise_i2c_clk(hw, &i2cctl);
2442 /* Minimum high period of clock is 4us */
2443 usec_delay(IXGBE_I2C_T_HIGH);
2445 ixgbe_lower_i2c_clk(hw, &i2cctl);
2447 /* Minimum low period of clock is 4.7 us.
2448 * This also takes care of the data hold time.
2450 usec_delay(IXGBE_I2C_T_LOW);
2452 status = IXGBE_ERR_I2C;
2453 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2454 "I2C data was not set to %X\n", data);
2461 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2462 * @hw: pointer to hardware structure
2463 * @i2cctl: Current value of I2CCTL register
2465 * Raises the I2C clock line '0'->'1'
2466 * Negates the I2C clock output enable on X550 hardware.
2468 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2470 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2472 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2475 DEBUGFUNC("ixgbe_raise_i2c_clk");
2478 *i2cctl |= clk_oe_bit;
2479 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2482 for (i = 0; i < timeout; i++) {
2483 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2485 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2486 IXGBE_WRITE_FLUSH(hw);
2487 /* SCL rise time (1000ns) */
2488 usec_delay(IXGBE_I2C_T_RISE);
2490 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2491 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2497 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2498 * @hw: pointer to hardware structure
2499 * @i2cctl: Current value of I2CCTL register
2501 * Lowers the I2C clock line '1'->'0'
2502 * Asserts the I2C clock output enable on X550 hardware.
2504 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2506 DEBUGFUNC("ixgbe_lower_i2c_clk");
2508 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2509 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2511 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2512 IXGBE_WRITE_FLUSH(hw);
2514 /* SCL fall time (300ns) */
2515 usec_delay(IXGBE_I2C_T_FALL);
2519 * ixgbe_set_i2c_data - Sets the I2C data bit
2520 * @hw: pointer to hardware structure
2521 * @i2cctl: Current value of I2CCTL register
2522 * @data: I2C data value (0 or 1) to set
2524 * Sets the I2C data bit
2525 * Asserts the I2C data output enable on X550 hardware.
2527 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2529 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2530 s32 status = IXGBE_SUCCESS;
2532 DEBUGFUNC("ixgbe_set_i2c_data");
2535 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2537 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2538 *i2cctl &= ~data_oe_bit;
2540 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2541 IXGBE_WRITE_FLUSH(hw);
2543 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2544 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2546 if (!data) /* Can't verify data in this case */
2547 return IXGBE_SUCCESS;
2549 *i2cctl |= data_oe_bit;
2550 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2551 IXGBE_WRITE_FLUSH(hw);
2554 /* Verify data was set correctly */
2555 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2556 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2557 status = IXGBE_ERR_I2C;
2558 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2559 "Error - I2C data was not set to %X.\n",
2567 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2568 * @hw: pointer to hardware structure
2569 * @i2cctl: Current value of I2CCTL register
2571 * Returns the I2C data bit value
2572 * Negates the I2C data output enable on X550 hardware.
2574 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2576 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2579 DEBUGFUNC("ixgbe_get_i2c_data");
2582 *i2cctl |= data_oe_bit;
2583 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2584 IXGBE_WRITE_FLUSH(hw);
2585 usec_delay(IXGBE_I2C_T_FALL);
2588 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2597 * ixgbe_i2c_bus_clear - Clears the I2C bus
2598 * @hw: pointer to hardware structure
2600 * Clears the I2C bus by sending nine clock pulses.
2601 * Used when data line is stuck low.
2603 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2608 DEBUGFUNC("ixgbe_i2c_bus_clear");
2610 ixgbe_i2c_start(hw);
2611 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2613 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2615 for (i = 0; i < 9; i++) {
2616 ixgbe_raise_i2c_clk(hw, &i2cctl);
2618 /* Min high period of clock is 4us */
2619 usec_delay(IXGBE_I2C_T_HIGH);
2621 ixgbe_lower_i2c_clk(hw, &i2cctl);
2623 /* Min low period of clock is 4.7us*/
2624 usec_delay(IXGBE_I2C_T_LOW);
2627 ixgbe_i2c_start(hw);
2629 /* Put the i2c bus back to default state */
2634 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2635 * @hw: pointer to hardware structure
2637 * Checks if the LASI temp alarm status was triggered due to overtemp
2639 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2641 s32 status = IXGBE_SUCCESS;
2644 DEBUGFUNC("ixgbe_tn_check_overtemp");
2646 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2649 /* Check that the LASI temp alarm status was triggered */
2650 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2651 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2653 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2656 status = IXGBE_ERR_OVERTEMP;
2657 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2663 * ixgbe_set_copper_phy_power - Control power for copper phy
2664 * @hw: pointer to hardware structure
2665 * @on: TRUE for on, FALSE for off
2667 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2672 if (!on && ixgbe_mng_present(hw))
2675 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2676 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2682 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2684 if (ixgbe_check_reset_blocked(hw))
2686 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2689 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2690 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,