1 /******************************************************************************
3 Copyright (c) 2001-2013, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "ixgbe_api.h"
36 #include "ixgbe_common.h"
37 #include "ixgbe_phy.h"
39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 static bool ixgbe_get_i2c_data(u32 *i2cctl);
50 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
54 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
55 * @hw: pointer to the hardware structure
57 * Initialize the function pointers.
59 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
61 struct ixgbe_phy_info *phy = &hw->phy;
63 DEBUGFUNC("ixgbe_init_phy_ops_generic");
66 phy->ops.identify = &ixgbe_identify_phy_generic;
67 phy->ops.reset = &ixgbe_reset_phy_generic;
68 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
69 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
70 phy->ops.read_reg_mdi = &ixgbe_read_phy_reg_mdi;
71 phy->ops.write_reg_mdi = &ixgbe_write_phy_reg_mdi;
72 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
73 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
74 phy->ops.check_link = NULL;
75 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
76 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
77 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
78 phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic;
79 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
80 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
81 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
82 phy->ops.identify_sfp = &ixgbe_identify_module_generic;
83 phy->sfp_type = ixgbe_sfp_type_unknown;
84 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
89 * ixgbe_identify_phy_generic - Get physical layer module
90 * @hw: pointer to hardware structure
92 * Determines the physical layer module found on the current adapter.
94 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
96 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
100 DEBUGFUNC("ixgbe_identify_phy_generic");
102 if (hw->phy.type == ixgbe_phy_unknown) {
103 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
104 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
105 hw->phy.addr = phy_addr;
106 ixgbe_get_phy_id(hw);
108 ixgbe_get_phy_type_from_id(hw->phy.id);
110 if (hw->phy.type == ixgbe_phy_unknown) {
111 hw->phy.ops.read_reg(hw,
112 IXGBE_MDIO_PHY_EXT_ABILITY,
113 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
116 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
117 IXGBE_MDIO_PHY_1000BASET_ABILITY))
119 ixgbe_phy_cu_unknown;
125 status = IXGBE_SUCCESS;
129 /* clear value if nothing found */
130 if (status != IXGBE_SUCCESS) {
132 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
133 "Could not identify valid PHY address");
136 status = IXGBE_SUCCESS;
143 * ixgbe_validate_phy_addr - Determines phy address is valid
144 * @hw: pointer to hardware structure
147 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
152 DEBUGFUNC("ixgbe_validate_phy_addr");
154 hw->phy.addr = phy_addr;
155 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
156 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
158 if (phy_id != 0xFFFF && phy_id != 0x0)
165 * ixgbe_get_phy_id - Get the phy type
166 * @hw: pointer to hardware structure
169 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
175 DEBUGFUNC("ixgbe_get_phy_id");
177 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
178 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
181 if (status == IXGBE_SUCCESS) {
182 hw->phy.id = (u32)(phy_id_high << 16);
183 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
184 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
186 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
187 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
193 * ixgbe_get_phy_type_from_id - Get the phy type
194 * @hw: pointer to hardware structure
197 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
199 enum ixgbe_phy_type phy_type;
201 DEBUGFUNC("ixgbe_get_phy_type_from_id");
205 phy_type = ixgbe_phy_tn;
208 phy_type = ixgbe_phy_aq;
211 phy_type = ixgbe_phy_qt;
214 phy_type = ixgbe_phy_nl;
217 phy_type = ixgbe_phy_unknown;
221 DEBUGOUT1("phy type found is %d\n", phy_type);
226 * ixgbe_reset_phy_generic - Performs a PHY reset
227 * @hw: pointer to hardware structure
229 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
233 s32 status = IXGBE_SUCCESS;
235 DEBUGFUNC("ixgbe_reset_phy_generic");
237 if (hw->phy.type == ixgbe_phy_unknown)
238 status = ixgbe_identify_phy_generic(hw);
240 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
243 /* Don't reset PHY if it's shut down due to overtemp. */
244 if (!hw->phy.reset_if_overtemp &&
245 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
249 * Perform soft PHY reset to the PHY_XS.
250 * This will cause a soft reset to the PHY
252 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
253 IXGBE_MDIO_PHY_XS_DEV_TYPE,
254 IXGBE_MDIO_PHY_XS_RESET);
257 * Poll for reset bit to self-clear indicating reset is complete.
258 * Some PHYs could take up to 3 seconds to complete and need about
259 * 1.7 usec delay after the reset is complete.
261 for (i = 0; i < 30; i++) {
263 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
264 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
265 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
271 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
272 status = IXGBE_ERR_RESET_FAILED;
273 ERROR_REPORT1(IXGBE_ERROR_POLLING,
274 "PHY reset polling failed to complete.\n");
282 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
284 * @hw: pointer to hardware structure
285 * @reg_addr: 32 bit address of PHY register to read
286 * @phy_data: Pointer to read data from PHY register
288 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
291 u32 i, data, command;
293 /* Setup and write the address cycle command */
294 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
295 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
296 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
297 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
299 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
302 * Check every 10 usec to see if the address cycle completed.
303 * The MDI Command bit will clear when the operation is
306 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
309 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
310 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
315 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
316 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
317 return IXGBE_ERR_PHY;
321 * Address cycle complete, setup and write the read
324 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
325 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
326 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
327 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
329 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
332 * Check every 10 usec to see if the address cycle
333 * completed. The MDI Command bit will clear when the
334 * operation is complete
336 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
339 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
340 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
344 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
345 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
346 return IXGBE_ERR_PHY;
350 * Read operation is complete. Get the data
353 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
354 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
355 *phy_data = (u16)(data);
357 return IXGBE_SUCCESS;
361 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
362 * using the SWFW lock - this function is needed in most cases
363 * @hw: pointer to hardware structure
364 * @reg_addr: 32 bit address of PHY register to read
365 * @phy_data: Pointer to read data from PHY register
367 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
368 u32 device_type, u16 *phy_data)
373 DEBUGFUNC("ixgbe_read_phy_reg_generic");
375 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
376 gssr = IXGBE_GSSR_PHY1_SM;
378 gssr = IXGBE_GSSR_PHY0_SM;
380 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
381 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
383 hw->mac.ops.release_swfw_sync(hw, gssr);
385 status = IXGBE_ERR_SWFW_SYNC;
392 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
394 * @hw: pointer to hardware structure
395 * @reg_addr: 32 bit PHY register to write
396 * @device_type: 5 bit device type
397 * @phy_data: Data to write to the PHY register
399 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
400 u32 device_type, u16 phy_data)
404 /* Put the data in the MDI single read and write data register*/
405 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
407 /* Setup and write the address cycle command */
408 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
409 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
410 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
411 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
413 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
416 * Check every 10 usec to see if the address cycle completed.
417 * The MDI Command bit will clear when the operation is
420 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
423 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
424 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
428 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
429 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
430 return IXGBE_ERR_PHY;
434 * Address cycle complete, setup and write the write
437 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
438 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
439 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
440 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
442 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
445 * Check every 10 usec to see if the address cycle
446 * completed. The MDI Command bit will clear when the
447 * operation is complete
449 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
452 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
453 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
457 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
458 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
459 return IXGBE_ERR_PHY;
462 return IXGBE_SUCCESS;
466 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
467 * using SWFW lock- this function is needed in most cases
468 * @hw: pointer to hardware structure
469 * @reg_addr: 32 bit PHY register to write
470 * @device_type: 5 bit device type
471 * @phy_data: Data to write to the PHY register
473 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
474 u32 device_type, u16 phy_data)
479 DEBUGFUNC("ixgbe_write_phy_reg_generic");
481 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
482 gssr = IXGBE_GSSR_PHY1_SM;
484 gssr = IXGBE_GSSR_PHY0_SM;
486 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
487 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
489 hw->mac.ops.release_swfw_sync(hw, gssr);
491 status = IXGBE_ERR_SWFW_SYNC;
498 * ixgbe_setup_phy_link_generic - Set and restart autoneg
499 * @hw: pointer to hardware structure
501 * Restart autonegotiation and PHY and waits for completion.
503 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
505 s32 status = IXGBE_SUCCESS;
507 u32 max_time_out = 10;
508 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
509 bool autoneg = FALSE;
510 ixgbe_link_speed speed;
512 DEBUGFUNC("ixgbe_setup_phy_link_generic");
514 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
516 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
517 /* Set or unset auto-negotiation 10G advertisement */
518 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
519 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
522 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
523 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
524 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
526 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
527 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
531 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
532 /* Set or unset auto-negotiation 1G advertisement */
533 hw->phy.ops.read_reg(hw,
534 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
535 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
538 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
539 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
540 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
542 hw->phy.ops.write_reg(hw,
543 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
544 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
548 if (speed & IXGBE_LINK_SPEED_100_FULL) {
549 /* Set or unset auto-negotiation 100M advertisement */
550 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
551 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
554 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
555 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
556 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
557 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
559 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
560 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
564 /* Restart PHY autonegotiation and wait for completion */
565 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
566 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
568 autoneg_reg |= IXGBE_MII_RESTART;
570 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
571 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
573 /* Wait for autonegotiation to finish */
574 for (time_out = 0; time_out < max_time_out; time_out++) {
576 /* Restart PHY autonegotiation and wait for completion */
577 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
578 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
581 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
582 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
586 if (time_out == max_time_out) {
587 status = IXGBE_ERR_LINK_SETUP;
588 ERROR_REPORT1(IXGBE_ERROR_POLLING,
589 "PHY autonegotiation time out");
596 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
597 * @hw: pointer to hardware structure
598 * @speed: new link speed
600 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
601 ixgbe_link_speed speed,
602 bool autoneg_wait_to_complete)
604 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
606 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
609 * Clear autoneg_advertised and set new values based on input link
612 hw->phy.autoneg_advertised = 0;
614 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
615 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
617 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
618 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
620 if (speed & IXGBE_LINK_SPEED_100_FULL)
621 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
623 /* Setup link based on the new speed settings */
624 hw->phy.ops.setup_link(hw);
626 return IXGBE_SUCCESS;
630 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
631 * @hw: pointer to hardware structure
632 * @speed: pointer to link speed
633 * @autoneg: boolean auto-negotiation value
635 * Determines the link capabilities by reading the AUTOC register.
637 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
638 ixgbe_link_speed *speed,
641 s32 status = IXGBE_ERR_LINK_SETUP;
644 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
649 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
650 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
653 if (status == IXGBE_SUCCESS) {
654 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
655 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
656 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
657 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
658 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
659 *speed |= IXGBE_LINK_SPEED_100_FULL;
666 * ixgbe_check_phy_link_tnx - Determine link and speed status
667 * @hw: pointer to hardware structure
669 * Reads the VS1 register to determine if link is up and the current speed for
672 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
675 s32 status = IXGBE_SUCCESS;
677 u32 max_time_out = 10;
682 DEBUGFUNC("ixgbe_check_phy_link_tnx");
684 /* Initialize speed and link to default case */
686 *speed = IXGBE_LINK_SPEED_10GB_FULL;
689 * Check current speed and link status of the PHY register.
690 * This is a vendor specific register and may have to
691 * be changed for other copper PHYs.
693 for (time_out = 0; time_out < max_time_out; time_out++) {
695 status = hw->phy.ops.read_reg(hw,
696 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
697 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
699 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
700 phy_speed = phy_data &
701 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
702 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
705 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
706 *speed = IXGBE_LINK_SPEED_1GB_FULL;
715 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
716 * @hw: pointer to hardware structure
718 * Restart autonegotiation and PHY and waits for completion.
720 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
722 s32 status = IXGBE_SUCCESS;
724 u32 max_time_out = 10;
725 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
726 bool autoneg = FALSE;
727 ixgbe_link_speed speed;
729 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
731 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
733 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
734 /* Set or unset auto-negotiation 10G advertisement */
735 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
736 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
739 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
740 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
741 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
743 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
744 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
748 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
749 /* Set or unset auto-negotiation 1G advertisement */
750 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
751 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
754 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
755 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
756 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
758 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
759 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
763 if (speed & IXGBE_LINK_SPEED_100_FULL) {
764 /* Set or unset auto-negotiation 100M advertisement */
765 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
766 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
769 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
770 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
771 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
773 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
774 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
778 /* Restart PHY autonegotiation and wait for completion */
779 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
780 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
782 autoneg_reg |= IXGBE_MII_RESTART;
784 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
785 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
787 /* Wait for autonegotiation to finish */
788 for (time_out = 0; time_out < max_time_out; time_out++) {
790 /* Restart PHY autonegotiation and wait for completion */
791 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
792 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
795 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
796 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
800 if (time_out == max_time_out) {
801 status = IXGBE_ERR_LINK_SETUP;
802 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
809 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
810 * @hw: pointer to hardware structure
811 * @firmware_version: pointer to the PHY Firmware Version
813 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
814 u16 *firmware_version)
816 s32 status = IXGBE_SUCCESS;
818 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
820 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
821 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
828 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
829 * @hw: pointer to hardware structure
830 * @firmware_version: pointer to the PHY Firmware Version
832 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
833 u16 *firmware_version)
835 s32 status = IXGBE_SUCCESS;
837 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
839 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
840 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
847 * ixgbe_reset_phy_nl - Performs a PHY reset
848 * @hw: pointer to hardware structure
850 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
852 u16 phy_offset, control, eword, edata, block_crc;
853 bool end_data = FALSE;
854 u16 list_offset, data_offset;
856 s32 ret_val = IXGBE_SUCCESS;
859 DEBUGFUNC("ixgbe_reset_phy_nl");
861 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
862 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
864 /* reset the PHY and poll for completion */
865 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
866 IXGBE_MDIO_PHY_XS_DEV_TYPE,
867 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
869 for (i = 0; i < 100; i++) {
870 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
871 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
872 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
877 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
878 DEBUGOUT("PHY reset did not complete.\n");
879 ret_val = IXGBE_ERR_PHY;
883 /* Get init offsets */
884 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
886 if (ret_val != IXGBE_SUCCESS)
889 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
893 * Read control word from PHY init contents offset
895 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
898 control = (eword & IXGBE_CONTROL_MASK_NL) >>
899 IXGBE_CONTROL_SHIFT_NL;
900 edata = eword & IXGBE_DATA_MASK_NL;
904 DEBUGOUT1("DELAY: %d MS\n", edata);
910 ret_val = hw->eeprom.ops.read(hw, data_offset,
915 for (i = 0; i < edata; i++) {
916 ret_val = hw->eeprom.ops.read(hw, data_offset,
920 hw->phy.ops.write_reg(hw, phy_offset,
921 IXGBE_TWINAX_DEV, eword);
922 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
928 case IXGBE_CONTROL_NL:
930 DEBUGOUT("CONTROL:\n");
931 if (edata == IXGBE_CONTROL_EOL_NL) {
934 } else if (edata == IXGBE_CONTROL_SOL_NL) {
937 DEBUGOUT("Bad control value\n");
938 ret_val = IXGBE_ERR_PHY;
943 DEBUGOUT("Bad control type\n");
944 ret_val = IXGBE_ERR_PHY;
953 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
954 "eeprom read at offset %d failed", data_offset);
955 return IXGBE_ERR_PHY;
959 * ixgbe_identify_module_generic - Identifies module type
960 * @hw: pointer to hardware structure
962 * Determines HW type and calls appropriate function.
964 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
966 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
968 DEBUGFUNC("ixgbe_identify_module_generic");
970 switch (hw->mac.ops.get_media_type(hw)) {
971 case ixgbe_media_type_fiber:
972 status = ixgbe_identify_sfp_module_generic(hw);
977 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
978 status = IXGBE_ERR_SFP_NOT_PRESENT;
986 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
987 * @hw: pointer to hardware structure
989 * Searches for and identifies the SFP module and assigns appropriate PHY type.
991 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
993 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
995 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
997 u8 comp_codes_1g = 0;
998 u8 comp_codes_10g = 0;
999 u8 oui_bytes[3] = {0, 0, 0};
1002 u16 enforce_sfp = 0;
1004 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1006 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1007 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1008 status = IXGBE_ERR_SFP_NOT_PRESENT;
1012 status = hw->phy.ops.read_i2c_eeprom(hw,
1013 IXGBE_SFF_IDENTIFIER,
1016 if (status != IXGBE_SUCCESS)
1017 goto err_read_i2c_eeprom;
1019 /* LAN ID is needed for sfp_type determination */
1020 hw->mac.ops.set_lan_id(hw);
1022 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1023 hw->phy.type = ixgbe_phy_sfp_unsupported;
1024 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1026 status = hw->phy.ops.read_i2c_eeprom(hw,
1027 IXGBE_SFF_1GBE_COMP_CODES,
1030 if (status != IXGBE_SUCCESS)
1031 goto err_read_i2c_eeprom;
1033 status = hw->phy.ops.read_i2c_eeprom(hw,
1034 IXGBE_SFF_10GBE_COMP_CODES,
1037 if (status != IXGBE_SUCCESS)
1038 goto err_read_i2c_eeprom;
1039 status = hw->phy.ops.read_i2c_eeprom(hw,
1040 IXGBE_SFF_CABLE_TECHNOLOGY,
1043 if (status != IXGBE_SUCCESS)
1044 goto err_read_i2c_eeprom;
1051 * 3 SFP_DA_CORE0 - 82599-specific
1052 * 4 SFP_DA_CORE1 - 82599-specific
1053 * 5 SFP_SR/LR_CORE0 - 82599-specific
1054 * 6 SFP_SR/LR_CORE1 - 82599-specific
1055 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1056 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1057 * 9 SFP_1g_cu_CORE0 - 82599-specific
1058 * 10 SFP_1g_cu_CORE1 - 82599-specific
1059 * 11 SFP_1g_sx_CORE0 - 82599-specific
1060 * 12 SFP_1g_sx_CORE1 - 82599-specific
1062 if (hw->mac.type == ixgbe_mac_82598EB) {
1063 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1064 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1065 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1066 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1067 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1068 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1070 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1071 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1072 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1073 if (hw->bus.lan_id == 0)
1075 ixgbe_sfp_type_da_cu_core0;
1078 ixgbe_sfp_type_da_cu_core1;
1079 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1080 hw->phy.ops.read_i2c_eeprom(
1081 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1084 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1085 if (hw->bus.lan_id == 0)
1087 ixgbe_sfp_type_da_act_lmt_core0;
1090 ixgbe_sfp_type_da_act_lmt_core1;
1093 ixgbe_sfp_type_unknown;
1095 } else if (comp_codes_10g &
1096 (IXGBE_SFF_10GBASESR_CAPABLE |
1097 IXGBE_SFF_10GBASELR_CAPABLE)) {
1098 if (hw->bus.lan_id == 0)
1100 ixgbe_sfp_type_srlr_core0;
1103 ixgbe_sfp_type_srlr_core1;
1104 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1105 if (hw->bus.lan_id == 0)
1107 ixgbe_sfp_type_1g_cu_core0;
1110 ixgbe_sfp_type_1g_cu_core1;
1111 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1112 if (hw->bus.lan_id == 0)
1114 ixgbe_sfp_type_1g_sx_core0;
1117 ixgbe_sfp_type_1g_sx_core1;
1119 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1123 if (hw->phy.sfp_type != stored_sfp_type)
1124 hw->phy.sfp_setup_needed = TRUE;
1126 /* Determine if the SFP+ PHY is dual speed or not. */
1127 hw->phy.multispeed_fiber = FALSE;
1128 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1129 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1130 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1131 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1132 hw->phy.multispeed_fiber = TRUE;
1134 /* Determine PHY vendor */
1135 if (hw->phy.type != ixgbe_phy_nl) {
1136 hw->phy.id = identifier;
1137 status = hw->phy.ops.read_i2c_eeprom(hw,
1138 IXGBE_SFF_VENDOR_OUI_BYTE0,
1141 if (status != IXGBE_SUCCESS)
1142 goto err_read_i2c_eeprom;
1144 status = hw->phy.ops.read_i2c_eeprom(hw,
1145 IXGBE_SFF_VENDOR_OUI_BYTE1,
1148 if (status != IXGBE_SUCCESS)
1149 goto err_read_i2c_eeprom;
1151 status = hw->phy.ops.read_i2c_eeprom(hw,
1152 IXGBE_SFF_VENDOR_OUI_BYTE2,
1155 if (status != IXGBE_SUCCESS)
1156 goto err_read_i2c_eeprom;
1159 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1160 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1161 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1163 switch (vendor_oui) {
1164 case IXGBE_SFF_VENDOR_OUI_TYCO:
1165 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1167 ixgbe_phy_sfp_passive_tyco;
1169 case IXGBE_SFF_VENDOR_OUI_FTL:
1170 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1171 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1173 hw->phy.type = ixgbe_phy_sfp_ftl;
1175 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1176 hw->phy.type = ixgbe_phy_sfp_avago;
1178 case IXGBE_SFF_VENDOR_OUI_INTEL:
1179 hw->phy.type = ixgbe_phy_sfp_intel;
1182 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1184 ixgbe_phy_sfp_passive_unknown;
1185 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1187 ixgbe_phy_sfp_active_unknown;
1189 hw->phy.type = ixgbe_phy_sfp_unknown;
1194 /* Allow any DA cable vendor */
1195 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1196 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1197 status = IXGBE_SUCCESS;
1201 /* Verify supported 1G SFP modules */
1202 if (comp_codes_10g == 0 &&
1203 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1204 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1205 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1206 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1207 hw->phy.type = ixgbe_phy_sfp_unsupported;
1208 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1212 /* Anything else 82598-based is supported */
1213 if (hw->mac.type == ixgbe_mac_82598EB) {
1214 status = IXGBE_SUCCESS;
1218 ixgbe_get_device_caps(hw, &enforce_sfp);
1219 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1220 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1221 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1222 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1223 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1224 /* Make sure we're a supported PHY type */
1225 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1226 status = IXGBE_SUCCESS;
1228 if (hw->allow_unsupported_sfp == TRUE) {
1229 EWARN(hw, "WARNING: Intel (R) Network "
1230 "Connections are quality tested "
1231 "using Intel (R) Ethernet Optics."
1232 " Using untested modules is not "
1233 "supported and may cause unstable"
1234 " operation or damage to the "
1235 "module or the adapter. Intel "
1236 "Corporation is not responsible "
1237 "for any harm caused by using "
1238 "untested modules.\n", status);
1239 status = IXGBE_SUCCESS;
1241 DEBUGOUT("SFP+ module not supported\n");
1243 ixgbe_phy_sfp_unsupported;
1244 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1248 status = IXGBE_SUCCESS;
1255 err_read_i2c_eeprom:
1256 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1257 if (hw->phy.type != ixgbe_phy_nl) {
1259 hw->phy.type = ixgbe_phy_unknown;
1261 return IXGBE_ERR_SFP_NOT_PRESENT;
1267 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1268 * @hw: pointer to hardware structure
1269 * @list_offset: offset to the SFP ID list
1270 * @data_offset: offset to the SFP data block
1272 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1273 * so it returns the offsets to the phy init sequence block.
1275 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1280 u16 sfp_type = hw->phy.sfp_type;
1282 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1284 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1285 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1287 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1288 return IXGBE_ERR_SFP_NOT_PRESENT;
1290 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1291 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1292 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1295 * Limiting active cables and 1G Phys must be initialized as
1298 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1299 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1300 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1301 sfp_type = ixgbe_sfp_type_srlr_core0;
1302 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1303 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1304 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1305 sfp_type = ixgbe_sfp_type_srlr_core1;
1307 /* Read offset to PHY init contents */
1308 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1309 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1310 "eeprom read at offset %d failed",
1311 IXGBE_PHY_INIT_OFFSET_NL);
1312 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1315 if ((!*list_offset) || (*list_offset == 0xFFFF))
1316 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1318 /* Shift offset to first ID word */
1322 * Find the matching SFP ID in the EEPROM
1323 * and program the init sequence
1325 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1328 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1329 if (sfp_id == sfp_type) {
1331 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1333 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1334 DEBUGOUT("SFP+ module not supported\n");
1335 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1340 (*list_offset) += 2;
1341 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1346 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1347 DEBUGOUT("No matching SFP+ module found\n");
1348 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1351 return IXGBE_SUCCESS;
1354 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1355 "eeprom read at offset %d failed", *list_offset);
1356 return IXGBE_ERR_PHY;
1360 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1361 * @hw: pointer to hardware structure
1362 * @byte_offset: EEPROM byte offset to read
1363 * @eeprom_data: value read
1365 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1367 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1370 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1372 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1373 IXGBE_I2C_EEPROM_DEV_ADDR,
1378 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1379 * @hw: pointer to hardware structure
1380 * @byte_offset: byte offset at address 0xA2
1381 * @eeprom_data: value read
1383 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1385 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1388 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1389 IXGBE_I2C_EEPROM_DEV_ADDR2,
1394 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1395 * @hw: pointer to hardware structure
1396 * @byte_offset: EEPROM byte offset to write
1397 * @eeprom_data: value to write
1399 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1401 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1404 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1406 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1407 IXGBE_I2C_EEPROM_DEV_ADDR,
1412 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1413 * @hw: pointer to hardware structure
1414 * @byte_offset: byte offset to read
1417 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1418 * a specified device address.
1420 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1421 u8 dev_addr, u8 *data)
1423 s32 status = IXGBE_SUCCESS;
1430 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1432 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1433 swfw_mask = IXGBE_GSSR_PHY1_SM;
1435 swfw_mask = IXGBE_GSSR_PHY0_SM;
1438 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1440 status = IXGBE_ERR_SWFW_SYNC;
1444 ixgbe_i2c_start(hw);
1446 /* Device Address and write indication */
1447 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1448 if (status != IXGBE_SUCCESS)
1451 status = ixgbe_get_i2c_ack(hw);
1452 if (status != IXGBE_SUCCESS)
1455 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1456 if (status != IXGBE_SUCCESS)
1459 status = ixgbe_get_i2c_ack(hw);
1460 if (status != IXGBE_SUCCESS)
1463 ixgbe_i2c_start(hw);
1465 /* Device Address and read indication */
1466 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1467 if (status != IXGBE_SUCCESS)
1470 status = ixgbe_get_i2c_ack(hw);
1471 if (status != IXGBE_SUCCESS)
1474 status = ixgbe_clock_in_i2c_byte(hw, data);
1475 if (status != IXGBE_SUCCESS)
1478 status = ixgbe_clock_out_i2c_bit(hw, nack);
1479 if (status != IXGBE_SUCCESS)
1486 ixgbe_i2c_bus_clear(hw);
1487 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1490 if (retry < max_retry)
1491 DEBUGOUT("I2C byte read error - Retrying.\n");
1493 DEBUGOUT("I2C byte read error.\n");
1495 } while (retry < max_retry);
1497 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1504 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1505 * @hw: pointer to hardware structure
1506 * @byte_offset: byte offset to write
1507 * @data: value to write
1509 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1510 * a specified device address.
1512 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1513 u8 dev_addr, u8 data)
1515 s32 status = IXGBE_SUCCESS;
1520 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1522 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1523 swfw_mask = IXGBE_GSSR_PHY1_SM;
1525 swfw_mask = IXGBE_GSSR_PHY0_SM;
1527 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1528 status = IXGBE_ERR_SWFW_SYNC;
1529 goto write_byte_out;
1533 ixgbe_i2c_start(hw);
1535 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1536 if (status != IXGBE_SUCCESS)
1539 status = ixgbe_get_i2c_ack(hw);
1540 if (status != IXGBE_SUCCESS)
1543 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1544 if (status != IXGBE_SUCCESS)
1547 status = ixgbe_get_i2c_ack(hw);
1548 if (status != IXGBE_SUCCESS)
1551 status = ixgbe_clock_out_i2c_byte(hw, data);
1552 if (status != IXGBE_SUCCESS)
1555 status = ixgbe_get_i2c_ack(hw);
1556 if (status != IXGBE_SUCCESS)
1563 ixgbe_i2c_bus_clear(hw);
1565 if (retry < max_retry)
1566 DEBUGOUT("I2C byte write error - Retrying.\n");
1568 DEBUGOUT("I2C byte write error.\n");
1569 } while (retry < max_retry);
1571 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1578 * ixgbe_i2c_start - Sets I2C start condition
1579 * @hw: pointer to hardware structure
1581 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1583 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1585 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1587 DEBUGFUNC("ixgbe_i2c_start");
1589 /* Start condition must begin with data and clock high */
1590 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1591 ixgbe_raise_i2c_clk(hw, &i2cctl);
1593 /* Setup time for start condition (4.7us) */
1594 usec_delay(IXGBE_I2C_T_SU_STA);
1596 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1598 /* Hold time for start condition (4us) */
1599 usec_delay(IXGBE_I2C_T_HD_STA);
1601 ixgbe_lower_i2c_clk(hw, &i2cctl);
1603 /* Minimum low period of clock is 4.7 us */
1604 usec_delay(IXGBE_I2C_T_LOW);
1609 * ixgbe_i2c_stop - Sets I2C stop condition
1610 * @hw: pointer to hardware structure
1612 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1614 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1616 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1618 DEBUGFUNC("ixgbe_i2c_stop");
1620 /* Stop condition must begin with data low and clock high */
1621 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1622 ixgbe_raise_i2c_clk(hw, &i2cctl);
1624 /* Setup time for stop condition (4us) */
1625 usec_delay(IXGBE_I2C_T_SU_STO);
1627 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1629 /* bus free time between stop and start (4.7us)*/
1630 usec_delay(IXGBE_I2C_T_BUF);
1634 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1635 * @hw: pointer to hardware structure
1636 * @data: data byte to clock in
1638 * Clocks in one byte data via I2C data/clock
1640 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1645 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1647 for (i = 7; i >= 0; i--) {
1648 ixgbe_clock_in_i2c_bit(hw, &bit);
1652 return IXGBE_SUCCESS;
1656 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1657 * @hw: pointer to hardware structure
1658 * @data: data byte clocked out
1660 * Clocks out one byte data via I2C data/clock
1662 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1664 s32 status = IXGBE_SUCCESS;
1669 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1671 for (i = 7; i >= 0; i--) {
1672 bit = (data >> i) & 0x1;
1673 status = ixgbe_clock_out_i2c_bit(hw, bit);
1675 if (status != IXGBE_SUCCESS)
1679 /* Release SDA line (set high) */
1680 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1681 i2cctl |= IXGBE_I2C_DATA_OUT;
1682 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1683 IXGBE_WRITE_FLUSH(hw);
1689 * ixgbe_get_i2c_ack - Polls for I2C ACK
1690 * @hw: pointer to hardware structure
1692 * Clocks in/out one bit via I2C data/clock
1694 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1696 s32 status = IXGBE_SUCCESS;
1698 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1702 DEBUGFUNC("ixgbe_get_i2c_ack");
1704 ixgbe_raise_i2c_clk(hw, &i2cctl);
1707 /* Minimum high period of clock is 4us */
1708 usec_delay(IXGBE_I2C_T_HIGH);
1710 /* Poll for ACK. Note that ACK in I2C spec is
1711 * transition from 1 to 0 */
1712 for (i = 0; i < timeout; i++) {
1713 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1714 ack = ixgbe_get_i2c_data(&i2cctl);
1722 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1723 "I2C ack was not received.\n");
1724 status = IXGBE_ERR_I2C;
1727 ixgbe_lower_i2c_clk(hw, &i2cctl);
1729 /* Minimum low period of clock is 4.7 us */
1730 usec_delay(IXGBE_I2C_T_LOW);
1736 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1737 * @hw: pointer to hardware structure
1738 * @data: read data value
1740 * Clocks in one bit via I2C data/clock
1742 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1744 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1746 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1748 ixgbe_raise_i2c_clk(hw, &i2cctl);
1750 /* Minimum high period of clock is 4us */
1751 usec_delay(IXGBE_I2C_T_HIGH);
1753 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1754 *data = ixgbe_get_i2c_data(&i2cctl);
1756 ixgbe_lower_i2c_clk(hw, &i2cctl);
1758 /* Minimum low period of clock is 4.7 us */
1759 usec_delay(IXGBE_I2C_T_LOW);
1761 return IXGBE_SUCCESS;
1765 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1766 * @hw: pointer to hardware structure
1767 * @data: data value to write
1769 * Clocks out one bit via I2C data/clock
1771 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1774 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1776 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1778 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1779 if (status == IXGBE_SUCCESS) {
1780 ixgbe_raise_i2c_clk(hw, &i2cctl);
1782 /* Minimum high period of clock is 4us */
1783 usec_delay(IXGBE_I2C_T_HIGH);
1785 ixgbe_lower_i2c_clk(hw, &i2cctl);
1787 /* Minimum low period of clock is 4.7 us.
1788 * This also takes care of the data hold time.
1790 usec_delay(IXGBE_I2C_T_LOW);
1792 status = IXGBE_ERR_I2C;
1793 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1794 "I2C data was not set to %X\n", data);
1800 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1801 * @hw: pointer to hardware structure
1802 * @i2cctl: Current value of I2CCTL register
1804 * Raises the I2C clock line '0'->'1'
1806 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1809 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1812 DEBUGFUNC("ixgbe_raise_i2c_clk");
1814 for (i = 0; i < timeout; i++) {
1815 *i2cctl |= IXGBE_I2C_CLK_OUT;
1817 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1818 IXGBE_WRITE_FLUSH(hw);
1819 /* SCL rise time (1000ns) */
1820 usec_delay(IXGBE_I2C_T_RISE);
1822 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1823 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1829 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1830 * @hw: pointer to hardware structure
1831 * @i2cctl: Current value of I2CCTL register
1833 * Lowers the I2C clock line '1'->'0'
1835 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1838 DEBUGFUNC("ixgbe_lower_i2c_clk");
1840 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1842 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1843 IXGBE_WRITE_FLUSH(hw);
1845 /* SCL fall time (300ns) */
1846 usec_delay(IXGBE_I2C_T_FALL);
1850 * ixgbe_set_i2c_data - Sets the I2C data bit
1851 * @hw: pointer to hardware structure
1852 * @i2cctl: Current value of I2CCTL register
1853 * @data: I2C data value (0 or 1) to set
1855 * Sets the I2C data bit
1857 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1859 s32 status = IXGBE_SUCCESS;
1861 DEBUGFUNC("ixgbe_set_i2c_data");
1864 *i2cctl |= IXGBE_I2C_DATA_OUT;
1866 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1868 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1869 IXGBE_WRITE_FLUSH(hw);
1871 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1872 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1874 /* Verify data was set correctly */
1875 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1876 if (data != ixgbe_get_i2c_data(i2cctl)) {
1877 status = IXGBE_ERR_I2C;
1878 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1879 "Error - I2C data was not set to %X.\n",
1887 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1888 * @hw: pointer to hardware structure
1889 * @i2cctl: Current value of I2CCTL register
1891 * Returns the I2C data bit value
1893 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1897 DEBUGFUNC("ixgbe_get_i2c_data");
1899 if (*i2cctl & IXGBE_I2C_DATA_IN)
1908 * ixgbe_i2c_bus_clear - Clears the I2C bus
1909 * @hw: pointer to hardware structure
1911 * Clears the I2C bus by sending nine clock pulses.
1912 * Used when data line is stuck low.
1914 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1916 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1919 DEBUGFUNC("ixgbe_i2c_bus_clear");
1921 ixgbe_i2c_start(hw);
1923 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1925 for (i = 0; i < 9; i++) {
1926 ixgbe_raise_i2c_clk(hw, &i2cctl);
1928 /* Min high period of clock is 4us */
1929 usec_delay(IXGBE_I2C_T_HIGH);
1931 ixgbe_lower_i2c_clk(hw, &i2cctl);
1933 /* Min low period of clock is 4.7us*/
1934 usec_delay(IXGBE_I2C_T_LOW);
1937 ixgbe_i2c_start(hw);
1939 /* Put the i2c bus back to default state */
1944 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1945 * @hw: pointer to hardware structure
1947 * Checks if the LASI temp alarm status was triggered due to overtemp
1949 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1951 s32 status = IXGBE_SUCCESS;
1954 DEBUGFUNC("ixgbe_tn_check_overtemp");
1956 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1959 /* Check that the LASI temp alarm status was triggered */
1960 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1961 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1963 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1966 status = IXGBE_ERR_OVERTEMP;
1967 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");