1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2017, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
33 ******************************************************************************/
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
42 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
45 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
50 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
51 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
55 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
56 * @hw: pointer to the hardware structure
59 * Returns an error code on error.
61 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
65 status = ixgbe_clock_out_i2c_byte(hw, byte);
68 return ixgbe_get_i2c_ack(hw);
72 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
73 * @hw: pointer to the hardware structure
74 * @byte: pointer to a u8 to receive the byte
76 * Returns an error code on error.
78 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
82 status = ixgbe_clock_in_i2c_byte(hw, byte);
86 return ixgbe_clock_out_i2c_bit(hw, FALSE);
90 * ixgbe_ones_comp_byte_add - Perform one's complement addition
94 * Returns one's complement 8-bit sum.
96 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
98 u16 sum = add1 + add2;
100 sum = (sum & 0xFF) + (sum >> 8);
105 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
106 * @hw: pointer to the hardware structure
107 * @addr: I2C bus address to read from
108 * @reg: I2C device register to read from
109 * @val: pointer to location to receive read value
110 * @lock: TRUE if to take and release semaphore
112 * Returns an error code on error.
114 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
117 u32 swfw_mask = hw->phy.phy_semaphore_mask;
126 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
127 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
130 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
131 return IXGBE_ERR_SWFW_SYNC;
133 /* Device Address and write indication */
134 if (ixgbe_out_i2c_byte_ack(hw, addr))
136 /* Write bits 14:8 */
137 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
140 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
143 if (ixgbe_out_i2c_byte_ack(hw, csum))
145 /* Re-start condition */
147 /* Device Address and read indication */
148 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
151 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
154 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
157 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
160 if (ixgbe_clock_out_i2c_bit(hw, FALSE))
164 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
165 *val = (high_bits << 8) | low_bits;
169 ixgbe_i2c_bus_clear(hw);
171 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
173 if (retry < max_retry)
174 DEBUGOUT("I2C byte read combined error - Retrying.\n");
176 DEBUGOUT("I2C byte read combined error.\n");
177 } while (retry < max_retry);
179 return IXGBE_ERR_I2C;
183 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
184 * @hw: pointer to the hardware structure
185 * @addr: I2C bus address to write to
186 * @reg: I2C device register to write to
187 * @val: value to write
188 * @lock: TRUE if to take and release semaphore
190 * Returns an error code on error.
192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
195 u32 swfw_mask = hw->phy.phy_semaphore_mask;
201 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
202 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
203 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
204 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
207 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
208 return IXGBE_ERR_SWFW_SYNC;
210 /* Device Address and write indication */
211 if (ixgbe_out_i2c_byte_ack(hw, addr))
213 /* Write bits 14:8 */
214 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
217 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
219 /* Write data 15:8 */
220 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
223 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
226 if (ixgbe_out_i2c_byte_ack(hw, csum))
230 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
234 ixgbe_i2c_bus_clear(hw);
236 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
238 if (retry < max_retry)
239 DEBUGOUT("I2C byte write combined error - Retrying.\n");
241 DEBUGOUT("I2C byte write combined error.\n");
242 } while (retry < max_retry);
244 return IXGBE_ERR_I2C;
248 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
249 * @hw: pointer to the hardware structure
251 * Initialize the function pointers.
253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
255 struct ixgbe_phy_info *phy = &hw->phy;
257 DEBUGFUNC("ixgbe_init_phy_ops_generic");
260 phy->ops.identify = ixgbe_identify_phy_generic;
261 phy->ops.reset = ixgbe_reset_phy_generic;
262 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
263 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
264 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
265 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
266 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
267 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
268 phy->ops.check_link = NULL;
269 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
270 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
271 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
272 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
273 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
274 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
275 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
276 phy->ops.identify_sfp = ixgbe_identify_module_generic;
277 phy->sfp_type = ixgbe_sfp_type_unknown;
278 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
279 phy->ops.write_i2c_byte_unlocked =
280 ixgbe_write_i2c_byte_generic_unlocked;
281 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
282 return IXGBE_SUCCESS;
286 * ixgbe_probe_phy - Probe a single address for a PHY
287 * @hw: pointer to hardware structure
288 * @phy_addr: PHY address to probe
290 * Returns TRUE if PHY found
292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
296 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
297 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
302 if (ixgbe_get_phy_id(hw))
305 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
307 if (hw->phy.type == ixgbe_phy_unknown) {
308 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
309 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
311 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
312 IXGBE_MDIO_PHY_1000BASET_ABILITY))
313 hw->phy.type = ixgbe_phy_cu_unknown;
315 hw->phy.type = ixgbe_phy_generic;
322 * ixgbe_identify_phy_generic - Get physical layer module
323 * @hw: pointer to hardware structure
325 * Determines the physical layer module found on the current adapter.
327 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
329 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
332 DEBUGFUNC("ixgbe_identify_phy_generic");
334 if (!hw->phy.phy_semaphore_mask) {
336 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
338 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
341 if (hw->phy.type != ixgbe_phy_unknown)
342 return IXGBE_SUCCESS;
344 if (hw->phy.nw_mng_if_sel) {
345 phy_addr = (hw->phy.nw_mng_if_sel &
346 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
347 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
348 if (ixgbe_probe_phy(hw, phy_addr))
349 return IXGBE_SUCCESS;
351 return IXGBE_ERR_PHY_ADDR_INVALID;
354 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
355 if (ixgbe_probe_phy(hw, phy_addr)) {
356 status = IXGBE_SUCCESS;
361 /* Certain media types do not have a phy so an address will not
362 * be found and the code will take this path. Caller has to
363 * decide if it is an error or not.
365 if (status != IXGBE_SUCCESS)
372 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
373 * @hw: pointer to the hardware structure
375 * This function checks the MMNGC.MNG_VETO bit to see if there are
376 * any constraints on link from manageability. For MAC's that don't
377 * have this bit just return faluse since the link can not be blocked
380 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
384 DEBUGFUNC("ixgbe_check_reset_blocked");
386 /* If we don't have this bit, it can't be blocking */
387 if (hw->mac.type == ixgbe_mac_82598EB)
390 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
391 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
392 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
393 "MNG_VETO bit detected.\n");
401 * ixgbe_validate_phy_addr - Determines phy address is valid
402 * @hw: pointer to hardware structure
403 * @phy_addr: PHY address
406 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
411 DEBUGFUNC("ixgbe_validate_phy_addr");
413 hw->phy.addr = phy_addr;
414 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
415 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
417 if (phy_id != 0xFFFF && phy_id != 0x0)
420 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
426 * ixgbe_get_phy_id - Get the phy type
427 * @hw: pointer to hardware structure
430 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
436 DEBUGFUNC("ixgbe_get_phy_id");
438 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
439 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
442 if (status == IXGBE_SUCCESS) {
443 hw->phy.id = (u32)(phy_id_high << 16);
444 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
445 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
447 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
448 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
450 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
451 phy_id_high, phy_id_low);
457 * ixgbe_get_phy_type_from_id - Get the phy type
458 * @phy_id: PHY ID information
461 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
463 enum ixgbe_phy_type phy_type;
465 DEBUGFUNC("ixgbe_get_phy_type_from_id");
469 phy_type = ixgbe_phy_tn;
474 phy_type = ixgbe_phy_aq;
477 phy_type = ixgbe_phy_qt;
480 phy_type = ixgbe_phy_nl;
484 phy_type = ixgbe_phy_x550em_ext_t;
486 case IXGBE_M88E1500_E_PHY_ID:
487 case IXGBE_M88E1543_E_PHY_ID:
488 phy_type = ixgbe_phy_ext_1g_t;
491 phy_type = ixgbe_phy_unknown;
498 * ixgbe_reset_phy_generic - Performs a PHY reset
499 * @hw: pointer to hardware structure
501 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
505 s32 status = IXGBE_SUCCESS;
507 DEBUGFUNC("ixgbe_reset_phy_generic");
509 if (hw->phy.type == ixgbe_phy_unknown)
510 status = ixgbe_identify_phy_generic(hw);
512 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
515 /* Don't reset PHY if it's shut down due to overtemp. */
516 if (!hw->phy.reset_if_overtemp &&
517 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
520 /* Blocked by MNG FW so bail */
521 if (ixgbe_check_reset_blocked(hw))
525 * Perform soft PHY reset to the PHY_XS.
526 * This will cause a soft reset to the PHY
528 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
529 IXGBE_MDIO_PHY_XS_DEV_TYPE,
530 IXGBE_MDIO_PHY_XS_RESET);
533 * Poll for reset bit to self-clear indicating reset is complete.
534 * Some PHYs could take up to 3 seconds to complete and need about
535 * 1.7 usec delay after the reset is complete.
537 for (i = 0; i < 30; i++) {
539 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
540 status = hw->phy.ops.read_reg(hw,
541 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
542 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
544 if (status != IXGBE_SUCCESS)
547 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
552 status = hw->phy.ops.read_reg(hw,
553 IXGBE_MDIO_PHY_XS_CONTROL,
554 IXGBE_MDIO_PHY_XS_DEV_TYPE,
556 if (status != IXGBE_SUCCESS)
559 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
566 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
567 status = IXGBE_ERR_RESET_FAILED;
568 ERROR_REPORT1(IXGBE_ERROR_POLLING,
569 "PHY reset polling failed to complete.\n");
577 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
579 * @hw: pointer to hardware structure
580 * @reg_addr: 32 bit address of PHY register to read
581 * @device_type: 5 bit device type
582 * @phy_data: Pointer to read data from PHY register
584 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
587 u32 i, data, command;
589 /* Setup and write the address cycle command */
590 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
591 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
592 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
593 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
595 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
598 * Check every 10 usec to see if the address cycle completed.
599 * The MDI Command bit will clear when the operation is
602 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
605 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
606 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
611 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
612 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
613 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
614 return IXGBE_ERR_PHY;
618 * Address cycle complete, setup and write the read
621 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
622 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
623 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
624 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
626 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
629 * Check every 10 usec to see if the address cycle
630 * completed. The MDI Command bit will clear when the
631 * operation is complete
633 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
636 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
637 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
641 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
642 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
643 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
644 return IXGBE_ERR_PHY;
648 * Read operation is complete. Get the data
651 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
652 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
653 *phy_data = (u16)(data);
655 return IXGBE_SUCCESS;
659 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
660 * using the SWFW lock - this function is needed in most cases
661 * @hw: pointer to hardware structure
662 * @reg_addr: 32 bit address of PHY register to read
663 * @device_type: 5 bit device type
664 * @phy_data: Pointer to read data from PHY register
666 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
667 u32 device_type, u16 *phy_data)
670 u32 gssr = hw->phy.phy_semaphore_mask;
672 DEBUGFUNC("ixgbe_read_phy_reg_generic");
674 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
675 return IXGBE_ERR_SWFW_SYNC;
677 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
679 hw->mac.ops.release_swfw_sync(hw, gssr);
685 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
687 * @hw: pointer to hardware structure
688 * @reg_addr: 32 bit PHY register to write
689 * @device_type: 5 bit device type
690 * @phy_data: Data to write to the PHY register
692 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
693 u32 device_type, u16 phy_data)
697 /* Put the data in the MDI single read and write data register*/
698 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
700 /* Setup and write the address cycle command */
701 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
702 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
703 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
704 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
706 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
709 * Check every 10 usec to see if the address cycle completed.
710 * The MDI Command bit will clear when the operation is
713 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
716 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
717 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
721 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
722 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
723 return IXGBE_ERR_PHY;
727 * Address cycle complete, setup and write the write
730 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
731 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
732 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
733 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
735 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
738 * Check every 10 usec to see if the address cycle
739 * completed. The MDI Command bit will clear when the
740 * operation is complete
742 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
745 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
746 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
750 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
751 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
752 return IXGBE_ERR_PHY;
755 return IXGBE_SUCCESS;
759 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
760 * using SWFW lock- this function is needed in most cases
761 * @hw: pointer to hardware structure
762 * @reg_addr: 32 bit PHY register to write
763 * @device_type: 5 bit device type
764 * @phy_data: Data to write to the PHY register
766 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
767 u32 device_type, u16 phy_data)
770 u32 gssr = hw->phy.phy_semaphore_mask;
772 DEBUGFUNC("ixgbe_write_phy_reg_generic");
774 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
775 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
777 hw->mac.ops.release_swfw_sync(hw, gssr);
779 status = IXGBE_ERR_SWFW_SYNC;
786 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
787 * @hw: pointer to hardware structure
789 * Restart auto-negotiation and PHY and waits for completion.
791 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
793 s32 status = IXGBE_SUCCESS;
794 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
795 bool autoneg = FALSE;
796 ixgbe_link_speed speed;
798 DEBUGFUNC("ixgbe_setup_phy_link_generic");
800 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
802 /* Set or unset auto-negotiation 10G advertisement */
803 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
804 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
807 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
808 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
809 (speed & IXGBE_LINK_SPEED_10GB_FULL))
810 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
812 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
813 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
816 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
817 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
820 if (hw->mac.type == ixgbe_mac_X550) {
821 /* Set or unset auto-negotiation 5G advertisement */
822 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
823 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
824 (speed & IXGBE_LINK_SPEED_5GB_FULL))
825 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
827 /* Set or unset auto-negotiation 2.5G advertisement */
828 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
829 if ((hw->phy.autoneg_advertised &
830 IXGBE_LINK_SPEED_2_5GB_FULL) &&
831 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
832 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
835 /* Set or unset auto-negotiation 1G advertisement */
836 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
837 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
838 (speed & IXGBE_LINK_SPEED_1GB_FULL))
839 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
841 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
842 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
845 /* Set or unset auto-negotiation 100M advertisement */
846 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
847 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
850 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
851 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
852 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
853 (speed & IXGBE_LINK_SPEED_100_FULL))
854 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
856 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
857 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
860 /* Blocked by MNG FW so don't reset PHY */
861 if (ixgbe_check_reset_blocked(hw))
864 /* Restart PHY auto-negotiation. */
865 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
866 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
868 autoneg_reg |= IXGBE_MII_RESTART;
870 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
871 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
877 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
878 * @hw: pointer to hardware structure
879 * @speed: new link speed
880 * @autoneg_wait_to_complete: unused
882 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
883 ixgbe_link_speed speed,
884 bool autoneg_wait_to_complete)
886 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
888 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
891 * Clear autoneg_advertised and set new values based on input link
894 hw->phy.autoneg_advertised = 0;
896 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
897 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
899 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
900 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
902 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
903 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
905 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
906 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
908 if (speed & IXGBE_LINK_SPEED_100_FULL)
909 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
911 if (speed & IXGBE_LINK_SPEED_10_FULL)
912 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
914 /* Setup link based on the new speed settings */
915 ixgbe_setup_phy_link(hw);
917 return IXGBE_SUCCESS;
921 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
922 * @hw: pointer to hardware structure
924 * Determines the supported link capabilities by reading the PHY auto
925 * negotiation register.
927 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
932 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
933 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
938 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
939 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
940 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
941 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
942 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
943 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
945 switch (hw->mac.type) {
947 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
948 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
950 case ixgbe_mac_X550EM_x:
951 case ixgbe_mac_X550EM_a:
952 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
962 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
963 * @hw: pointer to hardware structure
964 * @speed: pointer to link speed
965 * @autoneg: boolean auto-negotiation value
967 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
968 ixgbe_link_speed *speed,
971 s32 status = IXGBE_SUCCESS;
973 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
976 if (!hw->phy.speeds_supported)
977 status = ixgbe_get_copper_speeds_supported(hw);
979 *speed = hw->phy.speeds_supported;
984 * ixgbe_check_phy_link_tnx - Determine link and speed status
985 * @hw: pointer to hardware structure
986 * @speed: current link speed
987 * @link_up: TRUE is link is up, FALSE otherwise
989 * Reads the VS1 register to determine if link is up and the current speed for
992 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
995 s32 status = IXGBE_SUCCESS;
997 u32 max_time_out = 10;
1002 DEBUGFUNC("ixgbe_check_phy_link_tnx");
1004 /* Initialize speed and link to default case */
1006 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1009 * Check current speed and link status of the PHY register.
1010 * This is a vendor specific register and may have to
1011 * be changed for other copper PHYs.
1013 for (time_out = 0; time_out < max_time_out; time_out++) {
1015 status = hw->phy.ops.read_reg(hw,
1016 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1017 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1019 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1020 phy_speed = phy_data &
1021 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1022 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1025 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1026 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1035 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1036 * @hw: pointer to hardware structure
1038 * Restart auto-negotiation and PHY and waits for completion.
1040 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1042 s32 status = IXGBE_SUCCESS;
1043 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1044 bool autoneg = FALSE;
1045 ixgbe_link_speed speed;
1047 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1049 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1051 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1052 /* Set or unset auto-negotiation 10G advertisement */
1053 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1054 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1057 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1058 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1059 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1061 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1062 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1066 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1067 /* Set or unset auto-negotiation 1G advertisement */
1068 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1069 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1072 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1073 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1074 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1076 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1077 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1081 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1082 /* Set or unset auto-negotiation 100M advertisement */
1083 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1084 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1087 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1088 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1089 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1091 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1092 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1096 /* Blocked by MNG FW so don't reset PHY */
1097 if (ixgbe_check_reset_blocked(hw))
1100 /* Restart PHY auto-negotiation. */
1101 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1102 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1104 autoneg_reg |= IXGBE_MII_RESTART;
1106 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1107 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1113 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1114 * @hw: pointer to hardware structure
1115 * @firmware_version: pointer to the PHY Firmware Version
1117 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1118 u16 *firmware_version)
1122 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1124 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1125 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1132 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1133 * @hw: pointer to hardware structure
1134 * @firmware_version: pointer to the PHY Firmware Version
1136 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1137 u16 *firmware_version)
1141 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1143 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1144 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1151 * ixgbe_reset_phy_nl - Performs a PHY reset
1152 * @hw: pointer to hardware structure
1154 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1156 u16 phy_offset, control, eword, edata, block_crc;
1157 bool end_data = FALSE;
1158 u16 list_offset, data_offset;
1160 s32 ret_val = IXGBE_SUCCESS;
1163 DEBUGFUNC("ixgbe_reset_phy_nl");
1165 /* Blocked by MNG FW so bail */
1166 if (ixgbe_check_reset_blocked(hw))
1169 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1170 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1172 /* reset the PHY and poll for completion */
1173 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1174 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1175 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1177 for (i = 0; i < 100; i++) {
1178 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1179 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1180 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1185 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1186 DEBUGOUT("PHY reset did not complete.\n");
1187 ret_val = IXGBE_ERR_PHY;
1191 /* Get init offsets */
1192 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1194 if (ret_val != IXGBE_SUCCESS)
1197 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1201 * Read control word from PHY init contents offset
1203 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1206 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1207 IXGBE_CONTROL_SHIFT_NL;
1208 edata = eword & IXGBE_DATA_MASK_NL;
1210 case IXGBE_DELAY_NL:
1212 DEBUGOUT1("DELAY: %d MS\n", edata);
1216 DEBUGOUT("DATA:\n");
1218 ret_val = hw->eeprom.ops.read(hw, data_offset,
1223 for (i = 0; i < edata; i++) {
1224 ret_val = hw->eeprom.ops.read(hw, data_offset,
1228 hw->phy.ops.write_reg(hw, phy_offset,
1229 IXGBE_TWINAX_DEV, eword);
1230 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1236 case IXGBE_CONTROL_NL:
1238 DEBUGOUT("CONTROL:\n");
1239 if (edata == IXGBE_CONTROL_EOL_NL) {
1242 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1245 DEBUGOUT("Bad control value\n");
1246 ret_val = IXGBE_ERR_PHY;
1251 DEBUGOUT("Bad control type\n");
1252 ret_val = IXGBE_ERR_PHY;
1261 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1262 "eeprom read at offset %d failed", data_offset);
1263 return IXGBE_ERR_PHY;
1267 * ixgbe_identify_module_generic - Identifies module type
1268 * @hw: pointer to hardware structure
1270 * Determines HW type and calls appropriate function.
1272 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1274 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1276 DEBUGFUNC("ixgbe_identify_module_generic");
1278 switch (hw->mac.ops.get_media_type(hw)) {
1279 case ixgbe_media_type_fiber:
1280 status = ixgbe_identify_sfp_module_generic(hw);
1283 case ixgbe_media_type_fiber_qsfp:
1284 status = ixgbe_identify_qsfp_module_generic(hw);
1288 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1289 status = IXGBE_ERR_SFP_NOT_PRESENT;
1297 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1298 * @hw: pointer to hardware structure
1300 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1302 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1304 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1306 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1308 u8 comp_codes_1g = 0;
1309 u8 comp_codes_10g = 0;
1310 u8 oui_bytes[3] = {0, 0, 0};
1313 u16 enforce_sfp = 0;
1315 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1317 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1318 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1319 status = IXGBE_ERR_SFP_NOT_PRESENT;
1323 /* LAN ID is needed for I2C access */
1324 hw->mac.ops.set_lan_id(hw);
1326 status = hw->phy.ops.read_i2c_eeprom(hw,
1327 IXGBE_SFF_IDENTIFIER,
1330 if (status != IXGBE_SUCCESS)
1331 goto err_read_i2c_eeprom;
1333 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1334 hw->phy.type = ixgbe_phy_sfp_unsupported;
1335 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1337 status = hw->phy.ops.read_i2c_eeprom(hw,
1338 IXGBE_SFF_1GBE_COMP_CODES,
1341 if (status != IXGBE_SUCCESS)
1342 goto err_read_i2c_eeprom;
1344 status = hw->phy.ops.read_i2c_eeprom(hw,
1345 IXGBE_SFF_10GBE_COMP_CODES,
1348 if (status != IXGBE_SUCCESS)
1349 goto err_read_i2c_eeprom;
1350 status = hw->phy.ops.read_i2c_eeprom(hw,
1351 IXGBE_SFF_CABLE_TECHNOLOGY,
1354 if (status != IXGBE_SUCCESS)
1355 goto err_read_i2c_eeprom;
1362 * 3 SFP_DA_CORE0 - 82599-specific
1363 * 4 SFP_DA_CORE1 - 82599-specific
1364 * 5 SFP_SR/LR_CORE0 - 82599-specific
1365 * 6 SFP_SR/LR_CORE1 - 82599-specific
1366 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1367 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1368 * 9 SFP_1g_cu_CORE0 - 82599-specific
1369 * 10 SFP_1g_cu_CORE1 - 82599-specific
1370 * 11 SFP_1g_sx_CORE0 - 82599-specific
1371 * 12 SFP_1g_sx_CORE1 - 82599-specific
1373 if (hw->mac.type == ixgbe_mac_82598EB) {
1374 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1375 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1376 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1377 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1378 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1379 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1381 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1383 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1384 if (hw->bus.lan_id == 0)
1386 ixgbe_sfp_type_da_cu_core0;
1389 ixgbe_sfp_type_da_cu_core1;
1390 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1391 hw->phy.ops.read_i2c_eeprom(
1392 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1395 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1396 if (hw->bus.lan_id == 0)
1398 ixgbe_sfp_type_da_act_lmt_core0;
1401 ixgbe_sfp_type_da_act_lmt_core1;
1404 ixgbe_sfp_type_unknown;
1406 } else if (comp_codes_10g &
1407 (IXGBE_SFF_10GBASESR_CAPABLE |
1408 IXGBE_SFF_10GBASELR_CAPABLE)) {
1409 if (hw->bus.lan_id == 0)
1411 ixgbe_sfp_type_srlr_core0;
1414 ixgbe_sfp_type_srlr_core1;
1415 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1416 if (hw->bus.lan_id == 0)
1418 ixgbe_sfp_type_1g_cu_core0;
1421 ixgbe_sfp_type_1g_cu_core1;
1422 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1423 if (hw->bus.lan_id == 0)
1425 ixgbe_sfp_type_1g_sx_core0;
1428 ixgbe_sfp_type_1g_sx_core1;
1429 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1430 if (hw->bus.lan_id == 0)
1432 ixgbe_sfp_type_1g_lx_core0;
1435 ixgbe_sfp_type_1g_lx_core1;
1437 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1441 if (hw->phy.sfp_type != stored_sfp_type)
1442 hw->phy.sfp_setup_needed = TRUE;
1444 /* Determine if the SFP+ PHY is dual speed or not. */
1445 hw->phy.multispeed_fiber = FALSE;
1446 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1447 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1448 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1449 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1450 hw->phy.multispeed_fiber = TRUE;
1452 /* Determine PHY vendor */
1453 if (hw->phy.type != ixgbe_phy_nl) {
1454 hw->phy.id = identifier;
1455 status = hw->phy.ops.read_i2c_eeprom(hw,
1456 IXGBE_SFF_VENDOR_OUI_BYTE0,
1459 if (status != IXGBE_SUCCESS)
1460 goto err_read_i2c_eeprom;
1462 status = hw->phy.ops.read_i2c_eeprom(hw,
1463 IXGBE_SFF_VENDOR_OUI_BYTE1,
1466 if (status != IXGBE_SUCCESS)
1467 goto err_read_i2c_eeprom;
1469 status = hw->phy.ops.read_i2c_eeprom(hw,
1470 IXGBE_SFF_VENDOR_OUI_BYTE2,
1473 if (status != IXGBE_SUCCESS)
1474 goto err_read_i2c_eeprom;
1477 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1478 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1479 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1481 switch (vendor_oui) {
1482 case IXGBE_SFF_VENDOR_OUI_TYCO:
1483 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1485 ixgbe_phy_sfp_passive_tyco;
1487 case IXGBE_SFF_VENDOR_OUI_FTL:
1488 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1489 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1491 hw->phy.type = ixgbe_phy_sfp_ftl;
1493 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1494 hw->phy.type = ixgbe_phy_sfp_avago;
1496 case IXGBE_SFF_VENDOR_OUI_INTEL:
1497 hw->phy.type = ixgbe_phy_sfp_intel;
1500 hw->phy.type = ixgbe_phy_sfp_unknown;
1505 /* Allow any DA cable vendor */
1506 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1507 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1508 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1509 hw->phy.type = ixgbe_phy_sfp_passive_unknown;
1510 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1511 hw->phy.type = ixgbe_phy_sfp_active_unknown;
1512 status = IXGBE_SUCCESS;
1516 /* Verify supported 1G SFP modules */
1517 if (comp_codes_10g == 0 &&
1518 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1519 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1520 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1521 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1522 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1523 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1524 hw->phy.type = ixgbe_phy_sfp_unsupported;
1525 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1529 /* Anything else 82598-based is supported */
1530 if (hw->mac.type == ixgbe_mac_82598EB) {
1531 status = IXGBE_SUCCESS;
1535 ixgbe_get_device_caps(hw, &enforce_sfp);
1536 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1537 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1538 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1539 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1540 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1541 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1542 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1543 /* Make sure we're a supported PHY type */
1544 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1545 status = IXGBE_SUCCESS;
1547 if (hw->allow_unsupported_sfp == TRUE) {
1548 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1549 status = IXGBE_SUCCESS;
1551 DEBUGOUT("SFP+ module not supported\n");
1553 ixgbe_phy_sfp_unsupported;
1554 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1558 status = IXGBE_SUCCESS;
1565 err_read_i2c_eeprom:
1566 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1567 if (hw->phy.type != ixgbe_phy_nl) {
1569 hw->phy.type = ixgbe_phy_unknown;
1571 return IXGBE_ERR_SFP_NOT_PRESENT;
1575 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1576 * @hw: pointer to hardware structure
1578 * Determines physical layer capabilities of the current SFP.
1580 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1582 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1583 u8 comp_codes_10g = 0;
1584 u8 comp_codes_1g = 0;
1586 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1588 hw->phy.ops.identify_sfp(hw);
1589 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1590 return physical_layer;
1592 switch (hw->phy.type) {
1593 case ixgbe_phy_sfp_passive_tyco:
1594 case ixgbe_phy_sfp_passive_unknown:
1595 case ixgbe_phy_qsfp_passive_unknown:
1596 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1598 case ixgbe_phy_sfp_ftl_active:
1599 case ixgbe_phy_sfp_active_unknown:
1600 case ixgbe_phy_qsfp_active_unknown:
1601 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1603 case ixgbe_phy_sfp_avago:
1604 case ixgbe_phy_sfp_ftl:
1605 case ixgbe_phy_sfp_intel:
1606 case ixgbe_phy_sfp_unknown:
1607 hw->phy.ops.read_i2c_eeprom(hw,
1608 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1609 hw->phy.ops.read_i2c_eeprom(hw,
1610 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1611 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1612 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1613 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1614 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1615 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1616 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1617 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1618 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1620 case ixgbe_phy_qsfp_intel:
1621 case ixgbe_phy_qsfp_unknown:
1622 hw->phy.ops.read_i2c_eeprom(hw,
1623 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1624 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1625 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1626 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1627 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1633 return physical_layer;
1637 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1638 * @hw: pointer to hardware structure
1640 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1642 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1644 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1646 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1648 u8 comp_codes_1g = 0;
1649 u8 comp_codes_10g = 0;
1650 u8 oui_bytes[3] = {0, 0, 0};
1651 u16 enforce_sfp = 0;
1653 u8 cable_length = 0;
1655 bool active_cable = FALSE;
1657 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1659 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1660 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1661 status = IXGBE_ERR_SFP_NOT_PRESENT;
1665 /* LAN ID is needed for I2C access */
1666 hw->mac.ops.set_lan_id(hw);
1668 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1671 if (status != IXGBE_SUCCESS)
1672 goto err_read_i2c_eeprom;
1674 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1675 hw->phy.type = ixgbe_phy_sfp_unsupported;
1676 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1680 hw->phy.id = identifier;
1682 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1685 if (status != IXGBE_SUCCESS)
1686 goto err_read_i2c_eeprom;
1688 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1691 if (status != IXGBE_SUCCESS)
1692 goto err_read_i2c_eeprom;
1694 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1695 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1696 if (hw->bus.lan_id == 0)
1697 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1699 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1700 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1701 IXGBE_SFF_10GBASELR_CAPABLE)) {
1702 if (hw->bus.lan_id == 0)
1703 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1705 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1707 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1708 active_cable = TRUE;
1710 if (!active_cable) {
1711 /* check for active DA cables that pre-date
1713 hw->phy.ops.read_i2c_eeprom(hw,
1714 IXGBE_SFF_QSFP_CONNECTOR,
1717 hw->phy.ops.read_i2c_eeprom(hw,
1718 IXGBE_SFF_QSFP_CABLE_LENGTH,
1721 hw->phy.ops.read_i2c_eeprom(hw,
1722 IXGBE_SFF_QSFP_DEVICE_TECH,
1726 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1727 (cable_length > 0) &&
1728 ((device_tech >> 4) ==
1729 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1730 active_cable = TRUE;
1734 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1735 if (hw->bus.lan_id == 0)
1737 ixgbe_sfp_type_da_act_lmt_core0;
1740 ixgbe_sfp_type_da_act_lmt_core1;
1742 /* unsupported module type */
1743 hw->phy.type = ixgbe_phy_sfp_unsupported;
1744 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1749 if (hw->phy.sfp_type != stored_sfp_type)
1750 hw->phy.sfp_setup_needed = TRUE;
1752 /* Determine if the QSFP+ PHY is dual speed or not. */
1753 hw->phy.multispeed_fiber = FALSE;
1754 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1755 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1756 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1757 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1758 hw->phy.multispeed_fiber = TRUE;
1760 /* Determine PHY vendor for optical modules */
1761 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1762 IXGBE_SFF_10GBASELR_CAPABLE)) {
1763 status = hw->phy.ops.read_i2c_eeprom(hw,
1764 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1767 if (status != IXGBE_SUCCESS)
1768 goto err_read_i2c_eeprom;
1770 status = hw->phy.ops.read_i2c_eeprom(hw,
1771 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1774 if (status != IXGBE_SUCCESS)
1775 goto err_read_i2c_eeprom;
1777 status = hw->phy.ops.read_i2c_eeprom(hw,
1778 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1781 if (status != IXGBE_SUCCESS)
1782 goto err_read_i2c_eeprom;
1785 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1786 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1787 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1789 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1790 hw->phy.type = ixgbe_phy_qsfp_intel;
1792 hw->phy.type = ixgbe_phy_qsfp_unknown;
1794 ixgbe_get_device_caps(hw, &enforce_sfp);
1795 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1796 /* Make sure we're a supported PHY type */
1797 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1798 status = IXGBE_SUCCESS;
1800 if (hw->allow_unsupported_sfp == TRUE) {
1801 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1802 status = IXGBE_SUCCESS;
1804 DEBUGOUT("QSFP module not supported\n");
1806 ixgbe_phy_sfp_unsupported;
1807 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1811 status = IXGBE_SUCCESS;
1818 err_read_i2c_eeprom:
1819 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1821 hw->phy.type = ixgbe_phy_unknown;
1823 return IXGBE_ERR_SFP_NOT_PRESENT;
1827 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1828 * @hw: pointer to hardware structure
1829 * @list_offset: offset to the SFP ID list
1830 * @data_offset: offset to the SFP data block
1832 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1833 * so it returns the offsets to the phy init sequence block.
1835 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1840 u16 sfp_type = hw->phy.sfp_type;
1842 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1844 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1845 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1847 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1848 return IXGBE_ERR_SFP_NOT_PRESENT;
1850 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1851 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1852 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1855 * Limiting active cables and 1G Phys must be initialized as
1858 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1859 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1860 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1861 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1862 sfp_type = ixgbe_sfp_type_srlr_core0;
1863 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1864 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1865 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1866 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1867 sfp_type = ixgbe_sfp_type_srlr_core1;
1869 /* Read offset to PHY init contents */
1870 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1871 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1872 "eeprom read at offset %d failed",
1873 IXGBE_PHY_INIT_OFFSET_NL);
1874 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1877 if ((!*list_offset) || (*list_offset == 0xFFFF))
1878 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1880 /* Shift offset to first ID word */
1884 * Find the matching SFP ID in the EEPROM
1885 * and program the init sequence
1887 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1890 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1891 if (sfp_id == sfp_type) {
1893 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1895 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1896 DEBUGOUT("SFP+ module not supported\n");
1897 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1902 (*list_offset) += 2;
1903 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1908 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1909 DEBUGOUT("No matching SFP+ module found\n");
1910 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1913 return IXGBE_SUCCESS;
1916 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1917 "eeprom read at offset %d failed", *list_offset);
1918 return IXGBE_ERR_PHY;
1922 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1923 * @hw: pointer to hardware structure
1924 * @byte_offset: EEPROM byte offset to read
1925 * @eeprom_data: value read
1927 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1929 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1932 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1934 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1935 IXGBE_I2C_EEPROM_DEV_ADDR,
1940 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1941 * @hw: pointer to hardware structure
1942 * @byte_offset: byte offset at address 0xA2
1943 * @sff8472_data: value read
1945 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1947 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1950 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1951 IXGBE_I2C_EEPROM_DEV_ADDR2,
1956 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1957 * @hw: pointer to hardware structure
1958 * @byte_offset: EEPROM byte offset to write
1959 * @eeprom_data: value to write
1961 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1963 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1966 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1968 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1969 IXGBE_I2C_EEPROM_DEV_ADDR,
1974 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected
1975 * @hw: pointer to hardware structure
1976 * @offset: eeprom offset to be read
1977 * @addr: I2C address to be read
1979 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1981 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1982 offset == IXGBE_SFF_IDENTIFIER &&
1983 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1989 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1990 * @hw: pointer to hardware structure
1991 * @byte_offset: byte offset to read
1992 * @dev_addr: address to read from
1994 * @lock: TRUE if to take and release semaphore
1996 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1997 * a specified device address.
1999 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2000 u8 dev_addr, u8 *data, bool lock)
2005 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2009 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2011 if (hw->mac.type >= ixgbe_mac_X550)
2013 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2014 max_retry = IXGBE_SFP_DETECT_RETRIES;
2017 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2018 return IXGBE_ERR_SWFW_SYNC;
2020 ixgbe_i2c_start(hw);
2022 /* Device Address and write indication */
2023 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2024 if (status != IXGBE_SUCCESS)
2027 status = ixgbe_get_i2c_ack(hw);
2028 if (status != IXGBE_SUCCESS)
2031 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2032 if (status != IXGBE_SUCCESS)
2035 status = ixgbe_get_i2c_ack(hw);
2036 if (status != IXGBE_SUCCESS)
2039 ixgbe_i2c_start(hw);
2041 /* Device Address and read indication */
2042 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2043 if (status != IXGBE_SUCCESS)
2046 status = ixgbe_get_i2c_ack(hw);
2047 if (status != IXGBE_SUCCESS)
2050 status = ixgbe_clock_in_i2c_byte(hw, data);
2051 if (status != IXGBE_SUCCESS)
2054 status = ixgbe_clock_out_i2c_bit(hw, nack);
2055 if (status != IXGBE_SUCCESS)
2060 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2061 return IXGBE_SUCCESS;
2064 ixgbe_i2c_bus_clear(hw);
2066 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2070 if (retry < max_retry)
2071 DEBUGOUT("I2C byte read error - Retrying.\n");
2073 DEBUGOUT("I2C byte read error.\n");
2075 } while (retry < max_retry);
2081 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2082 * @hw: pointer to hardware structure
2083 * @byte_offset: byte offset to read
2084 * @dev_addr: address to read from
2087 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2088 * a specified device address.
2090 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2091 u8 dev_addr, u8 *data)
2093 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2098 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2099 * @hw: pointer to hardware structure
2100 * @byte_offset: byte offset to read
2101 * @dev_addr: address to read from
2104 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2105 * a specified device address.
2107 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2108 u8 dev_addr, u8 *data)
2110 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2115 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2116 * @hw: pointer to hardware structure
2117 * @byte_offset: byte offset to write
2118 * @dev_addr: address to write to
2119 * @data: value to write
2120 * @lock: TRUE if to take and release semaphore
2122 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2123 * a specified device address.
2125 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2126 u8 dev_addr, u8 data, bool lock)
2131 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2133 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2135 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2137 return IXGBE_ERR_SWFW_SYNC;
2140 ixgbe_i2c_start(hw);
2142 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2143 if (status != IXGBE_SUCCESS)
2146 status = ixgbe_get_i2c_ack(hw);
2147 if (status != IXGBE_SUCCESS)
2150 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2151 if (status != IXGBE_SUCCESS)
2154 status = ixgbe_get_i2c_ack(hw);
2155 if (status != IXGBE_SUCCESS)
2158 status = ixgbe_clock_out_i2c_byte(hw, data);
2159 if (status != IXGBE_SUCCESS)
2162 status = ixgbe_get_i2c_ack(hw);
2163 if (status != IXGBE_SUCCESS)
2168 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2169 return IXGBE_SUCCESS;
2172 ixgbe_i2c_bus_clear(hw);
2174 if (retry < max_retry)
2175 DEBUGOUT("I2C byte write error - Retrying.\n");
2177 DEBUGOUT("I2C byte write error.\n");
2178 } while (retry < max_retry);
2181 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2187 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2188 * @hw: pointer to hardware structure
2189 * @byte_offset: byte offset to write
2190 * @dev_addr: address to write to
2191 * @data: value to write
2193 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2194 * a specified device address.
2196 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2197 u8 dev_addr, u8 data)
2199 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2204 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2205 * @hw: pointer to hardware structure
2206 * @byte_offset: byte offset to write
2207 * @dev_addr: address to write to
2208 * @data: value to write
2210 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2211 * a specified device address.
2213 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2214 u8 dev_addr, u8 data)
2216 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2221 * ixgbe_i2c_start - Sets I2C start condition
2222 * @hw: pointer to hardware structure
2224 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2225 * Set bit-bang mode on X550 hardware.
2227 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2229 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2231 DEBUGFUNC("ixgbe_i2c_start");
2233 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2235 /* Start condition must begin with data and clock high */
2236 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2237 ixgbe_raise_i2c_clk(hw, &i2cctl);
2239 /* Setup time for start condition (4.7us) */
2240 usec_delay(IXGBE_I2C_T_SU_STA);
2242 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2244 /* Hold time for start condition (4us) */
2245 usec_delay(IXGBE_I2C_T_HD_STA);
2247 ixgbe_lower_i2c_clk(hw, &i2cctl);
2249 /* Minimum low period of clock is 4.7 us */
2250 usec_delay(IXGBE_I2C_T_LOW);
2255 * ixgbe_i2c_stop - Sets I2C stop condition
2256 * @hw: pointer to hardware structure
2258 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2259 * Disables bit-bang mode and negates data output enable on X550
2262 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2264 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2265 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2266 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2267 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2269 DEBUGFUNC("ixgbe_i2c_stop");
2271 /* Stop condition must begin with data low and clock high */
2272 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2273 ixgbe_raise_i2c_clk(hw, &i2cctl);
2275 /* Setup time for stop condition (4us) */
2276 usec_delay(IXGBE_I2C_T_SU_STO);
2278 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2280 /* bus free time between stop and start (4.7us)*/
2281 usec_delay(IXGBE_I2C_T_BUF);
2283 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2284 i2cctl &= ~bb_en_bit;
2285 i2cctl |= data_oe_bit | clk_oe_bit;
2286 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2287 IXGBE_WRITE_FLUSH(hw);
2292 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2293 * @hw: pointer to hardware structure
2294 * @data: data byte to clock in
2296 * Clocks in one byte data via I2C data/clock
2298 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2303 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2306 for (i = 7; i >= 0; i--) {
2307 ixgbe_clock_in_i2c_bit(hw, &bit);
2311 return IXGBE_SUCCESS;
2315 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2316 * @hw: pointer to hardware structure
2317 * @data: data byte clocked out
2319 * Clocks out one byte data via I2C data/clock
2321 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2323 s32 status = IXGBE_SUCCESS;
2328 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2330 for (i = 7; i >= 0; i--) {
2331 bit = (data >> i) & 0x1;
2332 status = ixgbe_clock_out_i2c_bit(hw, bit);
2334 if (status != IXGBE_SUCCESS)
2338 /* Release SDA line (set high) */
2339 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2340 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2341 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2342 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2343 IXGBE_WRITE_FLUSH(hw);
2349 * ixgbe_get_i2c_ack - Polls for I2C ACK
2350 * @hw: pointer to hardware structure
2352 * Clocks in/out one bit via I2C data/clock
2354 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2356 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2357 s32 status = IXGBE_SUCCESS;
2359 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2363 DEBUGFUNC("ixgbe_get_i2c_ack");
2366 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2367 i2cctl |= data_oe_bit;
2368 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2369 IXGBE_WRITE_FLUSH(hw);
2371 ixgbe_raise_i2c_clk(hw, &i2cctl);
2373 /* Minimum high period of clock is 4us */
2374 usec_delay(IXGBE_I2C_T_HIGH);
2376 /* Poll for ACK. Note that ACK in I2C spec is
2377 * transition from 1 to 0 */
2378 for (i = 0; i < timeout; i++) {
2379 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2380 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2388 DEBUGOUT("I2C ack was not received.\n");
2389 status = IXGBE_ERR_I2C;
2392 ixgbe_lower_i2c_clk(hw, &i2cctl);
2394 /* Minimum low period of clock is 4.7 us */
2395 usec_delay(IXGBE_I2C_T_LOW);
2401 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2402 * @hw: pointer to hardware structure
2403 * @data: read data value
2405 * Clocks in one bit via I2C data/clock
2407 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2409 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2410 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2412 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2415 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2416 i2cctl |= data_oe_bit;
2417 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2418 IXGBE_WRITE_FLUSH(hw);
2420 ixgbe_raise_i2c_clk(hw, &i2cctl);
2422 /* Minimum high period of clock is 4us */
2423 usec_delay(IXGBE_I2C_T_HIGH);
2425 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2426 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2428 ixgbe_lower_i2c_clk(hw, &i2cctl);
2430 /* Minimum low period of clock is 4.7 us */
2431 usec_delay(IXGBE_I2C_T_LOW);
2433 return IXGBE_SUCCESS;
2437 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2438 * @hw: pointer to hardware structure
2439 * @data: data value to write
2441 * Clocks out one bit via I2C data/clock
2443 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2446 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2448 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2450 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2451 if (status == IXGBE_SUCCESS) {
2452 ixgbe_raise_i2c_clk(hw, &i2cctl);
2454 /* Minimum high period of clock is 4us */
2455 usec_delay(IXGBE_I2C_T_HIGH);
2457 ixgbe_lower_i2c_clk(hw, &i2cctl);
2459 /* Minimum low period of clock is 4.7 us.
2460 * This also takes care of the data hold time.
2462 usec_delay(IXGBE_I2C_T_LOW);
2464 status = IXGBE_ERR_I2C;
2465 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2466 "I2C data was not set to %X\n", data);
2473 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2474 * @hw: pointer to hardware structure
2475 * @i2cctl: Current value of I2CCTL register
2477 * Raises the I2C clock line '0'->'1'
2478 * Negates the I2C clock output enable on X550 hardware.
2480 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2482 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2484 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2487 DEBUGFUNC("ixgbe_raise_i2c_clk");
2490 *i2cctl |= clk_oe_bit;
2491 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2494 for (i = 0; i < timeout; i++) {
2495 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2497 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2498 IXGBE_WRITE_FLUSH(hw);
2499 /* SCL rise time (1000ns) */
2500 usec_delay(IXGBE_I2C_T_RISE);
2502 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2503 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2509 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2510 * @hw: pointer to hardware structure
2511 * @i2cctl: Current value of I2CCTL register
2513 * Lowers the I2C clock line '1'->'0'
2514 * Asserts the I2C clock output enable on X550 hardware.
2516 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2518 DEBUGFUNC("ixgbe_lower_i2c_clk");
2520 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2521 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2523 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2524 IXGBE_WRITE_FLUSH(hw);
2526 /* SCL fall time (300ns) */
2527 usec_delay(IXGBE_I2C_T_FALL);
2531 * ixgbe_set_i2c_data - Sets the I2C data bit
2532 * @hw: pointer to hardware structure
2533 * @i2cctl: Current value of I2CCTL register
2534 * @data: I2C data value (0 or 1) to set
2536 * Sets the I2C data bit
2537 * Asserts the I2C data output enable on X550 hardware.
2539 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2541 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2542 s32 status = IXGBE_SUCCESS;
2544 DEBUGFUNC("ixgbe_set_i2c_data");
2547 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2549 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2550 *i2cctl &= ~data_oe_bit;
2552 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2553 IXGBE_WRITE_FLUSH(hw);
2555 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2556 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2558 if (!data) /* Can't verify data in this case */
2559 return IXGBE_SUCCESS;
2561 *i2cctl |= data_oe_bit;
2562 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2563 IXGBE_WRITE_FLUSH(hw);
2566 /* Verify data was set correctly */
2567 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2568 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2569 status = IXGBE_ERR_I2C;
2570 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2571 "Error - I2C data was not set to %X.\n",
2579 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2580 * @hw: pointer to hardware structure
2581 * @i2cctl: Current value of I2CCTL register
2583 * Returns the I2C data bit value
2584 * Negates the I2C data output enable on X550 hardware.
2586 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2588 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2590 UNREFERENCED_1PARAMETER(hw);
2592 DEBUGFUNC("ixgbe_get_i2c_data");
2595 *i2cctl |= data_oe_bit;
2596 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2597 IXGBE_WRITE_FLUSH(hw);
2598 usec_delay(IXGBE_I2C_T_FALL);
2601 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2610 * ixgbe_i2c_bus_clear - Clears the I2C bus
2611 * @hw: pointer to hardware structure
2613 * Clears the I2C bus by sending nine clock pulses.
2614 * Used when data line is stuck low.
2616 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2621 DEBUGFUNC("ixgbe_i2c_bus_clear");
2623 ixgbe_i2c_start(hw);
2624 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2626 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2628 for (i = 0; i < 9; i++) {
2629 ixgbe_raise_i2c_clk(hw, &i2cctl);
2631 /* Min high period of clock is 4us */
2632 usec_delay(IXGBE_I2C_T_HIGH);
2634 ixgbe_lower_i2c_clk(hw, &i2cctl);
2636 /* Min low period of clock is 4.7us*/
2637 usec_delay(IXGBE_I2C_T_LOW);
2640 ixgbe_i2c_start(hw);
2642 /* Put the i2c bus back to default state */
2647 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2648 * @hw: pointer to hardware structure
2650 * Checks if the LASI temp alarm status was triggered due to overtemp
2652 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2654 s32 status = IXGBE_SUCCESS;
2657 DEBUGFUNC("ixgbe_tn_check_overtemp");
2659 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2662 /* Check that the LASI temp alarm status was triggered */
2663 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2664 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2666 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2669 status = IXGBE_ERR_OVERTEMP;
2670 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2676 * ixgbe_set_copper_phy_power - Control power for copper phy
2677 * @hw: pointer to hardware structure
2678 * @on: TRUE for on, FALSE for off
2680 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2685 if (!on && ixgbe_mng_present(hw))
2688 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2689 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2695 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2697 if (ixgbe_check_reset_blocked(hw))
2699 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2702 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2703 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,