sys/dev/ixgbe/ixgbe_phy.c

   1 /******************************************************************************
   2   SPDX-License-Identifier: BSD-3-Clause
   3
   4   Copyright (c) 2001-2017, Intel Corporation
   5   All rights reserved.
   6
   7   Redistribution and use in source and binary forms, with or without
   8   modification, are permitted provided that the following conditions are met:
   9
  10    1. Redistributions of source code must retain the above copyright notice,
  11       this list of conditions and the following disclaimer.
  12
  13    2. Redistributions in binary form must reproduce the above copyright
  14       notice, this list of conditions and the following disclaimer in the
  15       documentation and/or other materials provided with the distribution.
  16
  17    3. Neither the name of the Intel Corporation nor the names of its
  18       contributors may be used to endorse or promote products derived from
  19       this software without specific prior written permission.
  20
  21   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31   POSSIBILITY OF SUCH DAMAGE.
  32
  33 ******************************************************************************/
  34 /*$FreeBSD$*/
  35
  36 #include "ixgbe_api.h"
  37 #include "ixgbe_common.h"
  38 #include "ixgbe_phy.h"
  39
  40 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  42 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  45 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  50 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  51 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  52                                           u8 *sff8472_data);
  53
  54 /**
  55  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  56  * @hw: pointer to the hardware structure
  57  * @byte: byte to send
  58  *
  59  * Returns an error code on error.
  60  */
  61 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  62 {
  63         s32 status;
  64
  65         status = ixgbe_clock_out_i2c_byte(hw, byte);
  66         if (status)
  67                 return status;
  68         return ixgbe_get_i2c_ack(hw);
  69 }
  70
  71 /**
  72  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  73  * @hw: pointer to the hardware structure
  74  * @byte: pointer to a u8 to receive the byte
  75  *
  76  * Returns an error code on error.
  77  */
  78 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  79 {
  80         s32 status;
  81
  82         status = ixgbe_clock_in_i2c_byte(hw, byte);
  83         if (status)
  84                 return status;
  85         /* ACK */
  86         return ixgbe_clock_out_i2c_bit(hw, FALSE);
  87 }
  88
  89 /**
  90  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  91  * @add1 - addend 1
  92  * @add2 - addend 2
  93  *
  94  * Returns one's complement 8-bit sum.
  95  */
  96 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  97 {
  98         u16 sum = add1 + add2;
  99
 100         sum = (sum & 0xFF) + (sum >> 8);
 101         return sum & 0xFF;
 102 }
 103
 104 /**
 105  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 106  * @hw: pointer to the hardware structure
 107  * @addr: I2C bus address to read from
 108  * @reg: I2C device register to read from
 109  * @val: pointer to location to receive read value
 110  * @lock: TRUE if to take and release semaphore
 111  *
 112  * Returns an error code on error.
 113  */
 114 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 115                                         u16 *val, bool lock)
 116 {
 117         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 118         int max_retry = 3;
 119         int retry = 0;
 120         u8 csum_byte;
 121         u8 high_bits;
 122         u8 low_bits;
 123         u8 reg_high;
 124         u8 csum;
 125
 126         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 127         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 128         csum = ~csum;
 129         do {
 130                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 131                         return IXGBE_ERR_SWFW_SYNC;
 132                 ixgbe_i2c_start(hw);
 133                 /* Device Address and write indication */
 134                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 135                         goto fail;
 136                 /* Write bits 14:8 */
 137                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 138                         goto fail;
 139                 /* Write bits 7:0 */
 140                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 141                         goto fail;
 142                 /* Write csum */
 143                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 144                         goto fail;
 145                 /* Re-start condition */
 146                 ixgbe_i2c_start(hw);
 147                 /* Device Address and read indication */
 148                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 149                         goto fail;
 150                 /* Get upper bits */
 151                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 152                         goto fail;
 153                 /* Get low bits */
 154                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 155                         goto fail;
 156                 /* Get csum */
 157                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 158                         goto fail;
 159                 /* NACK */
 160                 if (ixgbe_clock_out_i2c_bit(hw, FALSE))
 161                         goto fail;
 162                 ixgbe_i2c_stop(hw);
 163                 if (lock)
 164                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 165                 *val = (high_bits << 8) | low_bits;
 166                 return 0;
 167
 168 fail:
 169                 ixgbe_i2c_bus_clear(hw);
 170                 if (lock)
 171                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 172                 retry++;
 173                 if (retry < max_retry)
 174                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 175                 else
 176                         DEBUGOUT("I2C byte read combined error.\n");
 177         } while (retry < max_retry);
 178
 179         return IXGBE_ERR_I2C;
 180 }
 181
 182 /**
 183  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 184  * @hw: pointer to the hardware structure
 185  * @addr: I2C bus address to write to
 186  * @reg: I2C device register to write to
 187  * @val: value to write
 188  * @lock: TRUE if to take and release semaphore
 189  *
 190  * Returns an error code on error.
 191  */
 192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 193                                          u16 val, bool lock)
 194 {
 195         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 196         int max_retry = 1;
 197         int retry = 0;
 198         u8 reg_high;
 199         u8 csum;
 200
 201         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 202         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 203         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 204         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 205         csum = ~csum;
 206         do {
 207                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 208                         return IXGBE_ERR_SWFW_SYNC;
 209                 ixgbe_i2c_start(hw);
 210                 /* Device Address and write indication */
 211                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 212                         goto fail;
 213                 /* Write bits 14:8 */
 214                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 215                         goto fail;
 216                 /* Write bits 7:0 */
 217                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 218                         goto fail;
 219                 /* Write data 15:8 */
 220                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 221                         goto fail;
 222                 /* Write data 7:0 */
 223                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 224                         goto fail;
 225                 /* Write csum */
 226                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 227                         goto fail;
 228                 ixgbe_i2c_stop(hw);
 229                 if (lock)
 230                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 231                 return 0;
 232
 233 fail:
 234                 ixgbe_i2c_bus_clear(hw);
 235                 if (lock)
 236                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 237                 retry++;
 238                 if (retry < max_retry)
 239                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 240                 else
 241                         DEBUGOUT("I2C byte write combined error.\n");
 242         } while (retry < max_retry);
 243
 244         return IXGBE_ERR_I2C;
 245 }
 246
 247 /**
 248  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 249  *  @hw: pointer to the hardware structure
 250  *
 251  *  Initialize the function pointers.
 252  **/
 253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 254 {
 255         struct ixgbe_phy_info *phy = &hw->phy;
 256
 257         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 258
 259         /* PHY */
 260         phy->ops.identify = ixgbe_identify_phy_generic;
 261         phy->ops.reset = ixgbe_reset_phy_generic;
 262         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 263         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 264         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 265         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 266         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 267         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 268         phy->ops.check_link = NULL;
 269         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 270         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 271         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 272         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 273         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 274         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 275         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 276         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 277         phy->sfp_type = ixgbe_sfp_type_unknown;
 278         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 279         phy->ops.write_i2c_byte_unlocked =
 280                                 ixgbe_write_i2c_byte_generic_unlocked;
 281         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 282         return IXGBE_SUCCESS;
 283 }
 284
 285 /**
 286  * ixgbe_probe_phy - Probe a single address for a PHY
 287  * @hw: pointer to hardware structure
 288  * @phy_addr: PHY address to probe
 289  *
 290  * Returns TRUE if PHY found
 291  */
 292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 293 {
 294         u16 ext_ability = 0;
 295
 296         if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
 297                 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
 298                         phy_addr);
 299                 return FALSE;
 300         }
 301
 302         if (ixgbe_get_phy_id(hw))
 303                 return FALSE;
 304
 305         hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 306
 307         if (hw->phy.type == ixgbe_phy_unknown) {
 308                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 309                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 310                 if (ext_ability &
 311                     (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 312                      IXGBE_MDIO_PHY_1000BASET_ABILITY))
 313                         hw->phy.type = ixgbe_phy_cu_unknown;
 314                 else
 315                         hw->phy.type = ixgbe_phy_generic;
 316         }
 317
 318         return TRUE;
 319 }
 320
 321 /**
 322  *  ixgbe_identify_phy_generic - Get physical layer module
 323  *  @hw: pointer to hardware structure
 324  *
 325  *  Determines the physical layer module found on the current adapter.
 326  **/
 327 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 328 {
 329         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 330         u16 phy_addr;
 331
 332         DEBUGFUNC("ixgbe_identify_phy_generic");
 333
 334         if (!hw->phy.phy_semaphore_mask) {
 335                 if (hw->bus.lan_id)
 336                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 337                 else
 338                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 339         }
 340
 341         if (hw->phy.type != ixgbe_phy_unknown)
 342                 return IXGBE_SUCCESS;
 343
 344         if (hw->phy.nw_mng_if_sel) {
 345                 phy_addr = (hw->phy.nw_mng_if_sel &
 346                             IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 347                            IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 348                 if (ixgbe_probe_phy(hw, phy_addr))
 349                         return IXGBE_SUCCESS;
 350                 else
 351                         return IXGBE_ERR_PHY_ADDR_INVALID;
 352         }
 353
 354         for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 355                 if (ixgbe_probe_phy(hw, phy_addr)) {
 356                         status = IXGBE_SUCCESS;
 357                         break;
 358                 }
 359         }
 360
 361         /* Certain media types do not have a phy so an address will not
 362          * be found and the code will take this path.  Caller has to
 363          * decide if it is an error or not.
 364          */
 365         if (status != IXGBE_SUCCESS)
 366                 hw->phy.addr = 0;
 367
 368         return status;
 369 }
 370
 371 /**
 372  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 373  * @hw: pointer to the hardware structure
 374  *
 375  * This function checks the MMNGC.MNG_VETO bit to see if there are
 376  * any constraints on link from manageability.  For MAC's that don't
 377  * have this bit just return faluse since the link can not be blocked
 378  * via this method.
 379  **/
 380 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 381 {
 382         u32 mmngc;
 383
 384         DEBUGFUNC("ixgbe_check_reset_blocked");
 385
 386         /* If we don't have this bit, it can't be blocking */
 387         if (hw->mac.type == ixgbe_mac_82598EB)
 388                 return FALSE;
 389
 390         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 391         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 392                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 393                               "MNG_VETO bit detected.\n");
 394                 return TRUE;
 395         }
 396
 397         return FALSE;
 398 }
 399
 400 /**
 401  *  ixgbe_validate_phy_addr - Determines phy address is valid
 402  *  @hw: pointer to hardware structure
 403  *
 404  **/
 405 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 406 {
 407         u16 phy_id = 0;
 408         bool valid = FALSE;
 409
 410         DEBUGFUNC("ixgbe_validate_phy_addr");
 411
 412         hw->phy.addr = phy_addr;
 413         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 414                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 415
 416         if (phy_id != 0xFFFF && phy_id != 0x0)
 417                 valid = TRUE;
 418
 419         DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
 420
 421         return valid;
 422 }
 423
 424 /**
 425  *  ixgbe_get_phy_id - Get the phy type
 426  *  @hw: pointer to hardware structure
 427  *
 428  **/
 429 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 430 {
 431         u32 status;
 432         u16 phy_id_high = 0;
 433         u16 phy_id_low = 0;
 434
 435         DEBUGFUNC("ixgbe_get_phy_id");
 436
 437         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 438                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 439                                       &phy_id_high);
 440
 441         if (status == IXGBE_SUCCESS) {
 442                 hw->phy.id = (u32)(phy_id_high << 16);
 443                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 444                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 445                                               &phy_id_low);
 446                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 447                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 448         }
 449         DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
 450                   phy_id_high, phy_id_low);
 451
 452         return status;
 453 }
 454
 455 /**
 456  *  ixgbe_get_phy_type_from_id - Get the phy type
 457  *  @phy_id: PHY ID information
 458  *
 459  **/
 460 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 461 {
 462         enum ixgbe_phy_type phy_type;
 463
 464         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 465
 466         switch (phy_id) {
 467         case TN1010_PHY_ID:
 468                 phy_type = ixgbe_phy_tn;
 469                 break;
 470         case X550_PHY_ID2:
 471         case X550_PHY_ID3:
 472         case X540_PHY_ID:
 473                 phy_type = ixgbe_phy_aq;
 474                 break;
 475         case QT2022_PHY_ID:
 476                 phy_type = ixgbe_phy_qt;
 477                 break;
 478         case ATH_PHY_ID:
 479                 phy_type = ixgbe_phy_nl;
 480                 break;
 481         case X557_PHY_ID:
 482         case X557_PHY_ID2:
 483                 phy_type = ixgbe_phy_x550em_ext_t;
 484                 break;
 485         case IXGBE_M88E1500_E_PHY_ID:
 486         case IXGBE_M88E1543_E_PHY_ID:
 487                 phy_type = ixgbe_phy_ext_1g_t;
 488                 break;
 489         default:
 490                 phy_type = ixgbe_phy_unknown;
 491                 break;
 492         }
 493         return phy_type;
 494 }
 495
 496 /**
 497  *  ixgbe_reset_phy_generic - Performs a PHY reset
 498  *  @hw: pointer to hardware structure
 499  **/
 500 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 501 {
 502         u32 i;
 503         u16 ctrl = 0;
 504         s32 status = IXGBE_SUCCESS;
 505
 506         DEBUGFUNC("ixgbe_reset_phy_generic");
 507
 508         if (hw->phy.type == ixgbe_phy_unknown)
 509                 status = ixgbe_identify_phy_generic(hw);
 510
 511         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 512                 goto out;
 513
 514         /* Don't reset PHY if it's shut down due to overtemp. */
 515         if (!hw->phy.reset_if_overtemp &&
 516             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 517                 goto out;
 518
 519         /* Blocked by MNG FW so bail */
 520         if (ixgbe_check_reset_blocked(hw))
 521                 goto out;
 522
 523         /*
 524          * Perform soft PHY reset to the PHY_XS.
 525          * This will cause a soft reset to the PHY
 526          */
 527         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 528                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 529                               IXGBE_MDIO_PHY_XS_RESET);
 530
 531         /*
 532          * Poll for reset bit to self-clear indicating reset is complete.
 533          * Some PHYs could take up to 3 seconds to complete and need about
 534          * 1.7 usec delay after the reset is complete.
 535          */
 536         for (i = 0; i < 30; i++) {
 537                 msec_delay(100);
 538                 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
 539                         status = hw->phy.ops.read_reg(hw,
 540                                                   IXGBE_MDIO_TX_VENDOR_ALARMS_3,
 541                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 542                                                   &ctrl);
 543                         if (status != IXGBE_SUCCESS)
 544                                 return status;
 545
 546                         if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
 547                                 usec_delay(2);
 548                                 break;
 549                         }
 550                 } else {
 551                         status = hw->phy.ops.read_reg(hw,
 552                                                      IXGBE_MDIO_PHY_XS_CONTROL,
 553                                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
 554                                                      &ctrl);
 555                         if (status != IXGBE_SUCCESS)
 556                                 return status;
 557
 558                         if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 559                                 usec_delay(2);
 560                                 break;
 561                         }
 562                 }
 563         }
 564
 565         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 566                 status = IXGBE_ERR_RESET_FAILED;
 567                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 568                              "PHY reset polling failed to complete.\n");
 569         }
 570
 571 out:
 572         return status;
 573 }
 574
 575 /**
 576  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 577  *  the SWFW lock
 578  *  @hw: pointer to hardware structure
 579  *  @reg_addr: 32 bit address of PHY register to read
 580  *  @phy_data: Pointer to read data from PHY register
 581  **/
 582 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 583                            u16 *phy_data)
 584 {
 585         u32 i, data, command;
 586
 587         /* Setup and write the address cycle command */
 588         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 589                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 590                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 591                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 592
 593         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 594
 595         /*
 596          * Check every 10 usec to see if the address cycle completed.
 597          * The MDI Command bit will clear when the operation is
 598          * complete
 599          */
 600         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 601                 usec_delay(10);
 602
 603                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 604                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 605                         break;
 606         }
 607
 608
 609         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 610                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 611                 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
 612                 return IXGBE_ERR_PHY;
 613         }
 614
 615         /*
 616          * Address cycle complete, setup and write the read
 617          * command
 618          */
 619         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 620                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 621                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 622                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 623
 624         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 625
 626         /*
 627          * Check every 10 usec to see if the address cycle
 628          * completed. The MDI Command bit will clear when the
 629          * operation is complete
 630          */
 631         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 632                 usec_delay(10);
 633
 634                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 635                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 636                         break;
 637         }
 638
 639         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 640                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 641                 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
 642                 return IXGBE_ERR_PHY;
 643         }
 644
 645         /*
 646          * Read operation is complete.  Get the data
 647          * from MSRWD
 648          */
 649         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 650         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 651         *phy_data = (u16)(data);
 652
 653         return IXGBE_SUCCESS;
 654 }
 655
 656 /**
 657  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 658  *  using the SWFW lock - this function is needed in most cases
 659  *  @hw: pointer to hardware structure
 660  *  @reg_addr: 32 bit address of PHY register to read
 661  *  @phy_data: Pointer to read data from PHY register
 662  **/
 663 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 664                                u32 device_type, u16 *phy_data)
 665 {
 666         s32 status;
 667         u32 gssr = hw->phy.phy_semaphore_mask;
 668
 669         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 670
 671         if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 672                 return IXGBE_ERR_SWFW_SYNC;
 673
 674         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
 675
 676         hw->mac.ops.release_swfw_sync(hw, gssr);
 677
 678         return status;
 679 }
 680
 681 /**
 682  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 683  *  without SWFW lock
 684  *  @hw: pointer to hardware structure
 685  *  @reg_addr: 32 bit PHY register to write
 686  *  @device_type: 5 bit device type
 687  *  @phy_data: Data to write to the PHY register
 688  **/
 689 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 690                                 u32 device_type, u16 phy_data)
 691 {
 692         u32 i, command;
 693
 694         /* Put the data in the MDI single read and write data register*/
 695         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 696
 697         /* Setup and write the address cycle command */
 698         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 699                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 700                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 701                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 702
 703         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 704
 705         /*
 706          * Check every 10 usec to see if the address cycle completed.
 707          * The MDI Command bit will clear when the operation is
 708          * complete
 709          */
 710         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 711                 usec_delay(10);
 712
 713                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 714                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 715                         break;
 716         }
 717
 718         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 719                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 720                 return IXGBE_ERR_PHY;
 721         }
 722
 723         /*
 724          * Address cycle complete, setup and write the write
 725          * command
 726          */
 727         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 728                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 729                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 730                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 731
 732         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 733
 734         /*
 735          * Check every 10 usec to see if the address cycle
 736          * completed. The MDI Command bit will clear when the
 737          * operation is complete
 738          */
 739         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 740                 usec_delay(10);
 741
 742                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 743                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 744                         break;
 745         }
 746
 747         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 748                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 749                 return IXGBE_ERR_PHY;
 750         }
 751
 752         return IXGBE_SUCCESS;
 753 }
 754
 755 /**
 756  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 757  *  using SWFW lock- this function is needed in most cases
 758  *  @hw: pointer to hardware structure
 759  *  @reg_addr: 32 bit PHY register to write
 760  *  @device_type: 5 bit device type
 761  *  @phy_data: Data to write to the PHY register
 762  **/
 763 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 764                                 u32 device_type, u16 phy_data)
 765 {
 766         s32 status;
 767         u32 gssr = hw->phy.phy_semaphore_mask;
 768
 769         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 770
 771         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 772                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
 773                                                  phy_data);
 774                 hw->mac.ops.release_swfw_sync(hw, gssr);
 775         } else {
 776                 status = IXGBE_ERR_SWFW_SYNC;
 777         }
 778
 779         return status;
 780 }
 781
 782 /**
 783  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 784  *  @hw: pointer to hardware structure
 785  *
 786  *  Restart auto-negotiation and PHY and waits for completion.
 787  **/
 788 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 789 {
 790         s32 status = IXGBE_SUCCESS;
 791         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 792         bool autoneg = FALSE;
 793         ixgbe_link_speed speed;
 794
 795         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 796
 797         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 798
 799         /* Set or unset auto-negotiation 10G advertisement */
 800         hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 801                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 802                              &autoneg_reg);
 803
 804         autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 805         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
 806             (speed & IXGBE_LINK_SPEED_10GB_FULL))
 807                 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 808
 809         hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 810                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 811                               autoneg_reg);
 812
 813         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 814                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 815                              &autoneg_reg);
 816
 817         if (hw->mac.type == ixgbe_mac_X550) {
 818                 /* Set or unset auto-negotiation 5G advertisement */
 819                 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 820                 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
 821                     (speed & IXGBE_LINK_SPEED_5GB_FULL))
 822                         autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 823
 824                 /* Set or unset auto-negotiation 2.5G advertisement */
 825                 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 826                 if ((hw->phy.autoneg_advertised &
 827                      IXGBE_LINK_SPEED_2_5GB_FULL) &&
 828                     (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
 829                         autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 830         }
 831
 832         /* Set or unset auto-negotiation 1G advertisement */
 833         autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 834         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
 835             (speed & IXGBE_LINK_SPEED_1GB_FULL))
 836                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 837
 838         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 839                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 840                               autoneg_reg);
 841
 842         /* Set or unset auto-negotiation 100M advertisement */
 843         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 844                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 845                              &autoneg_reg);
 846
 847         autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 848                          IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 849         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
 850             (speed & IXGBE_LINK_SPEED_100_FULL))
 851                 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 852
 853         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 854                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 855                               autoneg_reg);
 856
 857         /* Blocked by MNG FW so don't reset PHY */
 858         if (ixgbe_check_reset_blocked(hw))
 859                 return status;
 860
 861         /* Restart PHY auto-negotiation. */
 862         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 863                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 864
 865         autoneg_reg |= IXGBE_MII_RESTART;
 866
 867         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 868                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 869
 870         return status;
 871 }
 872
 873 /**
 874  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 875  *  @hw: pointer to hardware structure
 876  *  @speed: new link speed
 877  **/
 878 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 879                                        ixgbe_link_speed speed,
 880                                        bool autoneg_wait_to_complete)
 881 {
 882         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 883
 884         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 885
 886         /*
 887          * Clear autoneg_advertised and set new values based on input link
 888          * speed.
 889          */
 890         hw->phy.autoneg_advertised = 0;
 891
 892         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 893                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 894
 895         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 896                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 897
 898         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 899                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 900
 901         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 902                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 903
 904         if (speed & IXGBE_LINK_SPEED_100_FULL)
 905                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 906
 907         if (speed & IXGBE_LINK_SPEED_10_FULL)
 908                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
 909
 910         /* Setup link based on the new speed settings */
 911         ixgbe_setup_phy_link(hw);
 912
 913         return IXGBE_SUCCESS;
 914 }
 915
 916 /**
 917  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 918  * @hw: pointer to hardware structure
 919  *
 920  * Determines the supported link capabilities by reading the PHY auto
 921  * negotiation register.
 922  **/
 923 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 924 {
 925         s32 status;
 926         u16 speed_ability;
 927
 928         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 929                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 930                                       &speed_ability);
 931         if (status)
 932                 return status;
 933
 934         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 935                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 936         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 937                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 938         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 939                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 940
 941         switch (hw->mac.type) {
 942         case ixgbe_mac_X550:
 943                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 944                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 945                 break;
 946         case ixgbe_mac_X550EM_x:
 947         case ixgbe_mac_X550EM_a:
 948                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 949                 break;
 950         default:
 951                 break;
 952         }
 953
 954         return status;
 955 }
 956
 957 /**
 958  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 959  *  @hw: pointer to hardware structure
 960  *  @speed: pointer to link speed
 961  *  @autoneg: boolean auto-negotiation value
 962  **/
 963 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 964                                                ixgbe_link_speed *speed,
 965                                                bool *autoneg)
 966 {
 967         s32 status = IXGBE_SUCCESS;
 968
 969         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 970
 971         *autoneg = TRUE;
 972         if (!hw->phy.speeds_supported)
 973                 status = ixgbe_get_copper_speeds_supported(hw);
 974
 975         *speed = hw->phy.speeds_supported;
 976         return status;
 977 }
 978
 979 /**
 980  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 981  *  @hw: pointer to hardware structure
 982  *
 983  *  Reads the VS1 register to determine if link is up and the current speed for
 984  *  the PHY.
 985  **/
 986 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 987                              bool *link_up)
 988 {
 989         s32 status = IXGBE_SUCCESS;
 990         u32 time_out;
 991         u32 max_time_out = 10;
 992         u16 phy_link = 0;
 993         u16 phy_speed = 0;
 994         u16 phy_data = 0;
 995
 996         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 997
 998         /* Initialize speed and link to default case */
 999         *link_up = FALSE;
1000         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1001
1002         /*
1003          * Check current speed and link status of the PHY register.
1004          * This is a vendor specific register and may have to
1005          * be changed for other copper PHYs.
1006          */
1007         for (time_out = 0; time_out < max_time_out; time_out++) {
1008                 usec_delay(10);
1009                 status = hw->phy.ops.read_reg(hw,
1010                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1011                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1012                                         &phy_data);
1013                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1014                 phy_speed = phy_data &
1015                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1016                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1017                         *link_up = TRUE;
1018                         if (phy_speed ==
1019                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1020                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1021                         break;
1022                 }
1023         }
1024
1025         return status;
1026 }
1027
1028 /**
1029  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1030  *      @hw: pointer to hardware structure
1031  *
1032  *      Restart auto-negotiation and PHY and waits for completion.
1033  **/
1034 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1035 {
1036         s32 status = IXGBE_SUCCESS;
1037         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1038         bool autoneg = FALSE;
1039         ixgbe_link_speed speed;
1040
1041         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1042
1043         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1044
1045         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1046                 /* Set or unset auto-negotiation 10G advertisement */
1047                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1048                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1049                                      &autoneg_reg);
1050
1051                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1052                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1053                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1054
1055                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1056                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1057                                       autoneg_reg);
1058         }
1059
1060         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1061                 /* Set or unset auto-negotiation 1G advertisement */
1062                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1063                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1064                                      &autoneg_reg);
1065
1066                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1067                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1068                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1069
1070                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1071                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1072                                       autoneg_reg);
1073         }
1074
1075         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1076                 /* Set or unset auto-negotiation 100M advertisement */
1077                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1078                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1079                                      &autoneg_reg);
1080
1081                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1082                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1083                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1084
1085                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1086                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1087                                       autoneg_reg);
1088         }
1089
1090         /* Blocked by MNG FW so don't reset PHY */
1091         if (ixgbe_check_reset_blocked(hw))
1092                 return status;
1093
1094         /* Restart PHY auto-negotiation. */
1095         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1096                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1097
1098         autoneg_reg |= IXGBE_MII_RESTART;
1099
1100         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1101                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1102
1103         return status;
1104 }
1105
1106 /**
1107  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1108  *  @hw: pointer to hardware structure
1109  *  @firmware_version: pointer to the PHY Firmware Version
1110  **/
1111 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1112                                        u16 *firmware_version)
1113 {
1114         s32 status;
1115
1116         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1117
1118         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1119                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1120                                       firmware_version);
1121
1122         return status;
1123 }
1124
1125 /**
1126  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1127  *  @hw: pointer to hardware structure
1128  *  @firmware_version: pointer to the PHY Firmware Version
1129  **/
1130 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1131                                            u16 *firmware_version)
1132 {
1133         s32 status;
1134
1135         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1136
1137         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1138                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1139                                       firmware_version);
1140
1141         return status;
1142 }
1143
1144 /**
1145  *  ixgbe_reset_phy_nl - Performs a PHY reset
1146  *  @hw: pointer to hardware structure
1147  **/
1148 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1149 {
1150         u16 phy_offset, control, eword, edata, block_crc;
1151         bool end_data = FALSE;
1152         u16 list_offset, data_offset;
1153         u16 phy_data = 0;
1154         s32 ret_val = IXGBE_SUCCESS;
1155         u32 i;
1156
1157         DEBUGFUNC("ixgbe_reset_phy_nl");
1158
1159         /* Blocked by MNG FW so bail */
1160         if (ixgbe_check_reset_blocked(hw))
1161                 goto out;
1162
1163         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1164                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1165
1166         /* reset the PHY and poll for completion */
1167         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1168                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1169                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1170
1171         for (i = 0; i < 100; i++) {
1172                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1173                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1174                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1175                         break;
1176                 msec_delay(10);
1177         }
1178
1179         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1180                 DEBUGOUT("PHY reset did not complete.\n");
1181                 ret_val = IXGBE_ERR_PHY;
1182                 goto out;
1183         }
1184
1185         /* Get init offsets */
1186         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1187                                                       &data_offset);
1188         if (ret_val != IXGBE_SUCCESS)
1189                 goto out;
1190
1191         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1192         data_offset++;
1193         while (!end_data) {
1194                 /*
1195                  * Read control word from PHY init contents offset
1196                  */
1197                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1198                 if (ret_val)
1199                         goto err_eeprom;
1200                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1201                            IXGBE_CONTROL_SHIFT_NL;
1202                 edata = eword & IXGBE_DATA_MASK_NL;
1203                 switch (control) {
1204                 case IXGBE_DELAY_NL:
1205                         data_offset++;
1206                         DEBUGOUT1("DELAY: %d MS\n", edata);
1207                         msec_delay(edata);
1208                         break;
1209                 case IXGBE_DATA_NL:
1210                         DEBUGOUT("DATA:\n");
1211                         data_offset++;
1212                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1213                                                       &phy_offset);
1214                         if (ret_val)
1215                                 goto err_eeprom;
1216                         data_offset++;
1217                         for (i = 0; i < edata; i++) {
1218                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1219                                                               &eword);
1220                                 if (ret_val)
1221                                         goto err_eeprom;
1222                                 hw->phy.ops.write_reg(hw, phy_offset,
1223                                                       IXGBE_TWINAX_DEV, eword);
1224                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1225                                           phy_offset);
1226                                 data_offset++;
1227                                 phy_offset++;
1228                         }
1229                         break;
1230                 case IXGBE_CONTROL_NL:
1231                         data_offset++;
1232                         DEBUGOUT("CONTROL:\n");
1233                         if (edata == IXGBE_CONTROL_EOL_NL) {
1234                                 DEBUGOUT("EOL\n");
1235                                 end_data = TRUE;
1236                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1237                                 DEBUGOUT("SOL\n");
1238                         } else {
1239                                 DEBUGOUT("Bad control value\n");
1240                                 ret_val = IXGBE_ERR_PHY;
1241                                 goto out;
1242                         }
1243                         break;
1244                 default:
1245                         DEBUGOUT("Bad control type\n");
1246                         ret_val = IXGBE_ERR_PHY;
1247                         goto out;
1248                 }
1249         }
1250
1251 out:
1252         return ret_val;
1253
1254 err_eeprom:
1255         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1256                       "eeprom read at offset %d failed", data_offset);
1257         return IXGBE_ERR_PHY;
1258 }
1259
1260 /**
1261  *  ixgbe_identify_module_generic - Identifies module type
1262  *  @hw: pointer to hardware structure
1263  *
1264  *  Determines HW type and calls appropriate function.
1265  **/
1266 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1267 {
1268         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1269
1270         DEBUGFUNC("ixgbe_identify_module_generic");
1271
1272         switch (hw->mac.ops.get_media_type(hw)) {
1273         case ixgbe_media_type_fiber:
1274                 status = ixgbe_identify_sfp_module_generic(hw);
1275                 break;
1276
1277         case ixgbe_media_type_fiber_qsfp:
1278                 status = ixgbe_identify_qsfp_module_generic(hw);
1279                 break;
1280
1281         default:
1282                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1283                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1284                 break;
1285         }
1286
1287         return status;
1288 }
1289
1290 /**
1291  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1292  *  @hw: pointer to hardware structure
1293  *
1294  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1295  **/
1296 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1297 {
1298         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1299         u32 vendor_oui = 0;
1300         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1301         u8 identifier = 0;
1302         u8 comp_codes_1g = 0;
1303         u8 comp_codes_10g = 0;
1304         u8 oui_bytes[3] = {0, 0, 0};
1305         u8 cable_tech = 0;
1306         u8 cable_spec = 0;
1307         u16 enforce_sfp = 0;
1308
1309         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1310
1311         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1312                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1313                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1314                 goto out;
1315         }
1316
1317         /* LAN ID is needed for I2C access */
1318         hw->mac.ops.set_lan_id(hw);
1319
1320         status = hw->phy.ops.read_i2c_eeprom(hw,
1321                                              IXGBE_SFF_IDENTIFIER,
1322                                              &identifier);
1323
1324         if (status != IXGBE_SUCCESS)
1325                 goto err_read_i2c_eeprom;
1326
1327         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1328                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1329                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1330         } else {
1331                 status = hw->phy.ops.read_i2c_eeprom(hw,
1332                                                      IXGBE_SFF_1GBE_COMP_CODES,
1333                                                      &comp_codes_1g);
1334
1335                 if (status != IXGBE_SUCCESS)
1336                         goto err_read_i2c_eeprom;
1337
1338                 status = hw->phy.ops.read_i2c_eeprom(hw,
1339                                                      IXGBE_SFF_10GBE_COMP_CODES,
1340                                                      &comp_codes_10g);
1341
1342                 if (status != IXGBE_SUCCESS)
1343                         goto err_read_i2c_eeprom;
1344                 status = hw->phy.ops.read_i2c_eeprom(hw,
1345                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1346                                                      &cable_tech);
1347
1348                 if (status != IXGBE_SUCCESS)
1349                         goto err_read_i2c_eeprom;
1350
1351                  /* ID Module
1352                   * =========
1353                   * 0   SFP_DA_CU
1354                   * 1   SFP_SR
1355                   * 2   SFP_LR
1356                   * 3   SFP_DA_CORE0 - 82599-specific
1357                   * 4   SFP_DA_CORE1 - 82599-specific
1358                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1359                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1360                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1361                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1362                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1363                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1364                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1365                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1366                   */
1367                 if (hw->mac.type == ixgbe_mac_82598EB) {
1368                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1369                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1370                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1371                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1372                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1373                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1374                         else
1375                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1376                 } else {
1377                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1378                                 if (hw->bus.lan_id == 0)
1379                                         hw->phy.sfp_type =
1380                                                      ixgbe_sfp_type_da_cu_core0;
1381                                 else
1382                                         hw->phy.sfp_type =
1383                                                      ixgbe_sfp_type_da_cu_core1;
1384                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1385                                 hw->phy.ops.read_i2c_eeprom(
1386                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1387                                                 &cable_spec);
1388                                 if (cable_spec &
1389                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1390                                         if (hw->bus.lan_id == 0)
1391                                                 hw->phy.sfp_type =
1392                                                 ixgbe_sfp_type_da_act_lmt_core0;
1393                                         else
1394                                                 hw->phy.sfp_type =
1395                                                 ixgbe_sfp_type_da_act_lmt_core1;
1396                                 } else {
1397                                         hw->phy.sfp_type =
1398                                                         ixgbe_sfp_type_unknown;
1399                                 }
1400                         } else if (comp_codes_10g &
1401                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1402                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1403                                 if (hw->bus.lan_id == 0)
1404                                         hw->phy.sfp_type =
1405                                                       ixgbe_sfp_type_srlr_core0;
1406                                 else
1407                                         hw->phy.sfp_type =
1408                                                       ixgbe_sfp_type_srlr_core1;
1409                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1410                                 if (hw->bus.lan_id == 0)
1411                                         hw->phy.sfp_type =
1412                                                 ixgbe_sfp_type_1g_cu_core0;
1413                                 else
1414                                         hw->phy.sfp_type =
1415                                                 ixgbe_sfp_type_1g_cu_core1;
1416                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1417                                 if (hw->bus.lan_id == 0)
1418                                         hw->phy.sfp_type =
1419                                                 ixgbe_sfp_type_1g_sx_core0;
1420                                 else
1421                                         hw->phy.sfp_type =
1422                                                 ixgbe_sfp_type_1g_sx_core1;
1423                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1424                                 if (hw->bus.lan_id == 0)
1425                                         hw->phy.sfp_type =
1426                                                 ixgbe_sfp_type_1g_lx_core0;
1427                                 else
1428                                         hw->phy.sfp_type =
1429                                                 ixgbe_sfp_type_1g_lx_core1;
1430                         } else {
1431                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1432                         }
1433                 }
1434
1435                 if (hw->phy.sfp_type != stored_sfp_type)
1436                         hw->phy.sfp_setup_needed = TRUE;
1437
1438                 /* Determine if the SFP+ PHY is dual speed or not. */
1439                 hw->phy.multispeed_fiber = FALSE;
1440                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1441                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1442                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1443                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1444                         hw->phy.multispeed_fiber = TRUE;
1445
1446                 /* Determine PHY vendor */
1447                 if (hw->phy.type != ixgbe_phy_nl) {
1448                         hw->phy.id = identifier;
1449                         status = hw->phy.ops.read_i2c_eeprom(hw,
1450                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1451                                                     &oui_bytes[0]);
1452
1453                         if (status != IXGBE_SUCCESS)
1454                                 goto err_read_i2c_eeprom;
1455
1456                         status = hw->phy.ops.read_i2c_eeprom(hw,
1457                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1458                                                     &oui_bytes[1]);
1459
1460                         if (status != IXGBE_SUCCESS)
1461                                 goto err_read_i2c_eeprom;
1462
1463                         status = hw->phy.ops.read_i2c_eeprom(hw,
1464                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1465                                                     &oui_bytes[2]);
1466
1467                         if (status != IXGBE_SUCCESS)
1468                                 goto err_read_i2c_eeprom;
1469
1470                         vendor_oui =
1471                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1472                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1473                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1474
1475                         switch (vendor_oui) {
1476                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1477                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1478                                         hw->phy.type =
1479                                                     ixgbe_phy_sfp_passive_tyco;
1480                                 break;
1481                         case IXGBE_SFF_VENDOR_OUI_FTL:
1482                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1483                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1484                                 else
1485                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1486                                 break;
1487                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1488                                 hw->phy.type = ixgbe_phy_sfp_avago;
1489                                 break;
1490                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1491                                 hw->phy.type = ixgbe_phy_sfp_intel;
1492                                 break;
1493                         default:
1494                                 hw->phy.type = ixgbe_phy_sfp_unknown;
1495                                 break;
1496                         }
1497                 }
1498
1499                 /* Allow any DA cable vendor */
1500                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1501                         IXGBE_SFF_DA_ACTIVE_CABLE)) {
1502                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1503                                 hw->phy.type = ixgbe_phy_sfp_passive_unknown;
1504                         else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1505                                 hw->phy.type = ixgbe_phy_sfp_active_unknown;
1506                         status = IXGBE_SUCCESS;
1507                         goto out;
1508                 }
1509
1510                 /* Verify supported 1G SFP modules */
1511                 if (comp_codes_10g == 0 &&
1512                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1513                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1514                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1515                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1516                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1517                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1518                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1519                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1520                         goto out;
1521                 }
1522
1523                 /* Anything else 82598-based is supported */
1524                 if (hw->mac.type == ixgbe_mac_82598EB) {
1525                         status = IXGBE_SUCCESS;
1526                         goto out;
1527                 }
1528
1529                 ixgbe_get_device_caps(hw, &enforce_sfp);
1530                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1531                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1532                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1533                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1534                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1535                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1536                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1537                         /* Make sure we're a supported PHY type */
1538                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1539                                 status = IXGBE_SUCCESS;
1540                         } else {
1541                                 if (hw->allow_unsupported_sfp == TRUE) {
1542                                         EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1543                                         status = IXGBE_SUCCESS;
1544                                 } else {
1545                                         DEBUGOUT("SFP+ module not supported\n");
1546                                         hw->phy.type =
1547                                                 ixgbe_phy_sfp_unsupported;
1548                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1549                                 }
1550                         }
1551                 } else {
1552                         status = IXGBE_SUCCESS;
1553                 }
1554         }
1555
1556 out:
1557         return status;
1558
1559 err_read_i2c_eeprom:
1560         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1561         if (hw->phy.type != ixgbe_phy_nl) {
1562                 hw->phy.id = 0;
1563                 hw->phy.type = ixgbe_phy_unknown;
1564         }
1565         return IXGBE_ERR_SFP_NOT_PRESENT;
1566 }
1567
1568 /**
1569  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1570  *  @hw: pointer to hardware structure
1571  *
1572  *  Determines physical layer capabilities of the current SFP.
1573  */
1574 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1575 {
1576         u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1577         u8 comp_codes_10g = 0;
1578         u8 comp_codes_1g = 0;
1579
1580         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1581
1582         hw->phy.ops.identify_sfp(hw);
1583         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1584                 return physical_layer;
1585
1586         switch (hw->phy.type) {
1587         case ixgbe_phy_sfp_passive_tyco:
1588         case ixgbe_phy_sfp_passive_unknown:
1589         case ixgbe_phy_qsfp_passive_unknown:
1590                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1591                 break;
1592         case ixgbe_phy_sfp_ftl_active:
1593         case ixgbe_phy_sfp_active_unknown:
1594         case ixgbe_phy_qsfp_active_unknown:
1595                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1596                 break;
1597         case ixgbe_phy_sfp_avago:
1598         case ixgbe_phy_sfp_ftl:
1599         case ixgbe_phy_sfp_intel:
1600         case ixgbe_phy_sfp_unknown:
1601                 hw->phy.ops.read_i2c_eeprom(hw,
1602                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1603                 hw->phy.ops.read_i2c_eeprom(hw,
1604                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1605                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1606                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1607                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1608                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1609                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1610                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1611                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1612                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1613                 break;
1614         case ixgbe_phy_qsfp_intel:
1615         case ixgbe_phy_qsfp_unknown:
1616                 hw->phy.ops.read_i2c_eeprom(hw,
1617                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1618                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1619                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1620                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1621                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1622                 break;
1623         default:
1624                 break;
1625         }
1626
1627         return physical_layer;
1628 }
1629
1630 /**
1631  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1632  *  @hw: pointer to hardware structure
1633  *
1634  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1635  **/
1636 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1637 {
1638         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1639         u32 vendor_oui = 0;
1640         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1641         u8 identifier = 0;
1642         u8 comp_codes_1g = 0;
1643         u8 comp_codes_10g = 0;
1644         u8 oui_bytes[3] = {0, 0, 0};
1645         u16 enforce_sfp = 0;
1646         u8 connector = 0;
1647         u8 cable_length = 0;
1648         u8 device_tech = 0;
1649         bool active_cable = FALSE;
1650
1651         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1652
1653         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1654                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1655                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1656                 goto out;
1657         }
1658
1659         /* LAN ID is needed for I2C access */
1660         hw->mac.ops.set_lan_id(hw);
1661
1662         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1663                                              &identifier);
1664
1665         if (status != IXGBE_SUCCESS)
1666                 goto err_read_i2c_eeprom;
1667
1668         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1669                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1670                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1671                 goto out;
1672         }
1673
1674         hw->phy.id = identifier;
1675
1676         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1677                                              &comp_codes_10g);
1678
1679         if (status != IXGBE_SUCCESS)
1680                 goto err_read_i2c_eeprom;
1681
1682         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1683                                              &comp_codes_1g);
1684
1685         if (status != IXGBE_SUCCESS)
1686                 goto err_read_i2c_eeprom;
1687
1688         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1689                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1690                 if (hw->bus.lan_id == 0)
1691                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1692                 else
1693                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1694         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1695                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1696                 if (hw->bus.lan_id == 0)
1697                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1698                 else
1699                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1700         } else {
1701                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1702                         active_cable = TRUE;
1703
1704                 if (!active_cable) {
1705                         /* check for active DA cables that pre-date
1706                          * SFF-8436 v3.6 */
1707                         hw->phy.ops.read_i2c_eeprom(hw,
1708                                         IXGBE_SFF_QSFP_CONNECTOR,
1709                                         &connector);
1710
1711                         hw->phy.ops.read_i2c_eeprom(hw,
1712                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1713                                         &cable_length);
1714
1715                         hw->phy.ops.read_i2c_eeprom(hw,
1716                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1717                                         &device_tech);
1718
1719                         if ((connector ==
1720                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1721                             (cable_length > 0) &&
1722                             ((device_tech >> 4) ==
1723                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1724                                 active_cable = TRUE;
1725                 }
1726
1727                 if (active_cable) {
1728                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1729                         if (hw->bus.lan_id == 0)
1730                                 hw->phy.sfp_type =
1731                                                 ixgbe_sfp_type_da_act_lmt_core0;
1732                         else
1733                                 hw->phy.sfp_type =
1734                                                 ixgbe_sfp_type_da_act_lmt_core1;
1735                 } else {
1736                         /* unsupported module type */
1737                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1738                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1739                         goto out;
1740                 }
1741         }
1742
1743         if (hw->phy.sfp_type != stored_sfp_type)
1744                 hw->phy.sfp_setup_needed = TRUE;
1745
1746         /* Determine if the QSFP+ PHY is dual speed or not. */
1747         hw->phy.multispeed_fiber = FALSE;
1748         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1749            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1750            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1751            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1752                 hw->phy.multispeed_fiber = TRUE;
1753
1754         /* Determine PHY vendor for optical modules */
1755         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1756                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1757                 status = hw->phy.ops.read_i2c_eeprom(hw,
1758                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1759                                             &oui_bytes[0]);
1760
1761                 if (status != IXGBE_SUCCESS)
1762                         goto err_read_i2c_eeprom;
1763
1764                 status = hw->phy.ops.read_i2c_eeprom(hw,
1765                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1766                                             &oui_bytes[1]);
1767
1768                 if (status != IXGBE_SUCCESS)
1769                         goto err_read_i2c_eeprom;
1770
1771                 status = hw->phy.ops.read_i2c_eeprom(hw,
1772                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1773                                             &oui_bytes[2]);
1774
1775                 if (status != IXGBE_SUCCESS)
1776                         goto err_read_i2c_eeprom;
1777
1778                 vendor_oui =
1779                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1780                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1781                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1782
1783                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1784                         hw->phy.type = ixgbe_phy_qsfp_intel;
1785                 else
1786                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1787
1788                 ixgbe_get_device_caps(hw, &enforce_sfp);
1789                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1790                         /* Make sure we're a supported PHY type */
1791                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1792                                 status = IXGBE_SUCCESS;
1793                         } else {
1794                                 if (hw->allow_unsupported_sfp == TRUE) {
1795                                         EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1796                                         status = IXGBE_SUCCESS;
1797                                 } else {
1798                                         DEBUGOUT("QSFP module not supported\n");
1799                                         hw->phy.type =
1800                                                 ixgbe_phy_sfp_unsupported;
1801                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1802                                 }
1803                         }
1804                 } else {
1805                         status = IXGBE_SUCCESS;
1806                 }
1807         }
1808
1809 out:
1810         return status;
1811
1812 err_read_i2c_eeprom:
1813         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1814         hw->phy.id = 0;
1815         hw->phy.type = ixgbe_phy_unknown;
1816
1817         return IXGBE_ERR_SFP_NOT_PRESENT;
1818 }
1819
1820 /**
1821  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1822  *  @hw: pointer to hardware structure
1823  *  @list_offset: offset to the SFP ID list
1824  *  @data_offset: offset to the SFP data block
1825  *
1826  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1827  *  so it returns the offsets to the phy init sequence block.
1828  **/
1829 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1830                                         u16 *list_offset,
1831                                         u16 *data_offset)
1832 {
1833         u16 sfp_id;
1834         u16 sfp_type = hw->phy.sfp_type;
1835
1836         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1837
1838         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1839                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1840
1841         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1842                 return IXGBE_ERR_SFP_NOT_PRESENT;
1843
1844         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1845             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1846                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1847
1848         /*
1849          * Limiting active cables and 1G Phys must be initialized as
1850          * SR modules
1851          */
1852         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1853             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1854             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1855             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1856                 sfp_type = ixgbe_sfp_type_srlr_core0;
1857         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1858                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1859                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1860                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1861                 sfp_type = ixgbe_sfp_type_srlr_core1;
1862
1863         /* Read offset to PHY init contents */
1864         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1865                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1866                               "eeprom read at offset %d failed",
1867                               IXGBE_PHY_INIT_OFFSET_NL);
1868                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1869         }
1870
1871         if ((!*list_offset) || (*list_offset == 0xFFFF))
1872                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1873
1874         /* Shift offset to first ID word */
1875         (*list_offset)++;
1876
1877         /*
1878          * Find the matching SFP ID in the EEPROM
1879          * and program the init sequence
1880          */
1881         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1882                 goto err_phy;
1883
1884         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1885                 if (sfp_id == sfp_type) {
1886                         (*list_offset)++;
1887                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1888                                 goto err_phy;
1889                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1890                                 DEBUGOUT("SFP+ module not supported\n");
1891                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1892                         } else {
1893                                 break;
1894                         }
1895                 } else {
1896                         (*list_offset) += 2;
1897                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1898                                 goto err_phy;
1899                 }
1900         }
1901
1902         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1903                 DEBUGOUT("No matching SFP+ module found\n");
1904                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1905         }
1906
1907         return IXGBE_SUCCESS;
1908
1909 err_phy:
1910         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1911                       "eeprom read at offset %d failed", *list_offset);
1912         return IXGBE_ERR_PHY;
1913 }
1914
1915 /**
1916  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1917  *  @hw: pointer to hardware structure
1918  *  @byte_offset: EEPROM byte offset to read
1919  *  @eeprom_data: value read
1920  *
1921  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1922  **/
1923 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1924                                   u8 *eeprom_data)
1925 {
1926         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1927
1928         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1929                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1930                                          eeprom_data);
1931 }
1932
1933 /**
1934  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1935  *  @hw: pointer to hardware structure
1936  *  @byte_offset: byte offset at address 0xA2
1937  *  @eeprom_data: value read
1938  *
1939  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1940  **/
1941 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1942                                           u8 *sff8472_data)
1943 {
1944         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1945                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1946                                          sff8472_data);
1947 }
1948
1949 /**
1950  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1951  *  @hw: pointer to hardware structure
1952  *  @byte_offset: EEPROM byte offset to write
1953  *  @eeprom_data: value to write
1954  *
1955  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1956  **/
1957 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1958                                    u8 eeprom_data)
1959 {
1960         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1961
1962         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1963                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1964                                           eeprom_data);
1965 }
1966
1967 /**
1968  * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected
1969  * @hw: pointer to hardware structure
1970  * @offset: eeprom offset to be read
1971  * @addr: I2C address to be read
1972  */
1973 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1974 {
1975         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1976             offset == IXGBE_SFF_IDENTIFIER &&
1977             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1978                 return TRUE;
1979         return FALSE;
1980 }
1981
1982 /**
1983  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1984  *  @hw: pointer to hardware structure
1985  *  @byte_offset: byte offset to read
1986  *  @data: value read
1987  *  @lock: TRUE if to take and release semaphore
1988  *
1989  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1990  *  a specified device address.
1991  **/
1992 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1993                                            u8 dev_addr, u8 *data, bool lock)
1994 {
1995         s32 status;
1996         u32 max_retry = 10;
1997         u32 retry = 0;
1998         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1999         bool nack = 1;
2000         *data = 0;
2001
2002         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2003
2004         if (hw->mac.type >= ixgbe_mac_X550)
2005                 max_retry = 3;
2006         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2007                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2008
2009         do {
2010                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2011                         return IXGBE_ERR_SWFW_SYNC;
2012
2013                 ixgbe_i2c_start(hw);
2014
2015                 /* Device Address and write indication */
2016                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2017                 if (status != IXGBE_SUCCESS)
2018                         goto fail;
2019
2020                 status = ixgbe_get_i2c_ack(hw);
2021                 if (status != IXGBE_SUCCESS)
2022                         goto fail;
2023
2024                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2025                 if (status != IXGBE_SUCCESS)
2026                         goto fail;
2027
2028                 status = ixgbe_get_i2c_ack(hw);
2029                 if (status != IXGBE_SUCCESS)
2030                         goto fail;
2031
2032                 ixgbe_i2c_start(hw);
2033
2034                 /* Device Address and read indication */
2035                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2036                 if (status != IXGBE_SUCCESS)
2037                         goto fail;
2038
2039                 status = ixgbe_get_i2c_ack(hw);
2040                 if (status != IXGBE_SUCCESS)
2041                         goto fail;
2042
2043                 status = ixgbe_clock_in_i2c_byte(hw, data);
2044                 if (status != IXGBE_SUCCESS)
2045                         goto fail;
2046
2047                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2048                 if (status != IXGBE_SUCCESS)
2049                         goto fail;
2050
2051                 ixgbe_i2c_stop(hw);
2052                 if (lock)
2053                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2054                 return IXGBE_SUCCESS;
2055
2056 fail:
2057                 ixgbe_i2c_bus_clear(hw);
2058                 if (lock) {
2059                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2060                         msec_delay(100);
2061                 }
2062                 retry++;
2063                 if (retry < max_retry)
2064                         DEBUGOUT("I2C byte read error - Retrying.\n");
2065                 else
2066                         DEBUGOUT("I2C byte read error.\n");
2067
2068         } while (retry < max_retry);
2069
2070         return status;
2071 }
2072
2073 /**
2074  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2075  *  @hw: pointer to hardware structure
2076  *  @byte_offset: byte offset to read
2077  *  @data: value read
2078  *
2079  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2080  *  a specified device address.
2081  **/
2082 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2083                                 u8 dev_addr, u8 *data)
2084 {
2085         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2086                                                data, TRUE);
2087 }
2088
2089 /**
2090  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2091  *  @hw: pointer to hardware structure
2092  *  @byte_offset: byte offset to read
2093  *  @data: value read
2094  *
2095  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2096  *  a specified device address.
2097  **/
2098 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2099                                          u8 dev_addr, u8 *data)
2100 {
2101         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2102                                                data, FALSE);
2103 }
2104
2105 /**
2106  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2107  *  @hw: pointer to hardware structure
2108  *  @byte_offset: byte offset to write
2109  *  @data: value to write
2110  *  @lock: TRUE if to take and release semaphore
2111  *
2112  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2113  *  a specified device address.
2114  **/
2115 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2116                                             u8 dev_addr, u8 data, bool lock)
2117 {
2118         s32 status;
2119         u32 max_retry = 1;
2120         u32 retry = 0;
2121         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2122
2123         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2124
2125         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2126             IXGBE_SUCCESS)
2127                 return IXGBE_ERR_SWFW_SYNC;
2128
2129         do {
2130                 ixgbe_i2c_start(hw);
2131
2132                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2133                 if (status != IXGBE_SUCCESS)
2134                         goto fail;
2135
2136                 status = ixgbe_get_i2c_ack(hw);
2137                 if (status != IXGBE_SUCCESS)
2138                         goto fail;
2139
2140                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2141                 if (status != IXGBE_SUCCESS)
2142                         goto fail;
2143
2144                 status = ixgbe_get_i2c_ack(hw);
2145                 if (status != IXGBE_SUCCESS)
2146                         goto fail;
2147
2148                 status = ixgbe_clock_out_i2c_byte(hw, data);
2149                 if (status != IXGBE_SUCCESS)
2150                         goto fail;
2151
2152                 status = ixgbe_get_i2c_ack(hw);
2153                 if (status != IXGBE_SUCCESS)
2154                         goto fail;
2155
2156                 ixgbe_i2c_stop(hw);
2157                 if (lock)
2158                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2159                 return IXGBE_SUCCESS;
2160
2161 fail:
2162                 ixgbe_i2c_bus_clear(hw);
2163                 retry++;
2164                 if (retry < max_retry)
2165                         DEBUGOUT("I2C byte write error - Retrying.\n");
2166                 else
2167                         DEBUGOUT("I2C byte write error.\n");
2168         } while (retry < max_retry);
2169
2170         if (lock)
2171                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2172
2173         return status;
2174 }
2175
2176 /**
2177  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2178  *  @hw: pointer to hardware structure
2179  *  @byte_offset: byte offset to write
2180  *  @data: value to write
2181  *
2182  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2183  *  a specified device address.
2184  **/
2185 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2186                                  u8 dev_addr, u8 data)
2187 {
2188         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2189                                                 data, TRUE);
2190 }
2191
2192 /**
2193  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2194  *  @hw: pointer to hardware structure
2195  *  @byte_offset: byte offset to write
2196  *  @data: value to write
2197  *
2198  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2199  *  a specified device address.
2200  **/
2201 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2202                                           u8 dev_addr, u8 data)
2203 {
2204         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2205                                                 data, FALSE);
2206 }
2207
2208 /**
2209  *  ixgbe_i2c_start - Sets I2C start condition
2210  *  @hw: pointer to hardware structure
2211  *
2212  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2213  *  Set bit-bang mode on X550 hardware.
2214  **/
2215 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2216 {
2217         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2218
2219         DEBUGFUNC("ixgbe_i2c_start");
2220
2221         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2222
2223         /* Start condition must begin with data and clock high */
2224         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2225         ixgbe_raise_i2c_clk(hw, &i2cctl);
2226
2227         /* Setup time for start condition (4.7us) */
2228         usec_delay(IXGBE_I2C_T_SU_STA);
2229
2230         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2231
2232         /* Hold time for start condition (4us) */
2233         usec_delay(IXGBE_I2C_T_HD_STA);
2234
2235         ixgbe_lower_i2c_clk(hw, &i2cctl);
2236
2237         /* Minimum low period of clock is 4.7 us */
2238         usec_delay(IXGBE_I2C_T_LOW);
2239
2240 }
2241
2242 /**
2243  *  ixgbe_i2c_stop - Sets I2C stop condition
2244  *  @hw: pointer to hardware structure
2245  *
2246  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2247  *  Disables bit-bang mode and negates data output enable on X550
2248  *  hardware.
2249  **/
2250 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2251 {
2252         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2253         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2254         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2255         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2256
2257         DEBUGFUNC("ixgbe_i2c_stop");
2258
2259         /* Stop condition must begin with data low and clock high */
2260         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2261         ixgbe_raise_i2c_clk(hw, &i2cctl);
2262
2263         /* Setup time for stop condition (4us) */
2264         usec_delay(IXGBE_I2C_T_SU_STO);
2265
2266         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2267
2268         /* bus free time between stop and start (4.7us)*/
2269         usec_delay(IXGBE_I2C_T_BUF);
2270
2271         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2272                 i2cctl &= ~bb_en_bit;
2273                 i2cctl |= data_oe_bit | clk_oe_bit;
2274                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2275                 IXGBE_WRITE_FLUSH(hw);
2276         }
2277 }
2278
2279 /**
2280  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2281  *  @hw: pointer to hardware structure
2282  *  @data: data byte to clock in
2283  *
2284  *  Clocks in one byte data via I2C data/clock
2285  **/
2286 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2287 {
2288         s32 i;
2289         bool bit = 0;
2290
2291         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2292
2293         *data = 0;
2294         for (i = 7; i >= 0; i--) {
2295                 ixgbe_clock_in_i2c_bit(hw, &bit);
2296                 *data |= bit << i;
2297         }
2298
2299         return IXGBE_SUCCESS;
2300 }
2301
2302 /**
2303  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2304  *  @hw: pointer to hardware structure
2305  *  @data: data byte clocked out
2306  *
2307  *  Clocks out one byte data via I2C data/clock
2308  **/
2309 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2310 {
2311         s32 status = IXGBE_SUCCESS;
2312         s32 i;
2313         u32 i2cctl;
2314         bool bit;
2315
2316         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2317
2318         for (i = 7; i >= 0; i--) {
2319                 bit = (data >> i) & 0x1;
2320                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2321
2322                 if (status != IXGBE_SUCCESS)
2323                         break;
2324         }
2325
2326         /* Release SDA line (set high) */
2327         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2328         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2329         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2330         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2331         IXGBE_WRITE_FLUSH(hw);
2332
2333         return status;
2334 }
2335
2336 /**
2337  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2338  *  @hw: pointer to hardware structure
2339  *
2340  *  Clocks in/out one bit via I2C data/clock
2341  **/
2342 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2343 {
2344         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2345         s32 status = IXGBE_SUCCESS;
2346         u32 i = 0;
2347         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2348         u32 timeout = 10;
2349         bool ack = 1;
2350
2351         DEBUGFUNC("ixgbe_get_i2c_ack");
2352
2353         if (data_oe_bit) {
2354                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2355                 i2cctl |= data_oe_bit;
2356                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2357                 IXGBE_WRITE_FLUSH(hw);
2358         }
2359         ixgbe_raise_i2c_clk(hw, &i2cctl);
2360
2361         /* Minimum high period of clock is 4us */
2362         usec_delay(IXGBE_I2C_T_HIGH);
2363
2364         /* Poll for ACK.  Note that ACK in I2C spec is
2365          * transition from 1 to 0 */
2366         for (i = 0; i < timeout; i++) {
2367                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2368                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2369
2370                 usec_delay(1);
2371                 if (!ack)
2372                         break;
2373         }
2374
2375         if (ack) {
2376                 DEBUGOUT("I2C ack was not received.\n");
2377                 status = IXGBE_ERR_I2C;
2378         }
2379
2380         ixgbe_lower_i2c_clk(hw, &i2cctl);
2381
2382         /* Minimum low period of clock is 4.7 us */
2383         usec_delay(IXGBE_I2C_T_LOW);
2384
2385         return status;
2386 }
2387
2388 /**
2389  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2390  *  @hw: pointer to hardware structure
2391  *  @data: read data value
2392  *
2393  *  Clocks in one bit via I2C data/clock
2394  **/
2395 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2396 {
2397         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2398         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2399
2400         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2401
2402         if (data_oe_bit) {
2403                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2404                 i2cctl |= data_oe_bit;
2405                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2406                 IXGBE_WRITE_FLUSH(hw);
2407         }
2408         ixgbe_raise_i2c_clk(hw, &i2cctl);
2409
2410         /* Minimum high period of clock is 4us */
2411         usec_delay(IXGBE_I2C_T_HIGH);
2412
2413         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2414         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2415
2416         ixgbe_lower_i2c_clk(hw, &i2cctl);
2417
2418         /* Minimum low period of clock is 4.7 us */
2419         usec_delay(IXGBE_I2C_T_LOW);
2420
2421         return IXGBE_SUCCESS;
2422 }
2423
2424 /**
2425  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2426  *  @hw: pointer to hardware structure
2427  *  @data: data value to write
2428  *
2429  *  Clocks out one bit via I2C data/clock
2430  **/
2431 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2432 {
2433         s32 status;
2434         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2435
2436         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2437
2438         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2439         if (status == IXGBE_SUCCESS) {
2440                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2441
2442                 /* Minimum high period of clock is 4us */
2443                 usec_delay(IXGBE_I2C_T_HIGH);
2444
2445                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2446
2447                 /* Minimum low period of clock is 4.7 us.
2448                  * This also takes care of the data hold time.
2449                  */
2450                 usec_delay(IXGBE_I2C_T_LOW);
2451         } else {
2452                 status = IXGBE_ERR_I2C;
2453                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2454                              "I2C data was not set to %X\n", data);
2455         }
2456
2457         return status;
2458 }
2459
2460 /**
2461  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2462  *  @hw: pointer to hardware structure
2463  *  @i2cctl: Current value of I2CCTL register
2464  *
2465  *  Raises the I2C clock line '0'->'1'
2466  *  Negates the I2C clock output enable on X550 hardware.
2467  **/
2468 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2469 {
2470         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2471         u32 i = 0;
2472         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2473         u32 i2cctl_r = 0;
2474
2475         DEBUGFUNC("ixgbe_raise_i2c_clk");
2476
2477         if (clk_oe_bit) {
2478                 *i2cctl |= clk_oe_bit;
2479                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2480         }
2481
2482         for (i = 0; i < timeout; i++) {
2483                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2484
2485                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2486                 IXGBE_WRITE_FLUSH(hw);
2487                 /* SCL rise time (1000ns) */
2488                 usec_delay(IXGBE_I2C_T_RISE);
2489
2490                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2491                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2492                         break;
2493         }
2494 }
2495
2496 /**
2497  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2498  *  @hw: pointer to hardware structure
2499  *  @i2cctl: Current value of I2CCTL register
2500  *
2501  *  Lowers the I2C clock line '1'->'0'
2502  *  Asserts the I2C clock output enable on X550 hardware.
2503  **/
2504 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2505 {
2506         DEBUGFUNC("ixgbe_lower_i2c_clk");
2507
2508         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2509         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2510
2511         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2512         IXGBE_WRITE_FLUSH(hw);
2513
2514         /* SCL fall time (300ns) */
2515         usec_delay(IXGBE_I2C_T_FALL);
2516 }
2517
2518 /**
2519  *  ixgbe_set_i2c_data - Sets the I2C data bit
2520  *  @hw: pointer to hardware structure
2521  *  @i2cctl: Current value of I2CCTL register
2522  *  @data: I2C data value (0 or 1) to set
2523  *
2524  *  Sets the I2C data bit
2525  *  Asserts the I2C data output enable on X550 hardware.
2526  **/
2527 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2528 {
2529         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2530         s32 status = IXGBE_SUCCESS;
2531
2532         DEBUGFUNC("ixgbe_set_i2c_data");
2533
2534         if (data)
2535                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2536         else
2537                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2538         *i2cctl &= ~data_oe_bit;
2539
2540         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2541         IXGBE_WRITE_FLUSH(hw);
2542
2543         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2544         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2545
2546         if (!data)      /* Can't verify data in this case */
2547                 return IXGBE_SUCCESS;
2548         if (data_oe_bit) {
2549                 *i2cctl |= data_oe_bit;
2550                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2551                 IXGBE_WRITE_FLUSH(hw);
2552         }
2553
2554         /* Verify data was set correctly */
2555         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2556         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2557                 status = IXGBE_ERR_I2C;
2558                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2559                              "Error - I2C data was not set to %X.\n",
2560                              data);
2561         }
2562
2563         return status;
2564 }
2565
2566 /**
2567  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2568  *  @hw: pointer to hardware structure
2569  *  @i2cctl: Current value of I2CCTL register
2570  *
2571  *  Returns the I2C data bit value
2572  *  Negates the I2C data output enable on X550 hardware.
2573  **/
2574 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2575 {
2576         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2577         bool data;
2578
2579         DEBUGFUNC("ixgbe_get_i2c_data");
2580
2581         if (data_oe_bit) {
2582                 *i2cctl |= data_oe_bit;
2583                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2584                 IXGBE_WRITE_FLUSH(hw);
2585                 usec_delay(IXGBE_I2C_T_FALL);
2586         }
2587
2588         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2589                 data = 1;
2590         else
2591                 data = 0;
2592
2593         return data;
2594 }
2595
2596 /**
2597  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2598  *  @hw: pointer to hardware structure
2599  *
2600  *  Clears the I2C bus by sending nine clock pulses.
2601  *  Used when data line is stuck low.
2602  **/
2603 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2604 {
2605         u32 i2cctl;
2606         u32 i;
2607
2608         DEBUGFUNC("ixgbe_i2c_bus_clear");
2609
2610         ixgbe_i2c_start(hw);
2611         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2612
2613         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2614
2615         for (i = 0; i < 9; i++) {
2616                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2617
2618                 /* Min high period of clock is 4us */
2619                 usec_delay(IXGBE_I2C_T_HIGH);
2620
2621                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2622
2623                 /* Min low period of clock is 4.7us*/
2624                 usec_delay(IXGBE_I2C_T_LOW);
2625         }
2626
2627         ixgbe_i2c_start(hw);
2628
2629         /* Put the i2c bus back to default state */
2630         ixgbe_i2c_stop(hw);
2631 }
2632
2633 /**
2634  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2635  *  @hw: pointer to hardware structure
2636  *
2637  *  Checks if the LASI temp alarm status was triggered due to overtemp
2638  **/
2639 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2640 {
2641         s32 status = IXGBE_SUCCESS;
2642         u16 phy_data = 0;
2643
2644         DEBUGFUNC("ixgbe_tn_check_overtemp");
2645
2646         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2647                 goto out;
2648
2649         /* Check that the LASI temp alarm status was triggered */
2650         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2651                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2652
2653         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2654                 goto out;
2655
2656         status = IXGBE_ERR_OVERTEMP;
2657         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2658 out:
2659         return status;
2660 }
2661
2662 /**
2663  * ixgbe_set_copper_phy_power - Control power for copper phy
2664  * @hw: pointer to hardware structure
2665  * @on: TRUE for on, FALSE for off
2666  */
2667 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2668 {
2669         u32 status;
2670         u16 reg;
2671
2672         if (!on && ixgbe_mng_present(hw))
2673                 return 0;
2674
2675         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2676                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2677                                       &reg);
2678         if (status)
2679                 return status;
2680
2681         if (on) {
2682                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2683         } else {
2684                 if (ixgbe_check_reset_blocked(hw))
2685                         return 0;
2686                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2687         }
2688
2689         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2690                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2691                                        reg);
2692         return status;
2693 }