1 /******************************************************************************
3 Copyright (c) 2001-2013, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
38 #include "ixgbe_type.h"
39 #define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
40 #define IXGBE_I2C_EEPROM_DEV_ADDR2 0xA2
41 #define IXGBE_I2C_EEPROM_BANK_LEN 0xFF
43 /* EEPROM byte offsets */
44 #define IXGBE_SFF_IDENTIFIER 0x0
45 #define IXGBE_SFF_IDENTIFIER_SFP 0x3
46 #define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25
47 #define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26
48 #define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
49 #define IXGBE_SFF_1GBE_COMP_CODES 0x6
50 #define IXGBE_SFF_10GBE_COMP_CODES 0x3
51 #define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
52 #define IXGBE_SFF_CABLE_SPEC_COMP 0x3C
53 #define IXGBE_SFF_SFF_8472_SWAP 0x5C
54 #define IXGBE_SFF_SFF_8472_COMP 0x5E
55 #define IXGBE_SFF_SFF_8472_OSCB 0x6E
56 #define IXGBE_SFF_SFF_8472_ESCB 0x76
59 #define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
60 #define IXGBE_SFF_DA_ACTIVE_CABLE 0x8
61 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
62 #define IXGBE_SFF_1GBASESX_CAPABLE 0x1
63 #define IXGBE_SFF_1GBASELX_CAPABLE 0x2
64 #define IXGBE_SFF_1GBASET_CAPABLE 0x8
65 #define IXGBE_SFF_10GBASESR_CAPABLE 0x10
66 #define IXGBE_SFF_10GBASELR_CAPABLE 0x20
67 #define IXGBE_SFF_SOFT_RS_SELECT_MASK 0x8
68 #define IXGBE_SFF_SOFT_RS_SELECT_10G 0x8
69 #define IXGBE_SFF_SOFT_RS_SELECT_1G 0x0
70 #define IXGBE_I2C_EEPROM_READ_MASK 0x100
71 #define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
72 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
73 #define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
74 #define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
75 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
77 /* Flow control defines */
78 #define IXGBE_TAF_SYM_PAUSE 0x400
79 #define IXGBE_TAF_ASM_PAUSE 0x800
81 /* Bit-shift macros */
82 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
83 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
84 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
86 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
87 #define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
88 #define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
89 #define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
90 #define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
92 /* I2C SDA and SCL timing parameters for standard mode */
93 #define IXGBE_I2C_T_HD_STA 4
94 #define IXGBE_I2C_T_LOW 5
95 #define IXGBE_I2C_T_HIGH 4
96 #define IXGBE_I2C_T_SU_STA 5
97 #define IXGBE_I2C_T_HD_DATA 5
98 #define IXGBE_I2C_T_SU_DATA 1
99 #define IXGBE_I2C_T_RISE 1
100 #define IXGBE_I2C_T_FALL 1
101 #define IXGBE_I2C_T_SU_STO 4
102 #define IXGBE_I2C_T_BUF 5
104 #define IXGBE_TN_LASI_STATUS_REG 0x9005
105 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
107 /* SFP+ SFF-8472 Compliance */
108 #define IXGBE_SFF_SFF_8472_UNSUP 0x00
109 #define IXGBE_SFF_SFF_8472_REV_9_3 0x01
110 #define IXGBE_SFF_SFF_8472_REV_9_5 0x02
111 #define IXGBE_SFF_SFF_8472_REV_10_2 0x03
112 #define IXGBE_SFF_SFF_8472_REV_10_4 0x04
113 #define IXGBE_SFF_SFF_8472_REV_11_0 0x05
115 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
116 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
117 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
118 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
119 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
120 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
121 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
123 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
125 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
126 u32 device_type, u16 *phy_data);
127 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
128 u32 device_type, u16 phy_data);
129 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
130 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
131 ixgbe_link_speed speed,
132 bool autoneg_wait_to_complete);
133 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
134 ixgbe_link_speed *speed,
138 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
139 ixgbe_link_speed *speed,
141 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
142 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
143 u16 *firmware_version);
144 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
145 u16 *firmware_version);
147 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
148 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
149 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
150 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
153 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
154 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
155 u8 dev_addr, u8 *data);
156 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
157 u8 dev_addr, u8 data);
158 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
160 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
162 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
163 #endif /* _IXGBE_PHY_H_ */