1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2017, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
33 ******************************************************************************/
36 #include "ixgbe_x540.h"
37 #include "ixgbe_type.h"
38 #include "ixgbe_api.h"
39 #include "ixgbe_common.h"
40 #include "ixgbe_phy.h"
42 #define IXGBE_X540_MAX_TX_QUEUES 128
43 #define IXGBE_X540_MAX_RX_QUEUES 128
44 #define IXGBE_X540_RAR_ENTRIES 128
45 #define IXGBE_X540_MC_TBL_SIZE 128
46 #define IXGBE_X540_VFT_TBL_SIZE 128
47 #define IXGBE_X540_RX_PB_SIZE 384
49 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
50 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
51 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
54 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
55 * @hw: pointer to hardware structure
57 * Initialize the function pointers and assign the MAC type for X540.
58 * Does not touch the hardware.
60 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
62 struct ixgbe_mac_info *mac = &hw->mac;
63 struct ixgbe_phy_info *phy = &hw->phy;
64 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
67 DEBUGFUNC("ixgbe_init_ops_X540");
69 ret_val = ixgbe_init_phy_ops_generic(hw);
70 ret_val = ixgbe_init_ops_generic(hw);
74 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
75 eeprom->ops.read = ixgbe_read_eerd_X540;
76 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540;
77 eeprom->ops.write = ixgbe_write_eewr_X540;
78 eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540;
79 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540;
80 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540;
81 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540;
84 phy->ops.init = ixgbe_init_phy_ops_generic;
85 phy->ops.reset = NULL;
86 phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
89 mac->ops.reset_hw = ixgbe_reset_hw_X540;
90 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
91 mac->ops.get_media_type = ixgbe_get_media_type_X540;
92 mac->ops.get_supported_physical_layer =
93 ixgbe_get_supported_physical_layer_X540;
94 mac->ops.read_analog_reg8 = NULL;
95 mac->ops.write_analog_reg8 = NULL;
96 mac->ops.start_hw = ixgbe_start_hw_X540;
97 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
98 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
99 mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
100 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
101 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
102 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540;
103 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540;
104 mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540;
105 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
106 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
108 /* RAR, Multicast, VLAN */
109 mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
110 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
111 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
112 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
113 mac->rar_highwater = 1;
114 mac->ops.set_vfta = ixgbe_set_vfta_generic;
115 mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
116 mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
117 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
118 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
119 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
122 mac->ops.get_link_capabilities =
123 ixgbe_get_copper_link_capabilities_generic;
124 mac->ops.setup_link = ixgbe_setup_mac_link_X540;
125 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
126 mac->ops.check_link = ixgbe_check_mac_link_generic;
127 mac->ops.bypass_rw = ixgbe_bypass_rw_generic;
128 mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic;
129 mac->ops.bypass_set = ixgbe_bypass_set_generic;
130 mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic;
133 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
134 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
135 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
136 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
137 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
138 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
139 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
143 * ARC supported; valid only if manageability features are
146 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
147 & IXGBE_FWSM_MODE_MASK);
149 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
152 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
153 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
155 /* Manageability interface */
156 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
158 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
164 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
165 * @hw: pointer to hardware structure
166 * @speed: pointer to link speed
167 * @autoneg: TRUE when autoneg or autotry is enabled
169 * Determines the link capabilities by reading the AUTOC register.
171 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
172 ixgbe_link_speed *speed,
175 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
177 return IXGBE_SUCCESS;
181 * ixgbe_get_media_type_X540 - Get media type
182 * @hw: pointer to hardware structure
184 * Returns the media type (fiber, copper, backplane)
186 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
188 UNREFERENCED_1PARAMETER(hw);
189 return ixgbe_media_type_copper;
193 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
194 * @hw: pointer to hardware structure
195 * @speed: new link speed
196 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
198 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
199 ixgbe_link_speed speed,
200 bool autoneg_wait_to_complete)
202 DEBUGFUNC("ixgbe_setup_mac_link_X540");
203 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
207 * ixgbe_reset_hw_X540 - Perform hardware reset
208 * @hw: pointer to hardware structure
210 * Resets the hardware by resetting the transmit and receive units, masks
211 * and clears all interrupts, and perform a reset.
213 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
217 u32 swfw_mask = hw->phy.phy_semaphore_mask;
219 DEBUGFUNC("ixgbe_reset_hw_X540");
221 /* Call adapter stop to disable tx/rx and clear interrupts */
222 status = hw->mac.ops.stop_adapter(hw);
223 if (status != IXGBE_SUCCESS)
226 /* flush pending Tx transactions */
227 ixgbe_clear_tx_pending(hw);
230 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
231 if (status != IXGBE_SUCCESS) {
232 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
233 "semaphore failed with %d", status);
234 return IXGBE_ERR_SWFW_SYNC;
236 ctrl = IXGBE_CTRL_RST;
237 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
238 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
239 IXGBE_WRITE_FLUSH(hw);
240 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
242 /* Poll for reset bit to self-clear indicating reset is complete */
243 for (i = 0; i < 10; i++) {
245 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
246 if (!(ctrl & IXGBE_CTRL_RST_MASK))
250 if (ctrl & IXGBE_CTRL_RST_MASK) {
251 status = IXGBE_ERR_RESET_FAILED;
252 ERROR_REPORT1(IXGBE_ERROR_POLLING,
253 "Reset polling failed to complete.\n");
258 * Double resets are required for recovery from certain error
259 * conditions. Between resets, it is necessary to stall to allow time
260 * for any pending HW events to complete.
262 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
263 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
267 /* Set the Rx packet buffer size. */
268 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
270 /* Store the permanent mac address */
271 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
274 * Store MAC address from RAR0, clear receive address registers, and
275 * clear the multicast table. Also reset num_rar_entries to 128,
276 * since we modify this value when programming the SAN MAC address.
278 hw->mac.num_rar_entries = 128;
279 hw->mac.ops.init_rx_addrs(hw);
281 /* Store the permanent SAN mac address */
282 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
284 /* Add the SAN MAC address to the RAR only if it's a valid address */
285 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
286 /* Save the SAN MAC RAR index */
287 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
289 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
290 hw->mac.san_addr, 0, IXGBE_RAH_AV);
292 /* clear VMDq pool/queue selection for this RAR */
293 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
294 IXGBE_CLEAR_VMDQ_ALL);
296 /* Reserve the last RAR for the SAN MAC address */
297 hw->mac.num_rar_entries--;
300 /* Store the alternative WWNN/WWPN prefix */
301 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
302 &hw->mac.wwpn_prefix);
309 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
310 * @hw: pointer to hardware structure
312 * Starts the hardware using the generic start_hw function
313 * and the generation start_hw function.
314 * Then performs revision-specific operations, if any.
316 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
318 s32 ret_val = IXGBE_SUCCESS;
320 DEBUGFUNC("ixgbe_start_hw_X540");
322 ret_val = ixgbe_start_hw_generic(hw);
323 if (ret_val != IXGBE_SUCCESS)
326 ret_val = ixgbe_start_hw_gen2(hw);
333 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
334 * @hw: pointer to hardware structure
336 * Determines physical layer capabilities of the current configuration.
338 u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
340 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
343 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
345 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
346 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
347 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
348 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
349 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
350 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
351 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
352 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
354 return physical_layer;
358 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
359 * @hw: pointer to hardware structure
361 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
362 * ixgbe_hw struct in order to set up EEPROM access.
364 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
366 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
370 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
372 if (eeprom->type == ixgbe_eeprom_uninitialized) {
373 eeprom->semaphore_delay = 10;
374 eeprom->type = ixgbe_flash;
376 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
377 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
378 IXGBE_EEC_SIZE_SHIFT);
379 eeprom->word_size = 1 << (eeprom_size +
380 IXGBE_EEPROM_WORD_SIZE_SHIFT);
382 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
383 eeprom->type, eeprom->word_size);
386 return IXGBE_SUCCESS;
390 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
391 * @hw: pointer to hardware structure
392 * @offset: offset of word in the EEPROM to read
393 * @data: word read from the EEPROM
395 * Reads a 16 bit word from the EEPROM using the EERD register.
397 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
399 s32 status = IXGBE_SUCCESS;
401 DEBUGFUNC("ixgbe_read_eerd_X540");
402 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
404 status = ixgbe_read_eerd_generic(hw, offset, data);
405 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
407 status = IXGBE_ERR_SWFW_SYNC;
414 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
415 * @hw: pointer to hardware structure
416 * @offset: offset of word in the EEPROM to read
417 * @words: number of words
418 * @data: word(s) read from the EEPROM
420 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
422 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
423 u16 offset, u16 words, u16 *data)
425 s32 status = IXGBE_SUCCESS;
427 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
428 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
430 status = ixgbe_read_eerd_buffer_generic(hw, offset,
432 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
434 status = IXGBE_ERR_SWFW_SYNC;
441 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
442 * @hw: pointer to hardware structure
443 * @offset: offset of word in the EEPROM to write
444 * @data: word write to the EEPROM
446 * Write a 16 bit word to the EEPROM using the EEWR register.
448 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
450 s32 status = IXGBE_SUCCESS;
452 DEBUGFUNC("ixgbe_write_eewr_X540");
453 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
455 status = ixgbe_write_eewr_generic(hw, offset, data);
456 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
458 status = IXGBE_ERR_SWFW_SYNC;
465 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
466 * @hw: pointer to hardware structure
467 * @offset: offset of word in the EEPROM to write
468 * @words: number of words
469 * @data: word(s) write to the EEPROM
471 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
473 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
474 u16 offset, u16 words, u16 *data)
476 s32 status = IXGBE_SUCCESS;
478 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
479 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
481 status = ixgbe_write_eewr_buffer_generic(hw, offset,
483 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
485 status = IXGBE_ERR_SWFW_SYNC;
492 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
494 * This function does not use synchronization for EERD and EEWR. It can
495 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
497 * @hw: pointer to hardware structure
499 * Returns a negative error code on error, or the 16-bit checksum
501 s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
508 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
510 /* Do not use hw->eeprom.ops.read because we do not want to take
511 * the synchronization semaphores here. Instead use
512 * ixgbe_read_eerd_generic
515 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
517 /* Include 0x0 up to IXGBE_EEPROM_CHECKSUM; do not include the
520 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
521 if (ixgbe_read_eerd_generic(hw, i, &word)) {
522 DEBUGOUT("EEPROM read failed\n");
523 return IXGBE_ERR_EEPROM;
528 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
529 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
531 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
532 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
535 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
536 DEBUGOUT("EEPROM read failed\n");
537 return IXGBE_ERR_EEPROM;
540 /* Skip pointer section if the pointer is invalid. */
541 if (pointer == 0xFFFF || pointer == 0 ||
542 pointer >= hw->eeprom.word_size)
545 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
546 DEBUGOUT("EEPROM read failed\n");
547 return IXGBE_ERR_EEPROM;
550 /* Skip pointer section if length is invalid. */
551 if (length == 0xFFFF || length == 0 ||
552 (pointer + length) >= hw->eeprom.word_size)
555 for (j = pointer + 1; j <= pointer + length; j++) {
556 if (ixgbe_read_eerd_generic(hw, j, &word)) {
557 DEBUGOUT("EEPROM read failed\n");
558 return IXGBE_ERR_EEPROM;
564 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
566 return (s32)checksum;
570 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
571 * @hw: pointer to hardware structure
572 * @checksum_val: calculated checksum
574 * Performs checksum calculation and validates the EEPROM checksum. If the
575 * caller does not need checksum_val, the value can be NULL.
577 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
582 u16 read_checksum = 0;
584 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
586 /* Read the first word from the EEPROM. If this times out or fails, do
587 * not continue or we could be in for a very long wait while every
590 status = hw->eeprom.ops.read(hw, 0, &checksum);
592 DEBUGOUT("EEPROM read failed\n");
596 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
597 return IXGBE_ERR_SWFW_SYNC;
599 status = hw->eeprom.ops.calc_checksum(hw);
603 checksum = (u16)(status & 0xffff);
605 /* Do not use hw->eeprom.ops.read because we do not want to take
606 * the synchronization semaphores twice here.
608 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
613 /* Verify read checksum from EEPROM is the same as
614 * calculated checksum
616 if (read_checksum != checksum) {
617 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
618 "Invalid EEPROM checksum");
619 status = IXGBE_ERR_EEPROM_CHECKSUM;
622 /* If the user cares, return the calculated checksum */
624 *checksum_val = checksum;
627 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
633 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
634 * @hw: pointer to hardware structure
636 * After writing EEPROM to shadow RAM using EEWR register, software calculates
637 * checksum and updates the EEPROM and instructs the hardware to update
640 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
645 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
647 /* Read the first word from the EEPROM. If this times out or fails, do
648 * not continue or we could be in for a very long wait while every
651 status = hw->eeprom.ops.read(hw, 0, &checksum);
653 DEBUGOUT("EEPROM read failed\n");
657 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
658 return IXGBE_ERR_SWFW_SYNC;
660 status = hw->eeprom.ops.calc_checksum(hw);
664 checksum = (u16)(status & 0xffff);
666 /* Do not use hw->eeprom.ops.write because we do not want to
667 * take the synchronization semaphores twice here.
669 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
673 status = ixgbe_update_flash_X540(hw);
676 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
682 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
683 * @hw: pointer to hardware structure
685 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
686 * EEPROM from shadow RAM to the flash device.
688 s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
693 DEBUGFUNC("ixgbe_update_flash_X540");
695 status = ixgbe_poll_flash_update_done_X540(hw);
696 if (status == IXGBE_ERR_EEPROM) {
697 DEBUGOUT("Flash update time out\n");
701 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP;
702 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
704 status = ixgbe_poll_flash_update_done_X540(hw);
705 if (status == IXGBE_SUCCESS)
706 DEBUGOUT("Flash update complete\n");
708 DEBUGOUT("Flash update time out\n");
710 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
711 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
713 if (flup & IXGBE_EEC_SEC1VAL) {
714 flup |= IXGBE_EEC_FLUP;
715 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
718 status = ixgbe_poll_flash_update_done_X540(hw);
719 if (status == IXGBE_SUCCESS)
720 DEBUGOUT("Flash update complete\n");
722 DEBUGOUT("Flash update time out\n");
729 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
730 * @hw: pointer to hardware structure
732 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
733 * flash update is done.
735 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
739 s32 status = IXGBE_ERR_EEPROM;
741 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
743 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
744 reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
745 if (reg & IXGBE_EEC_FLUDONE) {
746 status = IXGBE_SUCCESS;
752 if (i == IXGBE_FLUDONE_ATTEMPTS)
753 ERROR_REPORT1(IXGBE_ERROR_POLLING,
754 "Flash update status polling timed out");
760 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
761 * @hw: pointer to hardware structure
762 * @mask: Mask to specify which semaphore to acquire
764 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
765 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
767 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
769 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
770 u32 fwmask = swmask << 5;
771 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
777 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
779 if (swmask & IXGBE_GSSR_EEP_SM)
780 hwmask |= IXGBE_GSSR_FLASH_SM;
782 /* SW only mask doesn't have FW bit pair */
783 if (mask & IXGBE_GSSR_SW_MNG_SM)
784 swmask |= IXGBE_GSSR_SW_MNG_SM;
786 swmask |= swi2c_mask;
787 fwmask |= swi2c_mask << 2;
788 if (hw->mac.type >= ixgbe_mac_X550)
791 for (i = 0; i < timeout; i++) {
792 /* SW NVM semaphore bit is used for access to all
793 * SW_FW_SYNC bits (not just NVM)
795 if (ixgbe_get_swfw_sync_semaphore(hw)) {
796 DEBUGOUT("Failed to get NVM access and register semaphore, returning IXGBE_ERR_SWFW_SYNC\n");
797 return IXGBE_ERR_SWFW_SYNC;
800 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
801 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
803 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw),
805 ixgbe_release_swfw_sync_semaphore(hw);
806 return IXGBE_SUCCESS;
808 /* Firmware currently using resource (fwmask), hardware
809 * currently using resource (hwmask), or other software
810 * thread currently using resource (swmask)
812 ixgbe_release_swfw_sync_semaphore(hw);
816 /* If the resource is not released by the FW/HW the SW can assume that
817 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
818 * of the requested resource(s) while ignoring the corresponding FW/HW
819 * bits in the SW_FW_SYNC register.
821 if (ixgbe_get_swfw_sync_semaphore(hw)) {
822 DEBUGOUT("Failed to get NVM sempahore and register semaphore while forcefully ignoring FW sempahore bit(s) and setting SW semaphore bit(s), returning IXGBE_ERR_SWFW_SYNC\n");
823 return IXGBE_ERR_SWFW_SYNC;
825 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
826 if (swfw_sync & (fwmask | hwmask)) {
828 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
829 ixgbe_release_swfw_sync_semaphore(hw);
831 return IXGBE_SUCCESS;
833 /* If the resource is not released by other SW the SW can assume that
834 * the other SW malfunctions. In that case the SW should clear all SW
835 * flags that it does not own and then repeat the whole process once
838 if (swfw_sync & swmask) {
839 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
840 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
841 IXGBE_GSSR_SW_MNG_SM;
844 rmask |= IXGBE_GSSR_I2C_MASK;
845 ixgbe_release_swfw_sync_X540(hw, rmask);
846 ixgbe_release_swfw_sync_semaphore(hw);
847 DEBUGOUT("Resource not released by other SW, returning IXGBE_ERR_SWFW_SYNC\n");
848 return IXGBE_ERR_SWFW_SYNC;
850 ixgbe_release_swfw_sync_semaphore(hw);
851 DEBUGOUT("Returning error IXGBE_ERR_SWFW_SYNC\n");
853 return IXGBE_ERR_SWFW_SYNC;
857 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
858 * @hw: pointer to hardware structure
859 * @mask: Mask to specify which semaphore to release
861 * Releases the SWFW semaphore through the SW_FW_SYNC register
862 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
864 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
866 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
869 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
871 if (mask & IXGBE_GSSR_I2C_MASK)
872 swmask |= mask & IXGBE_GSSR_I2C_MASK;
873 ixgbe_get_swfw_sync_semaphore(hw);
875 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
876 swfw_sync &= ~swmask;
877 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
879 ixgbe_release_swfw_sync_semaphore(hw);
884 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
885 * @hw: pointer to hardware structure
887 * Sets the hardware semaphores so SW/FW can gain control of shared resources
889 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
891 s32 status = IXGBE_ERR_EEPROM;
896 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
898 /* Get SMBI software semaphore between device drivers first */
899 for (i = 0; i < timeout; i++) {
901 * If the SMBI bit is 0 when we read it, then the bit will be
902 * set and we have the semaphore
904 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
905 if (!(swsm & IXGBE_SWSM_SMBI)) {
906 status = IXGBE_SUCCESS;
912 /* Now get the semaphore between SW/FW through the REGSMP bit */
913 if (status == IXGBE_SUCCESS) {
914 for (i = 0; i < timeout; i++) {
915 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
916 if (!(swsm & IXGBE_SWFW_REGSMP))
923 * Release semaphores and return error if SW NVM semaphore
924 * was not granted because we don't have access to the EEPROM
927 ERROR_REPORT1(IXGBE_ERROR_POLLING,
928 "REGSMP Software NVM semaphore not granted.\n");
929 ixgbe_release_swfw_sync_semaphore(hw);
930 status = IXGBE_ERR_EEPROM;
933 ERROR_REPORT1(IXGBE_ERROR_POLLING,
934 "Software semaphore SMBI between device drivers "
942 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
943 * @hw: pointer to hardware structure
945 * This function clears hardware semaphore bits.
947 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
951 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
953 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
955 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
956 swsm &= ~IXGBE_SWFW_REGSMP;
957 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm);
959 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
960 swsm &= ~IXGBE_SWSM_SMBI;
961 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
963 IXGBE_WRITE_FLUSH(hw);
967 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore
968 * @hw: pointer to hardware structure
970 * This function reset hardware semaphore bits for a semaphore that may
971 * have be left locked due to a catastrophic failure.
973 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
977 /* First try to grab the semaphore but we don't need to bother
978 * looking to see whether we got the lock or not since we do
979 * the same thing regardless of whether we got the lock or not.
980 * We got the lock - we release it.
981 * We timeout trying to get the lock - we force its release.
983 ixgbe_get_swfw_sync_semaphore(hw);
984 ixgbe_release_swfw_sync_semaphore(hw);
986 /* Acquire and release all software resources. */
987 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
988 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
989 IXGBE_GSSR_SW_MNG_SM;
991 rmask |= IXGBE_GSSR_I2C_MASK;
992 ixgbe_acquire_swfw_sync_X540(hw, rmask);
993 ixgbe_release_swfw_sync_X540(hw, rmask);
997 * ixgbe_blink_led_start_X540 - Blink LED based on index.
998 * @hw: pointer to hardware structure
999 * @index: led number to blink
1001 * Devices that implement the version 2 interface:
1004 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
1008 ixgbe_link_speed speed;
1011 DEBUGFUNC("ixgbe_blink_led_start_X540");
1014 return IXGBE_ERR_PARAM;
1017 * Link should be up in order for the blink bit in the LED control
1018 * register to work. Force link and speed in the MAC if link is down.
1019 * This will be reversed when we stop the blinking.
1021 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
1022 if (link_up == FALSE) {
1023 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1024 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
1025 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1027 /* Set the LED to LINK_UP + BLINK. */
1028 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1029 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1030 ledctl_reg |= IXGBE_LED_BLINK(index);
1031 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1032 IXGBE_WRITE_FLUSH(hw);
1034 return IXGBE_SUCCESS;
1038 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
1039 * @hw: pointer to hardware structure
1040 * @index: led number to stop blinking
1042 * Devices that implement the version 2 interface:
1045 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
1051 return IXGBE_ERR_PARAM;
1053 DEBUGFUNC("ixgbe_blink_led_stop_X540");
1055 /* Restore the LED to its default value. */
1056 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1057 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1058 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
1059 ledctl_reg &= ~IXGBE_LED_BLINK(index);
1060 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1062 /* Unforce link and speed in the MAC. */
1063 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1064 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
1065 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1066 IXGBE_WRITE_FLUSH(hw);
1068 return IXGBE_SUCCESS;