1 /******************************************************************************
3 Copyright (c) 2013-2018, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
35 #ifndef _I40E_ADMINQ_CMD_H_
36 #define _I40E_ADMINQ_CMD_H_
38 /* This header file defines the i40e Admin Queue commands and is shared between
39 * i40e Firmware and Software.
41 * This file needs to comply with the Linux Kernel coding style.
45 #define I40E_FW_API_VERSION_MAJOR 0x0001
46 #define I40E_FW_API_VERSION_MINOR_X722 0x0005
47 #define I40E_FW_API_VERSION_MINOR_X710 0x0007
49 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
50 I40E_FW_API_VERSION_MINOR_X710 : \
51 I40E_FW_API_VERSION_MINOR_X722)
53 /* API version 1.7 implements additional link and PHY-specific APIs */
54 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
80 /* Flags sub-structure
81 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
82 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
85 /* command flags and offsets*/
86 #define I40E_AQ_FLAG_DD_SHIFT 0
87 #define I40E_AQ_FLAG_CMP_SHIFT 1
88 #define I40E_AQ_FLAG_ERR_SHIFT 2
89 #define I40E_AQ_FLAG_VFE_SHIFT 3
90 #define I40E_AQ_FLAG_LB_SHIFT 9
91 #define I40E_AQ_FLAG_RD_SHIFT 10
92 #define I40E_AQ_FLAG_VFC_SHIFT 11
93 #define I40E_AQ_FLAG_BUF_SHIFT 12
94 #define I40E_AQ_FLAG_SI_SHIFT 13
95 #define I40E_AQ_FLAG_EI_SHIFT 14
96 #define I40E_AQ_FLAG_FE_SHIFT 15
98 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
99 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
100 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
101 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
102 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
103 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
104 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
105 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
106 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
107 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
108 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
111 enum i40e_admin_queue_err {
112 I40E_AQ_RC_OK = 0, /* success */
113 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
114 I40E_AQ_RC_ENOENT = 2, /* No such element */
115 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
116 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
117 I40E_AQ_RC_EIO = 5, /* I/O error */
118 I40E_AQ_RC_ENXIO = 6, /* No such resource */
119 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
120 I40E_AQ_RC_EAGAIN = 8, /* Try again */
121 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
122 I40E_AQ_RC_EACCES = 10, /* Permission denied */
123 I40E_AQ_RC_EFAULT = 11, /* Bad address */
124 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
125 I40E_AQ_RC_EEXIST = 13, /* object already exists */
126 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
127 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
128 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
129 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
130 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
131 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
132 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
133 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
134 I40E_AQ_RC_EFBIG = 22, /* File too large */
137 /* Admin Queue command opcodes */
138 enum i40e_admin_queue_opc {
140 i40e_aqc_opc_get_version = 0x0001,
141 i40e_aqc_opc_driver_version = 0x0002,
142 i40e_aqc_opc_queue_shutdown = 0x0003,
143 i40e_aqc_opc_set_pf_context = 0x0004,
145 /* resource ownership */
146 i40e_aqc_opc_request_resource = 0x0008,
147 i40e_aqc_opc_release_resource = 0x0009,
149 i40e_aqc_opc_list_func_capabilities = 0x000A,
150 i40e_aqc_opc_list_dev_capabilities = 0x000B,
153 i40e_aqc_opc_set_proxy_config = 0x0104,
154 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
157 i40e_aqc_opc_mac_address_read = 0x0107,
158 i40e_aqc_opc_mac_address_write = 0x0108,
161 i40e_aqc_opc_clear_pxe_mode = 0x0110,
164 i40e_aqc_opc_set_wol_filter = 0x0120,
165 i40e_aqc_opc_get_wake_reason = 0x0121,
166 i40e_aqc_opc_clear_all_wol_filters = 0x025E,
168 /* internal switch commands */
169 i40e_aqc_opc_get_switch_config = 0x0200,
170 i40e_aqc_opc_add_statistics = 0x0201,
171 i40e_aqc_opc_remove_statistics = 0x0202,
172 i40e_aqc_opc_set_port_parameters = 0x0203,
173 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
174 i40e_aqc_opc_set_switch_config = 0x0205,
175 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
176 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
178 i40e_aqc_opc_add_vsi = 0x0210,
179 i40e_aqc_opc_update_vsi_parameters = 0x0211,
180 i40e_aqc_opc_get_vsi_parameters = 0x0212,
182 i40e_aqc_opc_add_pv = 0x0220,
183 i40e_aqc_opc_update_pv_parameters = 0x0221,
184 i40e_aqc_opc_get_pv_parameters = 0x0222,
186 i40e_aqc_opc_add_veb = 0x0230,
187 i40e_aqc_opc_update_veb_parameters = 0x0231,
188 i40e_aqc_opc_get_veb_parameters = 0x0232,
190 i40e_aqc_opc_delete_element = 0x0243,
192 i40e_aqc_opc_add_macvlan = 0x0250,
193 i40e_aqc_opc_remove_macvlan = 0x0251,
194 i40e_aqc_opc_add_vlan = 0x0252,
195 i40e_aqc_opc_remove_vlan = 0x0253,
196 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
197 i40e_aqc_opc_add_tag = 0x0255,
198 i40e_aqc_opc_remove_tag = 0x0256,
199 i40e_aqc_opc_add_multicast_etag = 0x0257,
200 i40e_aqc_opc_remove_multicast_etag = 0x0258,
201 i40e_aqc_opc_update_tag = 0x0259,
202 i40e_aqc_opc_add_control_packet_filter = 0x025A,
203 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
204 i40e_aqc_opc_add_cloud_filters = 0x025C,
205 i40e_aqc_opc_remove_cloud_filters = 0x025D,
206 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
208 i40e_aqc_opc_add_mirror_rule = 0x0260,
209 i40e_aqc_opc_delete_mirror_rule = 0x0261,
212 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
213 i40e_aqc_opc_dcb_updated = 0x0302,
214 i40e_aqc_opc_set_dcb_parameters = 0x0303,
217 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
218 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
219 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
220 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
221 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
222 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
224 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
225 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
226 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
227 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
228 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
229 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
230 i40e_aqc_opc_query_port_ets_config = 0x0419,
231 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
232 i40e_aqc_opc_suspend_port_tx = 0x041B,
233 i40e_aqc_opc_resume_port_tx = 0x041C,
234 i40e_aqc_opc_configure_partition_bw = 0x041D,
236 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
237 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
240 i40e_aqc_opc_get_phy_abilities = 0x0600,
241 i40e_aqc_opc_set_phy_config = 0x0601,
242 i40e_aqc_opc_set_mac_config = 0x0603,
243 i40e_aqc_opc_set_link_restart_an = 0x0605,
244 i40e_aqc_opc_get_link_status = 0x0607,
245 i40e_aqc_opc_set_phy_int_mask = 0x0613,
246 i40e_aqc_opc_get_local_advt_reg = 0x0614,
247 i40e_aqc_opc_set_local_advt_reg = 0x0615,
248 i40e_aqc_opc_get_partner_advt = 0x0616,
249 i40e_aqc_opc_set_lb_modes = 0x0618,
250 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
251 i40e_aqc_opc_set_phy_debug = 0x0622,
252 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
253 i40e_aqc_opc_run_phy_activity = 0x0626,
254 i40e_aqc_opc_set_phy_register = 0x0628,
255 i40e_aqc_opc_get_phy_register = 0x0629,
258 i40e_aqc_opc_nvm_read = 0x0701,
259 i40e_aqc_opc_nvm_erase = 0x0702,
260 i40e_aqc_opc_nvm_update = 0x0703,
261 i40e_aqc_opc_nvm_config_read = 0x0704,
262 i40e_aqc_opc_nvm_config_write = 0x0705,
263 i40e_aqc_opc_nvm_progress = 0x0706,
264 i40e_aqc_opc_oem_post_update = 0x0720,
265 i40e_aqc_opc_thermal_sensor = 0x0721,
267 /* virtualization commands */
268 i40e_aqc_opc_send_msg_to_pf = 0x0801,
269 i40e_aqc_opc_send_msg_to_vf = 0x0802,
270 i40e_aqc_opc_send_msg_to_peer = 0x0803,
272 /* alternate structure */
273 i40e_aqc_opc_alternate_write = 0x0900,
274 i40e_aqc_opc_alternate_write_indirect = 0x0901,
275 i40e_aqc_opc_alternate_read = 0x0902,
276 i40e_aqc_opc_alternate_read_indirect = 0x0903,
277 i40e_aqc_opc_alternate_write_done = 0x0904,
278 i40e_aqc_opc_alternate_set_mode = 0x0905,
279 i40e_aqc_opc_alternate_clear_port = 0x0906,
282 i40e_aqc_opc_lldp_get_mib = 0x0A00,
283 i40e_aqc_opc_lldp_update_mib = 0x0A01,
284 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
285 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
286 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
287 i40e_aqc_opc_lldp_stop = 0x0A05,
288 i40e_aqc_opc_lldp_start = 0x0A06,
289 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
290 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
291 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
293 /* Tunnel commands */
294 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
295 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
296 i40e_aqc_opc_set_rss_key = 0x0B02,
297 i40e_aqc_opc_set_rss_lut = 0x0B03,
298 i40e_aqc_opc_get_rss_key = 0x0B04,
299 i40e_aqc_opc_get_rss_lut = 0x0B05,
302 i40e_aqc_opc_event_lan_overflow = 0x1001,
305 i40e_aqc_opc_oem_parameter_change = 0xFE00,
306 i40e_aqc_opc_oem_device_status_change = 0xFE01,
307 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
308 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
311 i40e_aqc_opc_debug_read_reg = 0xFF03,
312 i40e_aqc_opc_debug_write_reg = 0xFF04,
313 i40e_aqc_opc_debug_modify_reg = 0xFF07,
314 i40e_aqc_opc_debug_dump_internals = 0xFF08,
317 /* command structures and indirect data structures */
319 /* Structure naming conventions:
320 * - no suffix for direct command descriptor structures
321 * - _data for indirect sent data
322 * - _resp for indirect return data (data which is both will use _data)
323 * - _completion for direct return data
324 * - _element_ for repeated elements (may also be _data or _resp)
326 * Command structures are expected to overlay the params.raw member of the basic
327 * descriptor, and as such cannot exceed 16 bytes in length.
330 /* This macro is used to generate a compilation error if a structure
331 * is not exactly the correct length. It gives a divide by zero error if the
332 * structure is not of the correct size, otherwise it creates an enum that is
335 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
336 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
338 /* This macro is used extensively to ensure that command structures are 16
339 * bytes in length as they have to map to the raw array of that size.
341 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
343 /* internal (0x00XX) commands */
345 /* Get version (direct 0x0001) */
346 struct i40e_aqc_get_version {
355 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
357 /* Send driver version (indirect 0x0002) */
358 struct i40e_aqc_driver_version {
362 u8 driver_subbuild_ver;
368 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
370 /* Queue Shutdown (direct 0x0003) */
371 struct i40e_aqc_queue_shutdown {
372 __le32 driver_unloading;
373 #define I40E_AQ_DRIVER_UNLOADING 0x1
377 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
379 /* Set PF context (0x0004, direct) */
380 struct i40e_aqc_set_pf_context {
385 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
387 /* Request resource ownership (direct 0x0008)
388 * Release resource ownership (direct 0x0009)
390 #define I40E_AQ_RESOURCE_NVM 1
391 #define I40E_AQ_RESOURCE_SDP 2
392 #define I40E_AQ_RESOURCE_ACCESS_READ 1
393 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
394 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
395 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
397 struct i40e_aqc_request_resource {
401 __le32 resource_number;
405 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
407 /* Get function capabilities (indirect 0x000A)
408 * Get device capabilities (indirect 0x000B)
410 struct i40e_aqc_list_capabilites {
412 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
420 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
422 struct i40e_aqc_list_capabilities_element_resp {
434 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
435 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
436 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
437 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
438 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
439 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
440 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
441 #define I40E_AQ_CAP_ID_SRIOV 0x0012
442 #define I40E_AQ_CAP_ID_VF 0x0013
443 #define I40E_AQ_CAP_ID_VMDQ 0x0014
444 #define I40E_AQ_CAP_ID_8021QBG 0x0015
445 #define I40E_AQ_CAP_ID_8021QBR 0x0016
446 #define I40E_AQ_CAP_ID_VSI 0x0017
447 #define I40E_AQ_CAP_ID_DCB 0x0018
448 #define I40E_AQ_CAP_ID_FCOE 0x0021
449 #define I40E_AQ_CAP_ID_ISCSI 0x0022
450 #define I40E_AQ_CAP_ID_RSS 0x0040
451 #define I40E_AQ_CAP_ID_RXQ 0x0041
452 #define I40E_AQ_CAP_ID_TXQ 0x0042
453 #define I40E_AQ_CAP_ID_MSIX 0x0043
454 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
455 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
456 #define I40E_AQ_CAP_ID_1588 0x0046
457 #define I40E_AQ_CAP_ID_IWARP 0x0051
458 #define I40E_AQ_CAP_ID_LED 0x0061
459 #define I40E_AQ_CAP_ID_SDP 0x0062
460 #define I40E_AQ_CAP_ID_MDIO 0x0063
461 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
462 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
463 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
464 #define I40E_AQ_CAP_ID_CEM 0x00F2
466 /* Set CPPM Configuration (direct 0x0103) */
467 struct i40e_aqc_cppm_configuration {
468 __le16 command_flags;
469 #define I40E_AQ_CPPM_EN_LTRC 0x0800
470 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
471 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
472 #define I40E_AQ_CPPM_EN_HPTC 0x4000
473 #define I40E_AQ_CPPM_EN_DMARC 0x8000
482 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
484 /* Set ARP Proxy command / response (indirect 0x0104) */
485 struct i40e_aqc_arp_proxy_data {
486 __le16 command_flags;
487 #define I40E_AQ_ARP_INIT_IPV4 0x0800
488 #define I40E_AQ_ARP_UNSUP_CTL 0x1000
489 #define I40E_AQ_ARP_ENA 0x2000
490 #define I40E_AQ_ARP_ADD_IPV4 0x4000
491 #define I40E_AQ_ARP_DEL_IPV4 0x8000
493 __le32 enabled_offloads;
494 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
495 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
501 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
503 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
504 struct i40e_aqc_ns_proxy_data {
505 __le16 table_idx_mac_addr_0;
506 __le16 table_idx_mac_addr_1;
507 __le16 table_idx_ipv6_0;
508 __le16 table_idx_ipv6_1;
510 #define I40E_AQ_NS_PROXY_ADD_0 0x0001
511 #define I40E_AQ_NS_PROXY_DEL_0 0x0002
512 #define I40E_AQ_NS_PROXY_ADD_1 0x0004
513 #define I40E_AQ_NS_PROXY_DEL_1 0x0008
514 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
515 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
516 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
517 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
518 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
519 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
520 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
521 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
522 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
525 u8 local_mac_addr[6];
526 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
530 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
532 /* Manage LAA Command (0x0106) - obsolete */
533 struct i40e_aqc_mng_laa {
534 __le16 command_flags;
535 #define I40E_AQ_LAA_FLAG_WR 0x8000
542 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
544 /* Manage MAC Address Read Command (indirect 0x0107) */
545 struct i40e_aqc_mac_address_read {
546 __le16 command_flags;
547 #define I40E_AQC_LAN_ADDR_VALID 0x10
548 #define I40E_AQC_SAN_ADDR_VALID 0x20
549 #define I40E_AQC_PORT_ADDR_VALID 0x40
550 #define I40E_AQC_WOL_ADDR_VALID 0x80
551 #define I40E_AQC_MC_MAG_EN_VALID 0x100
552 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200
553 #define I40E_AQC_ADDR_VALID_MASK 0x3F0
559 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
561 struct i40e_aqc_mac_address_read_data {
568 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
570 /* Manage MAC Address Write Command (0x0108) */
571 struct i40e_aqc_mac_address_write {
572 __le16 command_flags;
573 #define I40E_AQC_MC_MAG_EN 0x0100
574 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
575 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
576 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
577 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
578 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
579 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
586 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
588 /* PXE commands (0x011x) */
590 /* Clear PXE Command and response (direct 0x0110) */
591 struct i40e_aqc_clear_pxe {
596 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
598 /* Set WoL Filter (0x0120) */
600 struct i40e_aqc_set_wol_filter {
602 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
603 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
604 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
605 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
607 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
608 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
609 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
611 #define I40E_AQC_SET_WOL_FILTER 0x8000
612 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
613 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000
614 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
615 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
617 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
618 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
624 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
626 struct i40e_aqc_set_wol_filter_data {
631 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
633 /* Get Wake Reason (0x0121) */
635 struct i40e_aqc_get_wake_reason_completion {
638 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
639 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
640 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
641 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
642 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
643 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
647 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
649 /* Switch configuration commands (0x02xx) */
651 /* Used by many indirect commands that only pass an seid and a buffer in the
654 struct i40e_aqc_switch_seid {
661 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
663 /* Get Switch Configuration command (indirect 0x0200)
664 * uses i40e_aqc_switch_seid for the descriptor
666 struct i40e_aqc_get_switch_config_header_resp {
672 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
674 struct i40e_aqc_switch_config_element_resp {
676 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
677 #define I40E_AQ_SW_ELEM_TYPE_PF 2
678 #define I40E_AQ_SW_ELEM_TYPE_VF 3
679 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
680 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
681 #define I40E_AQ_SW_ELEM_TYPE_PV 16
682 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
683 #define I40E_AQ_SW_ELEM_TYPE_PA 18
684 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
686 #define I40E_AQ_SW_ELEM_REV_1 1
689 __le16 downlink_seid;
692 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
693 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
694 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
699 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
701 /* Get Switch Configuration (indirect 0x0200)
702 * an array of elements are returned in the response buffer
703 * the first in the array is the header, remainder are elements
705 struct i40e_aqc_get_switch_config_resp {
706 struct i40e_aqc_get_switch_config_header_resp header;
707 struct i40e_aqc_switch_config_element_resp element[1];
710 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
712 /* Add Statistics (direct 0x0201)
713 * Remove Statistics (direct 0x0202)
715 struct i40e_aqc_add_remove_statistics {
722 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
724 /* Set Port Parameters command (direct 0x0203) */
725 struct i40e_aqc_set_port_parameters {
726 __le16 command_flags;
727 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
728 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
729 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
730 __le16 bad_frame_vsi;
731 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
732 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
733 __le16 default_seid; /* reserved for command */
737 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
739 /* Get Switch Resource Allocation (indirect 0x0204) */
740 struct i40e_aqc_get_switch_resource_alloc {
741 u8 num_entries; /* reserved for command */
747 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
749 /* expect an array of these structs in the response buffer */
750 struct i40e_aqc_switch_resource_alloc_element_resp {
752 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
753 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
754 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
755 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
756 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
757 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
758 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
759 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
760 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
761 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
762 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
763 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
764 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
765 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
766 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
767 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
768 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
769 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
770 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
775 __le16 total_unalloced;
779 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
781 /* Set Switch Configuration (direct 0x0205) */
782 struct i40e_aqc_set_switch_config {
784 /* flags used for both fields below */
785 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
786 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
787 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004
789 /* The ethertype in switch_tag is dropped on ingress and used
790 * internally by the switch. Set this to zero for the default
791 * of 0x88a8 (802.1ad). Should be zero for firmware API
792 * versions lower than 1.7.
795 /* The ethertypes in first_tag and second_tag are used to
796 * match the outer and inner VLAN tags (respectively) when HW
797 * double VLAN tagging is enabled via the set port parameters
798 * AQ command. Otherwise these are both ignored. Set them to
799 * zero for their defaults of 0x8100 (802.1Q). Should be zero
800 * for firmware API versions lower than 1.7.
804 /* Next byte is split into following:
805 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0
806 * Bit 6 : 0 : Destination Port, 1: source port
811 * 3: Both TCP and UDP
814 * 1: L4 port only mode
815 * 2: non-tunneled mode
818 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80
820 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40
822 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00
823 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10
824 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20
825 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30
827 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00
828 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01
829 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02
830 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03
835 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
837 /* Read Receive control registers (direct 0x0206)
838 * Write Receive control registers (direct 0x0207)
839 * used for accessing Rx control registers that can be
840 * slow and need special handling when under high Rx load
842 struct i40e_aqc_rx_ctl_reg_read_write {
849 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
851 /* Add VSI (indirect 0x0210)
852 * this indirect command uses struct i40e_aqc_vsi_properties_data
853 * as the indirect buffer (128 bytes)
855 * Update VSI (indirect 0x211)
856 * uses the same data structure as Add VSI
858 * Get VSI (indirect 0x0212)
859 * uses the same completion and data structure as Add VSI
861 struct i40e_aqc_add_get_update_vsi {
864 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
865 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
866 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
871 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
872 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
873 #define I40E_AQ_VSI_TYPE_VF 0x0
874 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
875 #define I40E_AQ_VSI_TYPE_PF 0x2
876 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
877 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
882 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
884 struct i40e_aqc_add_get_update_vsi_completion {
893 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
895 struct i40e_aqc_vsi_properties_data {
896 /* first 96 byte are written by SW */
897 __le16 valid_sections;
898 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
899 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
900 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
901 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
902 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
903 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
904 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
905 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
906 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
907 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
909 __le16 switch_id; /* 12bit id combined with flags below */
910 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
911 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
912 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
913 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
914 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
916 /* security section */
918 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
919 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
920 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
923 __le16 pvid; /* VLANS include priority bits */
926 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
927 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
928 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
929 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
930 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
931 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
932 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
933 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
934 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
935 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
936 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
937 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
938 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
939 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
940 u8 pvlan_reserved[3];
941 /* ingress egress up sections */
942 __le32 ingress_table; /* bitmap, 3 bits per up */
943 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
944 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
945 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
946 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
947 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
948 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
949 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
950 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
951 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
952 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
953 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
954 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
955 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
956 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
957 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
958 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
959 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
960 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
961 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
962 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
963 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
964 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
965 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
966 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
967 __le32 egress_table; /* same defines as for ingress table */
968 /* cascaded PV section */
971 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
972 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
973 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
974 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
975 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
976 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
977 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
978 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
979 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
981 /* queue mapping section */
982 __le16 mapping_flags;
983 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
984 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
985 __le16 queue_mapping[16];
986 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
987 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
988 __le16 tc_mapping[8];
989 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
990 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
991 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
992 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
993 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
994 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
995 /* queueing option section */
996 u8 queueing_opt_flags;
997 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
998 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
999 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
1000 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
1001 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
1002 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
1003 u8 queueing_opt_reserved[3];
1004 /* scheduler section */
1007 /* outer up section */
1008 __le32 outer_up_table; /* same structure and defines as ingress tbl */
1010 /* last 32 bytes are written by FW */
1011 __le16 qs_handle[8];
1012 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
1013 __le16 stat_counter_idx;
1015 u8 resp_reserved[12];
1018 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
1020 /* Add Port Virtualizer (direct 0x0220)
1021 * also used for update PV (direct 0x0221) but only flags are used
1022 * (IS_CTRL_PORT only works on add PV)
1024 struct i40e_aqc_add_update_pv {
1025 __le16 command_flags;
1026 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
1027 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
1028 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
1029 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
1031 __le16 connected_seid;
1035 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
1037 struct i40e_aqc_add_update_pv_completion {
1038 /* reserved for update; for add also encodes error if rc == ENOSPC */
1040 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
1041 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
1042 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
1043 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
1047 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
1049 /* Get PV Params (direct 0x0222)
1050 * uses i40e_aqc_switch_seid for the descriptor
1053 struct i40e_aqc_get_pv_params_completion {
1055 __le16 default_stag;
1056 __le16 pv_flags; /* same flags as add_pv */
1057 #define I40E_AQC_GET_PV_PV_TYPE 0x1
1058 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
1059 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
1061 __le16 default_port_seid;
1064 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
1066 /* Add VEB (direct 0x0230) */
1067 struct i40e_aqc_add_veb {
1069 __le16 downlink_seid;
1071 #define I40E_AQC_ADD_VEB_FLOATING 0x1
1072 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1073 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1074 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1075 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1076 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1077 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1078 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1083 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1085 struct i40e_aqc_add_veb_completion {
1088 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1090 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1091 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1092 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1093 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1094 __le16 statistic_index;
1099 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1101 /* Get VEB Parameters (direct 0x0232)
1102 * uses i40e_aqc_switch_seid for the descriptor
1104 struct i40e_aqc_get_veb_parameters_completion {
1107 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1108 __le16 statistic_index;
1114 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1116 /* Delete Element (direct 0x0243)
1117 * uses the generic i40e_aqc_switch_seid
1120 /* Add MAC-VLAN (indirect 0x0250) */
1122 /* used for the command for most vlan commands */
1123 struct i40e_aqc_macvlan {
1124 __le16 num_addresses;
1126 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1127 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1128 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1129 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1134 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1136 /* indirect data for command and response */
1137 struct i40e_aqc_add_macvlan_element_data {
1141 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1142 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1143 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1144 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1145 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1146 __le16 queue_number;
1147 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1148 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1149 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1150 /* response section */
1152 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1153 #define I40E_AQC_MM_HASH_MATCH 0x02
1154 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1158 struct i40e_aqc_add_remove_macvlan_completion {
1159 __le16 perfect_mac_used;
1160 __le16 perfect_mac_free;
1161 __le16 unicast_hash_free;
1162 __le16 multicast_hash_free;
1167 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1169 /* Remove MAC-VLAN (indirect 0x0251)
1170 * uses i40e_aqc_macvlan for the descriptor
1171 * data points to an array of num_addresses of elements
1174 struct i40e_aqc_remove_macvlan_element_data {
1178 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1179 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1180 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1181 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1185 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1186 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1187 u8 reply_reserved[3];
1190 /* Add VLAN (indirect 0x0252)
1191 * Remove VLAN (indirect 0x0253)
1192 * use the generic i40e_aqc_macvlan for the command
1194 struct i40e_aqc_add_remove_vlan_element_data {
1197 /* flags for add VLAN */
1198 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1199 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1200 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1201 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1202 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1203 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1204 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1205 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1206 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1207 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1208 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1209 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1210 /* flags for remove VLAN */
1211 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1214 /* flags for add VLAN */
1215 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1216 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1217 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1218 /* flags for remove VLAN */
1219 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1220 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1224 struct i40e_aqc_add_remove_vlan_completion {
1232 /* Set VSI Promiscuous Modes (direct 0x0254) */
1233 struct i40e_aqc_set_vsi_promiscuous_modes {
1234 __le16 promiscuous_flags;
1236 /* flags used for both fields above */
1237 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1238 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1239 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1240 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1241 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1242 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1244 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1246 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1247 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1251 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1253 /* Add S/E-tag command (direct 0x0255)
1254 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1256 struct i40e_aqc_add_tag {
1258 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1260 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1261 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1262 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1264 __le16 queue_number;
1268 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1270 struct i40e_aqc_add_remove_tag_completion {
1276 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1278 /* Remove S/E-tag command (direct 0x0256)
1279 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1281 struct i40e_aqc_remove_tag {
1283 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1284 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1285 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1290 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1292 /* Add multicast E-Tag (direct 0x0257)
1293 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1294 * and no external data
1296 struct i40e_aqc_add_remove_mcast_etag {
1299 u8 num_unicast_etags;
1301 __le32 addr_high; /* address of array of 2-byte s-tags */
1305 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1307 struct i40e_aqc_add_remove_mcast_etag_completion {
1309 __le16 mcast_etags_used;
1310 __le16 mcast_etags_free;
1316 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1318 /* Update S/E-Tag (direct 0x0259) */
1319 struct i40e_aqc_update_tag {
1321 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1322 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1323 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1329 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1331 struct i40e_aqc_update_tag_completion {
1337 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1339 /* Add Control Packet filter (direct 0x025A)
1340 * Remove Control Packet filter (direct 0x025B)
1341 * uses the i40e_aqc_add_oveb_cloud,
1342 * and the generic direct completion structure
1344 struct i40e_aqc_add_remove_control_packet_filter {
1348 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1349 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1350 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1351 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1352 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1354 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1355 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1356 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1361 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1363 struct i40e_aqc_add_remove_control_packet_filter_completion {
1364 __le16 mac_etype_used;
1366 __le16 mac_etype_free;
1371 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1373 /* Add Cloud filters (indirect 0x025C)
1374 * Remove Cloud filters (indirect 0x025D)
1375 * uses the i40e_aqc_add_remove_cloud_filters,
1376 * and the generic indirect completion structure
1378 struct i40e_aqc_add_remove_cloud_filters {
1382 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1383 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1384 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1390 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1392 struct i40e_aqc_add_remove_cloud_filters_element_data {
1406 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1407 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1408 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1409 /* 0x0000 reserved */
1410 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1411 /* 0x0002 reserved */
1412 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1413 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1414 /* 0x0005 reserved */
1415 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1416 /* 0x0007 reserved */
1417 /* 0x0008 reserved */
1418 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1419 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1420 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1421 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1423 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1424 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1425 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1426 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1427 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1429 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1430 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1431 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1432 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1433 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1434 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1435 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1436 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1438 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1439 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1440 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1444 __le16 queue_number;
1445 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1446 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1447 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1449 /* response section */
1450 u8 allocation_result;
1451 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1452 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1453 u8 response_reserved[7];
1456 struct i40e_aqc_remove_cloud_filters_completion {
1457 __le16 perfect_ovlan_used;
1458 __le16 perfect_ovlan_free;
1465 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1467 /* Add Mirror Rule (indirect or direct 0x0260)
1468 * Delete Mirror Rule (indirect or direct 0x0261)
1469 * note: some rule types (4,5) do not use an external buffer.
1470 * take care to set the flags correctly.
1472 struct i40e_aqc_add_delete_mirror_rule {
1475 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1476 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1477 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1478 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1479 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1480 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1481 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1482 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1484 __le16 destination; /* VSI for add, rule id for delete */
1485 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1489 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1491 struct i40e_aqc_add_delete_mirror_rule_completion {
1493 __le16 rule_id; /* only used on add */
1494 __le16 mirror_rules_used;
1495 __le16 mirror_rules_free;
1500 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1504 /* PFC Ignore (direct 0x0301)
1505 * the command and response use the same descriptor structure
1507 struct i40e_aqc_pfc_ignore {
1509 u8 command_flags; /* unused on response */
1510 #define I40E_AQC_PFC_IGNORE_SET 0x80
1511 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1515 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1517 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1518 * with no parameters
1521 /* TX scheduler 0x04xx */
1523 /* Almost all the indirect commands use
1524 * this generic struct to pass the SEID in param0
1526 struct i40e_aqc_tx_sched_ind {
1533 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1535 /* Several commands respond with a set of queue set handles */
1536 struct i40e_aqc_qs_handles_resp {
1537 __le16 qs_handles[8];
1540 /* Configure VSI BW limits (direct 0x0400) */
1541 struct i40e_aqc_configure_vsi_bw_limit {
1546 u8 max_credit; /* 0-3, limit = 2^max */
1550 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1552 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1553 * responds with i40e_aqc_qs_handles_resp
1555 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1558 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1560 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1561 __le16 tc_bw_max[2];
1565 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1567 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1568 * responds with i40e_aqc_qs_handles_resp
1570 struct i40e_aqc_configure_vsi_tc_bw_data {
1573 u8 tc_bw_credits[8];
1575 __le16 qs_handles[8];
1578 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1580 /* Query vsi bw configuration (indirect 0x0408) */
1581 struct i40e_aqc_query_vsi_bw_config_resp {
1583 u8 tc_suspended_bits;
1585 __le16 qs_handles[8];
1587 __le16 port_bw_limit;
1589 u8 max_bw; /* 0-3, limit = 2^max */
1593 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1595 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1596 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1599 u8 share_credits[8];
1602 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1603 __le16 tc_bw_max[2];
1606 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1608 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1609 struct i40e_aqc_configure_switching_comp_bw_limit {
1614 u8 max_bw; /* 0-3, limit = 2^max */
1618 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1620 /* Enable Physical Port ETS (indirect 0x0413)
1621 * Modify Physical Port ETS (indirect 0x0414)
1622 * Disable Physical Port ETS (indirect 0x0415)
1624 struct i40e_aqc_configure_switching_comp_ets_data {
1628 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1629 u8 tc_strict_priority_flags;
1631 u8 tc_bw_share_credits[8];
1635 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1637 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1638 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1641 __le16 tc_bw_credit[8];
1643 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1644 __le16 tc_bw_max[2];
1648 I40E_CHECK_STRUCT_LEN(0x40,
1649 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1651 /* Configure Switching Component Bandwidth Allocation per Tc
1654 struct i40e_aqc_configure_switching_comp_bw_config_data {
1657 u8 absolute_credits; /* bool */
1658 u8 tc_bw_share_credits[8];
1662 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1664 /* Query Switching Component Configuration (indirect 0x0418) */
1665 struct i40e_aqc_query_switching_comp_ets_config_resp {
1668 __le16 port_bw_limit;
1670 u8 tc_bw_max; /* 0-3, limit = 2^max */
1674 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1676 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1677 struct i40e_aqc_query_port_ets_config_resp {
1681 u8 tc_strict_priority_bits;
1683 u8 tc_bw_share_credits[8];
1684 __le16 tc_bw_limits[8];
1686 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1687 __le16 tc_bw_max[2];
1691 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1693 /* Query Switching Component Bandwidth Allocation per Traffic Type
1696 struct i40e_aqc_query_switching_comp_bw_config_resp {
1699 u8 absolute_credits_enable; /* bool */
1700 u8 tc_bw_share_credits[8];
1701 __le16 tc_bw_limits[8];
1703 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1704 __le16 tc_bw_max[2];
1707 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1709 /* Suspend/resume port TX traffic
1710 * (direct 0x041B and 0x041C) uses the generic SEID struct
1713 /* Configure partition BW
1716 struct i40e_aqc_configure_partition_bw_data {
1717 __le16 pf_valid_bits;
1718 u8 min_bw[16]; /* guaranteed bandwidth */
1719 u8 max_bw[16]; /* bandwidth limit */
1722 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1724 /* Get and set the active HMC resource profile and status.
1725 * (direct 0x0500) and (direct 0x0501)
1727 struct i40e_aq_get_set_hmc_resource_profile {
1733 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1735 enum i40e_aq_hmc_profile {
1736 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1737 I40E_HMC_PROFILE_DEFAULT = 1,
1738 I40E_HMC_PROFILE_FAVOR_VF = 2,
1739 I40E_HMC_PROFILE_EQUAL = 3,
1742 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1744 /* set in param0 for get phy abilities to report qualified modules */
1745 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1746 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1748 enum i40e_aq_phy_type {
1749 I40E_PHY_TYPE_SGMII = 0x0,
1750 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1751 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1752 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1753 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1754 I40E_PHY_TYPE_XAUI = 0x5,
1755 I40E_PHY_TYPE_XFI = 0x6,
1756 I40E_PHY_TYPE_SFI = 0x7,
1757 I40E_PHY_TYPE_XLAUI = 0x8,
1758 I40E_PHY_TYPE_XLPPI = 0x9,
1759 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1760 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1761 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1762 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1763 I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
1764 I40E_PHY_TYPE_UNSUPPORTED = 0xF,
1765 I40E_PHY_TYPE_100BASE_TX = 0x11,
1766 I40E_PHY_TYPE_1000BASE_T = 0x12,
1767 I40E_PHY_TYPE_10GBASE_T = 0x13,
1768 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1769 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1770 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1771 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1772 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1773 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1774 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1775 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1776 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1777 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1778 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1779 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1780 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1781 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1782 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1783 I40E_PHY_TYPE_25GBASE_AOC = 0x23,
1784 I40E_PHY_TYPE_25GBASE_ACC = 0x24,
1786 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
1787 I40E_PHY_TYPE_EMPTY = 0xFE,
1788 I40E_PHY_TYPE_DEFAULT = 0xFF,
1791 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
1792 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
1793 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
1794 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1795 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
1796 BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1797 BIT_ULL(I40E_PHY_TYPE_XFI) | \
1798 BIT_ULL(I40E_PHY_TYPE_SFI) | \
1799 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1800 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1801 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
1802 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
1803 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
1804 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
1805 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
1806 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
1807 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
1808 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
1809 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
1810 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
1811 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
1812 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
1813 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
1814 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
1815 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
1816 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
1817 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
1818 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
1819 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
1820 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
1821 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
1822 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
1823 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
1824 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
1825 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
1826 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC))
1828 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1829 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1830 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1831 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1832 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1833 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1835 enum i40e_aq_link_speed {
1836 I40E_LINK_SPEED_UNKNOWN = 0,
1837 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1838 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1839 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1840 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1841 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT),
1842 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT),
1845 struct i40e_aqc_module_desc {
1853 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1855 struct i40e_aq_get_phy_abilities_resp {
1856 __le32 phy_type; /* bitmap using the above enum for offsets */
1857 u8 link_speed; /* bitmap using the above enum bit patterns */
1859 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1860 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1861 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1862 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1863 #define I40E_AQ_PHY_AN_ENABLED 0x10
1864 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1865 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
1866 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
1867 __le16 eee_capability;
1868 #define I40E_AQ_EEE_100BASE_TX 0x0002
1869 #define I40E_AQ_EEE_1000BASE_T 0x0004
1870 #define I40E_AQ_EEE_10GBASE_T 0x0008
1871 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1872 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1873 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1876 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1878 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01
1879 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02
1880 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1881 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1882 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10
1883 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20
1884 u8 fec_cfg_curr_mod_ext_info;
1885 #define I40E_AQ_ENABLE_FEC_KR 0x01
1886 #define I40E_AQ_ENABLE_FEC_RS 0x02
1887 #define I40E_AQ_REQUEST_FEC_KR 0x04
1888 #define I40E_AQ_REQUEST_FEC_RS 0x08
1889 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
1891 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0
1892 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5
1897 u8 qualified_module_count;
1898 #define I40E_AQ_PHY_MAX_QMS 16
1899 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1902 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1904 /* Set PHY Config (direct 0x0601) */
1905 struct i40e_aq_set_phy_config { /* same bits as above in all */
1909 /* bits 0-2 use the values from get_phy_abilities_resp */
1910 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1911 #define I40E_AQ_PHY_ENABLE_AN 0x10
1912 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1913 __le16 eee_capability;
1918 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
1919 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
1920 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
1921 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
1922 #define I40E_AQ_SET_FEC_AUTO BIT(4)
1923 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1924 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1928 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1930 /* Set MAC Config command data structure (direct 0x0603) */
1931 struct i40e_aq_set_mac_config {
1932 __le16 max_frame_size;
1934 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1935 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1936 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1937 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1938 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1939 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1940 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1941 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1942 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1943 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1944 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1945 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1946 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1947 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1948 u8 tx_timer_priority; /* bitmap */
1949 __le16 tx_timer_value;
1950 __le16 fc_refresh_threshold;
1954 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1956 /* Restart Auto-Negotiation (direct 0x605) */
1957 struct i40e_aqc_set_link_restart_an {
1959 #define I40E_AQ_PHY_RESTART_AN 0x02
1960 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1964 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1966 /* Get Link Status cmd & response data structure (direct 0x0607) */
1967 struct i40e_aqc_get_link_status {
1968 __le16 command_flags; /* only field set on command */
1969 #define I40E_AQ_LSE_MASK 0x3
1970 #define I40E_AQ_LSE_NOP 0x0
1971 #define I40E_AQ_LSE_DISABLE 0x2
1972 #define I40E_AQ_LSE_ENABLE 0x3
1973 /* only response uses this flag */
1974 #define I40E_AQ_LSE_IS_ENABLED 0x1
1975 u8 phy_type; /* i40e_aq_phy_type */
1976 u8 link_speed; /* i40e_aq_link_speed */
1978 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1979 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1980 #define I40E_AQ_LINK_FAULT 0x02
1981 #define I40E_AQ_LINK_FAULT_TX 0x04
1982 #define I40E_AQ_LINK_FAULT_RX 0x08
1983 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1984 #define I40E_AQ_LINK_UP_PORT 0x20
1985 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1986 #define I40E_AQ_SIGNAL_DETECT 0x80
1988 #define I40E_AQ_AN_COMPLETED 0x01
1989 #define I40E_AQ_LP_AN_ABILITY 0x02
1990 #define I40E_AQ_PD_FAULT 0x04
1991 #define I40E_AQ_FEC_EN 0x08
1992 #define I40E_AQ_PHY_LOW_POWER 0x10
1993 #define I40E_AQ_LINK_PAUSE_TX 0x20
1994 #define I40E_AQ_LINK_PAUSE_RX 0x40
1995 #define I40E_AQ_QUALIFIED_MODULE 0x80
1997 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1998 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1999 #define I40E_AQ_LINK_TX_SHIFT 0x02
2000 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
2001 #define I40E_AQ_LINK_TX_ACTIVE 0x00
2002 #define I40E_AQ_LINK_TX_DRAINED 0x01
2003 #define I40E_AQ_LINK_TX_FLUSHED 0x03
2004 #define I40E_AQ_LINK_FORCED_40G 0x10
2005 /* 25G Error Codes */
2006 #define I40E_AQ_25G_NO_ERR 0X00
2007 #define I40E_AQ_25G_NOT_PRESENT 0X01
2008 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
2009 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
2010 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
2011 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
2012 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
2013 /* Since firmware API 1.7 loopback field keeps power class info as well */
2014 #define I40E_AQ_LOOPBACK_MASK 0x07
2015 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6
2016 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB)
2017 __le16 max_frame_size;
2019 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
2020 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
2021 #define I40E_AQ_CONFIG_CRC_ENA 0x04
2022 #define I40E_AQ_CONFIG_PACING_MASK 0x78
2026 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
2027 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
2028 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
2029 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
2030 #define I40E_AQ_PWR_CLASS_MASK 0x03
2040 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
2042 /* Set event mask command (direct 0x613) */
2043 struct i40e_aqc_set_phy_int_mask {
2046 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
2047 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
2048 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
2049 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
2050 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
2051 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
2052 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
2053 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
2054 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
2058 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
2060 /* Get Local AN advt register (direct 0x0614)
2061 * Set Local AN advt register (direct 0x0615)
2062 * Get Link Partner AN advt register (direct 0x0616)
2064 struct i40e_aqc_an_advt_reg {
2065 __le32 local_an_reg0;
2066 __le16 local_an_reg1;
2070 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
2072 /* Set Loopback mode (0x0618) */
2073 struct i40e_aqc_set_lb_mode {
2075 #define I40E_AQ_LB_NONE 0
2076 #define I40E_AQ_LB_MAC 1
2077 #define I40E_AQ_LB_SERDES 2
2078 #define I40E_AQ_LB_PHY_INT 3
2079 #define I40E_AQ_LB_PHY_EXT 4
2080 #define I40E_AQ_LB_CPVL_PCS 5
2081 #define I40E_AQ_LB_CPVL_EXT 6
2082 #define I40E_AQ_LB_PHY_LOCAL 0x01
2083 #define I40E_AQ_LB_PHY_REMOTE 0x02
2084 #define I40E_AQ_LB_MAC_LOCAL 0x04
2086 #define I40E_AQ_LB_LOCAL 0
2087 #define I40E_AQ_LB_FAR 0x01
2089 #define I40E_AQ_LB_SPEED_NONE 0
2090 #define I40E_AQ_LB_SPEED_1G 1
2091 #define I40E_AQ_LB_SPEED_10G 2
2092 #define I40E_AQ_LB_SPEED_40G 3
2093 #define I40E_AQ_LB_SPEED_20G 4
2098 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
2100 /* Set PHY Debug command (0x0622) */
2101 struct i40e_aqc_set_phy_debug {
2103 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
2104 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
2105 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
2106 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2107 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
2108 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
2109 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
2110 /* Disable link manageability on a single port */
2111 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
2112 /* Disable link manageability on all ports needs both bits 4 and 5 */
2113 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
2117 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
2119 enum i40e_aq_phy_reg_type {
2120 I40E_AQC_PHY_REG_INTERNAL = 0x1,
2121 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
2122 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2125 /* Run PHY Activity (0x0626) */
2126 struct i40e_aqc_run_phy_activity {
2135 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
2137 /* Set PHY Register command (0x0628) */
2138 /* Get PHY Register command (0x0629) */
2139 struct i40e_aqc_phy_register_access {
2141 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0
2142 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
2143 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
2151 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
2153 /* NVM Read command (indirect 0x0701)
2154 * NVM Erase commands (direct 0x0702)
2155 * NVM Update commands (indirect 0x0703)
2157 struct i40e_aqc_nvm_update {
2159 #define I40E_AQ_NVM_LAST_CMD 0x01
2160 #define I40E_AQ_NVM_FLASH_ONLY 0x80
2161 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
2162 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03
2163 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
2164 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
2172 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
2174 /* NVM Config Read (indirect 0x0704) */
2175 struct i40e_aqc_nvm_config_read {
2177 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2178 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2179 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2180 __le16 element_count;
2181 __le16 element_id; /* Feature/field ID */
2182 __le16 element_id_msw; /* MSWord of field ID */
2183 __le32 address_high;
2187 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
2189 /* NVM Config Write (indirect 0x0705) */
2190 struct i40e_aqc_nvm_config_write {
2192 __le16 element_count;
2194 __le32 address_high;
2198 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
2200 /* Used for 0x0704 as well as for 0x0705 commands */
2201 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2202 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2203 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2204 #define I40E_AQ_ANVM_FEATURE 0
2205 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
2206 struct i40e_aqc_nvm_config_data_feature {
2208 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2209 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2210 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2211 __le16 feature_options;
2212 __le16 feature_selection;
2215 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2217 struct i40e_aqc_nvm_config_data_immediate_field {
2220 __le16 field_options;
2224 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2226 /* OEM Post Update (indirect 0x0720)
2227 * no command data struct used
2229 struct i40e_aqc_nvm_oem_post_update {
2230 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2235 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2237 struct i40e_aqc_nvm_oem_post_update_buffer {
2244 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2246 /* Thermal Sensor (indirect 0x0721)
2247 * read or set thermal sensor configs and values
2248 * takes a sensor and command specific data buffer, not detailed here
2250 struct i40e_aqc_thermal_sensor {
2252 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2253 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2254 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2260 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2262 /* Send to PF command (indirect 0x0801) id is only used by PF
2263 * Send to VF command (indirect 0x0802) id is only used by PF
2264 * Send to Peer PF command (indirect 0x0803)
2266 struct i40e_aqc_pf_vf_message {
2273 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2275 /* Alternate structure */
2277 /* Direct write (direct 0x0900)
2278 * Direct read (direct 0x0902)
2280 struct i40e_aqc_alternate_write {
2287 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2289 /* Indirect write (indirect 0x0901)
2290 * Indirect read (indirect 0x0903)
2293 struct i40e_aqc_alternate_ind_write {
2300 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2302 /* Done alternate write (direct 0x0904)
2305 struct i40e_aqc_alternate_write_done {
2307 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2308 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2309 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2310 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2314 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2316 /* Set OEM mode (direct 0x0905) */
2317 struct i40e_aqc_alternate_set_mode {
2319 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2320 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2324 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2326 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2328 /* async events 0x10xx */
2330 /* Lan Queue Overflow Event (direct, 0x1001) */
2331 struct i40e_aqc_lan_overflow {
2332 __le32 prtdcb_rupto;
2337 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2339 /* Get LLDP MIB (indirect 0x0A00) */
2340 struct i40e_aqc_lldp_get_mib {
2343 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2344 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2345 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2346 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2347 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2348 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2349 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2350 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2351 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2352 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2353 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2361 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2363 /* Configure LLDP MIB Change Event (direct 0x0A01)
2364 * also used for the event (with type in the command field)
2366 struct i40e_aqc_lldp_update_mib {
2368 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2369 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2375 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2377 /* Add LLDP TLV (indirect 0x0A02)
2378 * Delete LLDP TLV (indirect 0x0A04)
2380 struct i40e_aqc_lldp_add_tlv {
2381 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2389 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2391 /* Update LLDP TLV (indirect 0x0A03) */
2392 struct i40e_aqc_lldp_update_tlv {
2393 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2402 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2404 /* Stop LLDP (direct 0x0A05) */
2405 struct i40e_aqc_lldp_stop {
2407 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2408 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2412 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2414 /* Start LLDP (direct 0x0A06) */
2416 struct i40e_aqc_lldp_start {
2418 #define I40E_AQ_LLDP_AGENT_START 0x1
2422 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2424 /* Set DCB (direct 0x0303) */
2425 struct i40e_aqc_set_dcb_parameters {
2427 #define I40E_AQ_DCB_SET_AGENT 0x1
2428 #define I40E_DCB_VALID 0x1
2433 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
2435 /* Get CEE DCBX Oper Config (0x0A07)
2436 * uses the generic descriptor struct
2437 * returns below as indirect response
2440 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2441 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2442 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2443 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2444 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2445 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2447 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2448 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2449 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2450 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2451 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2452 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2453 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2454 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2455 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2456 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2457 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2458 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2460 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2461 * word boundary layout issues, which the Linux compilers silently deal
2462 * with by adding padding, making the actual struct larger than designed.
2463 * However, the FW compiler for the NIC is less lenient and complains
2464 * about the struct. Hence, the struct defined here has an extra byte in
2465 * fields reserved3 and reserved4 to directly acknowledge that padding,
2466 * and the new length is used in the length check macro.
2468 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2476 __le16 oper_app_prio;
2481 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2483 struct i40e_aqc_get_cee_dcb_cfg_resp {
2488 __le16 oper_app_prio;
2493 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2495 /* Set Local LLDP MIB (indirect 0x0A08)
2496 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2498 struct i40e_aqc_lldp_set_local_mib {
2499 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2500 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2501 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2502 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2503 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2504 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2505 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2506 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2511 __le32 address_high;
2515 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2517 struct i40e_aqc_lldp_set_local_mib_resp {
2518 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01
2523 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);
2525 /* Stop/Start LLDP Agent (direct 0x0A09)
2526 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2528 struct i40e_aqc_lldp_stop_start_specific_agent {
2529 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2530 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2531 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2536 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2538 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2539 struct i40e_aqc_add_udp_tunnel {
2543 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2544 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2545 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2546 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2550 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2552 struct i40e_aqc_add_udp_tunnel_completion {
2554 u8 filter_entry_index;
2556 #define I40E_AQC_SINGLE_PF 0x0
2557 #define I40E_AQC_MULTIPLE_PFS 0x1
2562 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2564 /* remove UDP Tunnel command (0x0B01) */
2565 struct i40e_aqc_remove_udp_tunnel {
2567 u8 index; /* 0 to 15 */
2571 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2573 struct i40e_aqc_del_udp_tunnel_completion {
2575 u8 index; /* 0 to 15 */
2577 u8 total_filters_used;
2581 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2583 struct i40e_aqc_get_set_rss_key {
2584 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2585 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2586 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2587 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2594 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2596 struct i40e_aqc_get_set_rss_key_data {
2597 u8 standard_rss_key[0x28];
2598 u8 extended_hash_key[0xc];
2601 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2603 struct i40e_aqc_get_set_rss_lut {
2604 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2605 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2606 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2607 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2609 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2610 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2611 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2613 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2614 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2621 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2623 /* tunnel key structure 0x0B10 */
2625 struct i40e_aqc_tunnel_key_structure {
2628 u8 key1_len; /* 0 to 15 */
2629 u8 key2_len; /* 0 to 15 */
2631 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2632 /* response flags */
2633 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2634 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2635 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2636 u8 network_key_index;
2637 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2638 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2639 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2640 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2644 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2646 /* OEM mode commands (direct 0xFE0x) */
2647 struct i40e_aqc_oem_param_change {
2649 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2650 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2651 #define I40E_AQ_OEM_PARAM_MAC 2
2652 __le32 param_value1;
2653 __le16 param_value2;
2657 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2659 struct i40e_aqc_oem_state_change {
2661 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2662 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2666 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2668 /* Initialize OCSD (0xFE02, direct) */
2669 struct i40e_aqc_opc_oem_ocsd_initialize {
2672 __le32 ocsd_memory_block_addr_high;
2673 __le32 ocsd_memory_block_addr_low;
2674 __le32 requested_update_interval;
2677 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2679 /* Initialize OCBB (0xFE03, direct) */
2680 struct i40e_aqc_opc_oem_ocbb_initialize {
2683 __le32 ocbb_memory_block_addr_high;
2684 __le32 ocbb_memory_block_addr_low;
2688 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2690 /* debug commands */
2692 /* get device id (0xFF00) uses the generic structure */
2694 /* set test more (0xFF01, internal) */
2696 struct i40e_acq_set_test_mode {
2698 #define I40E_AQ_TEST_PARTIAL 0
2699 #define I40E_AQ_TEST_FULL 1
2700 #define I40E_AQ_TEST_NVM 2
2703 #define I40E_AQ_TEST_OPEN 0
2704 #define I40E_AQ_TEST_CLOSE 1
2705 #define I40E_AQ_TEST_INC 2
2707 __le32 address_high;
2711 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2713 /* Debug Read Register command (0xFF03)
2714 * Debug Write Register command (0xFF04)
2716 struct i40e_aqc_debug_reg_read_write {
2723 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2725 /* Scatter/gather Reg Read (indirect 0xFF05)
2726 * Scatter/gather Reg Write (indirect 0xFF06)
2729 /* i40e_aq_desc is used for the command */
2730 struct i40e_aqc_debug_reg_sg_element_data {
2735 /* Debug Modify register (direct 0xFF07) */
2736 struct i40e_aqc_debug_modify_reg {
2743 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2745 /* dump internal data (0xFF08, indirect) */
2747 #define I40E_AQ_CLUSTER_ID_AUX 0
2748 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2749 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2750 #define I40E_AQ_CLUSTER_ID_HMC 3
2751 #define I40E_AQ_CLUSTER_ID_MAC0 4
2752 #define I40E_AQ_CLUSTER_ID_MAC1 5
2753 #define I40E_AQ_CLUSTER_ID_MAC2 6
2754 #define I40E_AQ_CLUSTER_ID_MAC3 7
2755 #define I40E_AQ_CLUSTER_ID_DCB 8
2756 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2757 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2758 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2760 struct i40e_aqc_debug_dump_internals {
2765 __le32 address_high;
2769 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2771 struct i40e_aqc_debug_modify_internals {
2773 u8 cluster_specific_params[7];
2774 __le32 address_high;
2778 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2780 #endif /* _I40E_ADMINQ_CMD_H_ */