sys/dev/ixl/i40e_common.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2013-2015, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #include "i40e_type.h"
  36 #include "i40e_adminq.h"
  37 #include "i40e_prototype.h"
  38 #include "i40e_virtchnl.h"
  39
  40
  41 /**
  42  * i40e_set_mac_type - Sets MAC type
  43  * @hw: pointer to the HW structure
  44  *
  45  * This function sets the mac type of the adapter based on the
  46  * vendor ID and device ID stored in the hw structure.
  47  **/
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 {
  50         enum i40e_status_code status = I40E_SUCCESS;
  51
  52         DEBUGFUNC("i40e_set_mac_type\n");
  53
  54         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  55                 switch (hw->device_id) {
  56                 case I40E_DEV_ID_SFP_XL710:
  57                 case I40E_DEV_ID_QEMU:
  58                 case I40E_DEV_ID_KX_B:
  59                 case I40E_DEV_ID_KX_C:
  60                 case I40E_DEV_ID_QSFP_A:
  61                 case I40E_DEV_ID_QSFP_B:
  62                 case I40E_DEV_ID_QSFP_C:
  63                 case I40E_DEV_ID_10G_BASE_T:
  64                 case I40E_DEV_ID_10G_BASE_T4:
  65                 case I40E_DEV_ID_20G_KR2:
  66                 case I40E_DEV_ID_20G_KR2_A:
  67                 case I40E_DEV_ID_25G_B:
  68                 case I40E_DEV_ID_25G_SFP28:
  69                         hw->mac.type = I40E_MAC_XL710;
  70                         break;
  71                 case I40E_DEV_ID_X722_A0:
  72                 case I40E_DEV_ID_KX_X722:
  73                 case I40E_DEV_ID_QSFP_X722:
  74                 case I40E_DEV_ID_SFP_X722:
  75                 case I40E_DEV_ID_1G_BASE_T_X722:
  76                 case I40E_DEV_ID_10G_BASE_T_X722:
  77                 case I40E_DEV_ID_SFP_I_X722:
  78                         hw->mac.type = I40E_MAC_X722;
  79                         break;
  80                 case I40E_DEV_ID_X722_VF:
  81                 case I40E_DEV_ID_X722_VF_HV:
  82                 case I40E_DEV_ID_X722_A0_VF:
  83                         hw->mac.type = I40E_MAC_X722_VF;
  84                         break;
  85                 case I40E_DEV_ID_VF:
  86                 case I40E_DEV_ID_VF_HV:
  87                         hw->mac.type = I40E_MAC_VF;
  88                         break;
  89                 default:
  90                         hw->mac.type = I40E_MAC_GENERIC;
  91                         break;
  92                 }
  93         } else {
  94                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  95         }
  96
  97         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  98                   hw->mac.type, status);
  99         return status;
 100 }
 101
 102 /**
 103  * i40e_aq_str - convert AQ err code to a string
 104  * @hw: pointer to the HW structure
 105  * @aq_err: the AQ error code to convert
 106  **/
 107 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 108 {
 109         switch (aq_err) {
 110         case I40E_AQ_RC_OK:
 111                 return "OK";
 112         case I40E_AQ_RC_EPERM:
 113                 return "I40E_AQ_RC_EPERM";
 114         case I40E_AQ_RC_ENOENT:
 115                 return "I40E_AQ_RC_ENOENT";
 116         case I40E_AQ_RC_ESRCH:
 117                 return "I40E_AQ_RC_ESRCH";
 118         case I40E_AQ_RC_EINTR:
 119                 return "I40E_AQ_RC_EINTR";
 120         case I40E_AQ_RC_EIO:
 121                 return "I40E_AQ_RC_EIO";
 122         case I40E_AQ_RC_ENXIO:
 123                 return "I40E_AQ_RC_ENXIO";
 124         case I40E_AQ_RC_E2BIG:
 125                 return "I40E_AQ_RC_E2BIG";
 126         case I40E_AQ_RC_EAGAIN:
 127                 return "I40E_AQ_RC_EAGAIN";
 128         case I40E_AQ_RC_ENOMEM:
 129                 return "I40E_AQ_RC_ENOMEM";
 130         case I40E_AQ_RC_EACCES:
 131                 return "I40E_AQ_RC_EACCES";
 132         case I40E_AQ_RC_EFAULT:
 133                 return "I40E_AQ_RC_EFAULT";
 134         case I40E_AQ_RC_EBUSY:
 135                 return "I40E_AQ_RC_EBUSY";
 136         case I40E_AQ_RC_EEXIST:
 137                 return "I40E_AQ_RC_EEXIST";
 138         case I40E_AQ_RC_EINVAL:
 139                 return "I40E_AQ_RC_EINVAL";
 140         case I40E_AQ_RC_ENOTTY:
 141                 return "I40E_AQ_RC_ENOTTY";
 142         case I40E_AQ_RC_ENOSPC:
 143                 return "I40E_AQ_RC_ENOSPC";
 144         case I40E_AQ_RC_ENOSYS:
 145                 return "I40E_AQ_RC_ENOSYS";
 146         case I40E_AQ_RC_ERANGE:
 147                 return "I40E_AQ_RC_ERANGE";
 148         case I40E_AQ_RC_EFLUSHED:
 149                 return "I40E_AQ_RC_EFLUSHED";
 150         case I40E_AQ_RC_BAD_ADDR:
 151                 return "I40E_AQ_RC_BAD_ADDR";
 152         case I40E_AQ_RC_EMODE:
 153                 return "I40E_AQ_RC_EMODE";
 154         case I40E_AQ_RC_EFBIG:
 155                 return "I40E_AQ_RC_EFBIG";
 156         }
 157
 158         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 159         return hw->err_str;
 160 }
 161
 162 /**
 163  * i40e_stat_str - convert status err code to a string
 164  * @hw: pointer to the HW structure
 165  * @stat_err: the status error code to convert
 166  **/
 167 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 168 {
 169         switch (stat_err) {
 170         case I40E_SUCCESS:
 171                 return "OK";
 172         case I40E_ERR_NVM:
 173                 return "I40E_ERR_NVM";
 174         case I40E_ERR_NVM_CHECKSUM:
 175                 return "I40E_ERR_NVM_CHECKSUM";
 176         case I40E_ERR_PHY:
 177                 return "I40E_ERR_PHY";
 178         case I40E_ERR_CONFIG:
 179                 return "I40E_ERR_CONFIG";
 180         case I40E_ERR_PARAM:
 181                 return "I40E_ERR_PARAM";
 182         case I40E_ERR_MAC_TYPE:
 183                 return "I40E_ERR_MAC_TYPE";
 184         case I40E_ERR_UNKNOWN_PHY:
 185                 return "I40E_ERR_UNKNOWN_PHY";
 186         case I40E_ERR_LINK_SETUP:
 187                 return "I40E_ERR_LINK_SETUP";
 188         case I40E_ERR_ADAPTER_STOPPED:
 189                 return "I40E_ERR_ADAPTER_STOPPED";
 190         case I40E_ERR_INVALID_MAC_ADDR:
 191                 return "I40E_ERR_INVALID_MAC_ADDR";
 192         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 193                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 194         case I40E_ERR_MASTER_REQUESTS_PENDING:
 195                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 196         case I40E_ERR_INVALID_LINK_SETTINGS:
 197                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 198         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 199                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 200         case I40E_ERR_RESET_FAILED:
 201                 return "I40E_ERR_RESET_FAILED";
 202         case I40E_ERR_SWFW_SYNC:
 203                 return "I40E_ERR_SWFW_SYNC";
 204         case I40E_ERR_NO_AVAILABLE_VSI:
 205                 return "I40E_ERR_NO_AVAILABLE_VSI";
 206         case I40E_ERR_NO_MEMORY:
 207                 return "I40E_ERR_NO_MEMORY";
 208         case I40E_ERR_BAD_PTR:
 209                 return "I40E_ERR_BAD_PTR";
 210         case I40E_ERR_RING_FULL:
 211                 return "I40E_ERR_RING_FULL";
 212         case I40E_ERR_INVALID_PD_ID:
 213                 return "I40E_ERR_INVALID_PD_ID";
 214         case I40E_ERR_INVALID_QP_ID:
 215                 return "I40E_ERR_INVALID_QP_ID";
 216         case I40E_ERR_INVALID_CQ_ID:
 217                 return "I40E_ERR_INVALID_CQ_ID";
 218         case I40E_ERR_INVALID_CEQ_ID:
 219                 return "I40E_ERR_INVALID_CEQ_ID";
 220         case I40E_ERR_INVALID_AEQ_ID:
 221                 return "I40E_ERR_INVALID_AEQ_ID";
 222         case I40E_ERR_INVALID_SIZE:
 223                 return "I40E_ERR_INVALID_SIZE";
 224         case I40E_ERR_INVALID_ARP_INDEX:
 225                 return "I40E_ERR_INVALID_ARP_INDEX";
 226         case I40E_ERR_INVALID_FPM_FUNC_ID:
 227                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 228         case I40E_ERR_QP_INVALID_MSG_SIZE:
 229                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 230         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 231                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 232         case I40E_ERR_INVALID_FRAG_COUNT:
 233                 return "I40E_ERR_INVALID_FRAG_COUNT";
 234         case I40E_ERR_QUEUE_EMPTY:
 235                 return "I40E_ERR_QUEUE_EMPTY";
 236         case I40E_ERR_INVALID_ALIGNMENT:
 237                 return "I40E_ERR_INVALID_ALIGNMENT";
 238         case I40E_ERR_FLUSHED_QUEUE:
 239                 return "I40E_ERR_FLUSHED_QUEUE";
 240         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 241                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 242         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 243                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 244         case I40E_ERR_TIMEOUT:
 245                 return "I40E_ERR_TIMEOUT";
 246         case I40E_ERR_OPCODE_MISMATCH:
 247                 return "I40E_ERR_OPCODE_MISMATCH";
 248         case I40E_ERR_CQP_COMPL_ERROR:
 249                 return "I40E_ERR_CQP_COMPL_ERROR";
 250         case I40E_ERR_INVALID_VF_ID:
 251                 return "I40E_ERR_INVALID_VF_ID";
 252         case I40E_ERR_INVALID_HMCFN_ID:
 253                 return "I40E_ERR_INVALID_HMCFN_ID";
 254         case I40E_ERR_BACKING_PAGE_ERROR:
 255                 return "I40E_ERR_BACKING_PAGE_ERROR";
 256         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 257                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 258         case I40E_ERR_INVALID_PBLE_INDEX:
 259                 return "I40E_ERR_INVALID_PBLE_INDEX";
 260         case I40E_ERR_INVALID_SD_INDEX:
 261                 return "I40E_ERR_INVALID_SD_INDEX";
 262         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 263                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 264         case I40E_ERR_INVALID_SD_TYPE:
 265                 return "I40E_ERR_INVALID_SD_TYPE";
 266         case I40E_ERR_MEMCPY_FAILED:
 267                 return "I40E_ERR_MEMCPY_FAILED";
 268         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 269                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 270         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 271                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 272         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 273                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 274         case I40E_ERR_SRQ_ENABLED:
 275                 return "I40E_ERR_SRQ_ENABLED";
 276         case I40E_ERR_ADMIN_QUEUE_ERROR:
 277                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 278         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 279                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 280         case I40E_ERR_BUF_TOO_SHORT:
 281                 return "I40E_ERR_BUF_TOO_SHORT";
 282         case I40E_ERR_ADMIN_QUEUE_FULL:
 283                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 284         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 285                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 286         case I40E_ERR_BAD_IWARP_CQE:
 287                 return "I40E_ERR_BAD_IWARP_CQE";
 288         case I40E_ERR_NVM_BLANK_MODE:
 289                 return "I40E_ERR_NVM_BLANK_MODE";
 290         case I40E_ERR_NOT_IMPLEMENTED:
 291                 return "I40E_ERR_NOT_IMPLEMENTED";
 292         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 293                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 294         case I40E_ERR_DIAG_TEST_FAILED:
 295                 return "I40E_ERR_DIAG_TEST_FAILED";
 296         case I40E_ERR_NOT_READY:
 297                 return "I40E_ERR_NOT_READY";
 298         case I40E_NOT_SUPPORTED:
 299                 return "I40E_NOT_SUPPORTED";
 300         case I40E_ERR_FIRMWARE_API_VERSION:
 301                 return "I40E_ERR_FIRMWARE_API_VERSION";
 302         }
 303
 304         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 305         return hw->err_str;
 306 }
 307
 308 /**
 309  * i40e_debug_aq
 310  * @hw: debug mask related to admin queue
 311  * @mask: debug mask
 312  * @desc: pointer to admin queue descriptor
 313  * @buffer: pointer to command buffer
 314  * @buf_len: max length of buffer
 315  *
 316  * Dumps debug log about adminq command with descriptor contents.
 317  **/
 318 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 319                    void *buffer, u16 buf_len)
 320 {
 321         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 322         u16 len = LE16_TO_CPU(aq_desc->datalen);
 323         u8 *buf = (u8 *)buffer;
 324         u16 i = 0;
 325
 326         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 327                 return;
 328
 329         i40e_debug(hw, mask,
 330                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 331                    LE16_TO_CPU(aq_desc->opcode),
 332                    LE16_TO_CPU(aq_desc->flags),
 333                    LE16_TO_CPU(aq_desc->datalen),
 334                    LE16_TO_CPU(aq_desc->retval));
 335         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 336                    LE32_TO_CPU(aq_desc->cookie_high),
 337                    LE32_TO_CPU(aq_desc->cookie_low));
 338         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 339                    LE32_TO_CPU(aq_desc->params.internal.param0),
 340                    LE32_TO_CPU(aq_desc->params.internal.param1));
 341         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 342                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 343                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 344
 345         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 346                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 347                 if (buf_len < len)
 348                         len = buf_len;
 349                 /* write the full 16-byte chunks */
 350                 for (i = 0; i < (len - 16); i += 16)
 351                         i40e_debug(hw, mask,
 352                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 353                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 354                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 355                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 356                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 357                 /* the most we could have left is 16 bytes, pad with zeros */
 358                 if (i < len) {
 359                         char d_buf[16];
 360                         int j, i_sav;
 361
 362                         i_sav = i;
 363                         memset(d_buf, 0, sizeof(d_buf));
 364                         for (j = 0; i < len; j++, i++)
 365                                 d_buf[j] = buf[i];
 366                         i40e_debug(hw, mask,
 367                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 368                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 369                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 370                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 371                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 372                 }
 373         }
 374 }
 375
 376 /**
 377  * i40e_check_asq_alive
 378  * @hw: pointer to the hw struct
 379  *
 380  * Returns TRUE if Queue is enabled else FALSE.
 381  **/
 382 bool i40e_check_asq_alive(struct i40e_hw *hw)
 383 {
 384         if (hw->aq.asq.len)
 385                 if (!i40e_is_vf(hw))
 386                         return !!(rd32(hw, hw->aq.asq.len) &
 387                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 388                 if (i40e_is_vf(hw))
 389                         return !!(rd32(hw, hw->aq.asq.len) &
 390                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 391         return FALSE;
 392 }
 393
 394 /**
 395  * i40e_aq_queue_shutdown
 396  * @hw: pointer to the hw struct
 397  * @unloading: is the driver unloading itself
 398  *
 399  * Tell the Firmware that we're shutting down the AdminQ and whether
 400  * or not the driver is unloading as well.
 401  **/
 402 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 403                                              bool unloading)
 404 {
 405         struct i40e_aq_desc desc;
 406         struct i40e_aqc_queue_shutdown *cmd =
 407                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 408         enum i40e_status_code status;
 409
 410         i40e_fill_default_direct_cmd_desc(&desc,
 411                                           i40e_aqc_opc_queue_shutdown);
 412
 413         if (unloading)
 414                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 415         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 416
 417         return status;
 418 }
 419
 420 /**
 421  * i40e_aq_get_set_rss_lut
 422  * @hw: pointer to the hardware structure
 423  * @vsi_id: vsi fw index
 424  * @pf_lut: for PF table set TRUE, for VSI table set FALSE
 425  * @lut: pointer to the lut buffer provided by the caller
 426  * @lut_size: size of the lut buffer
 427  * @set: set TRUE to set the table, FALSE to get the table
 428  *
 429  * Internal function to get or set RSS look up table
 430  **/
 431 static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 432                                                      u16 vsi_id, bool pf_lut,
 433                                                      u8 *lut, u16 lut_size,
 434                                                      bool set)
 435 {
 436         enum i40e_status_code status;
 437         struct i40e_aq_desc desc;
 438         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 439                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 440
 441         if (set)
 442                 i40e_fill_default_direct_cmd_desc(&desc,
 443                                                   i40e_aqc_opc_set_rss_lut);
 444         else
 445                 i40e_fill_default_direct_cmd_desc(&desc,
 446                                                   i40e_aqc_opc_get_rss_lut);
 447
 448         /* Indirect command */
 449         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 450         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 451
 452         cmd_resp->vsi_id =
 453                         CPU_TO_LE16((u16)((vsi_id <<
 454                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 455                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 456         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 457
 458         if (pf_lut)
 459                 cmd_resp->flags |= CPU_TO_LE16((u16)
 460                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 461                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 462                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 463         else
 464                 cmd_resp->flags |= CPU_TO_LE16((u16)
 465                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 466                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 467                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 468
 469         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 470
 471         return status;
 472 }
 473
 474 /**
 475  * i40e_aq_get_rss_lut
 476  * @hw: pointer to the hardware structure
 477  * @vsi_id: vsi fw index
 478  * @pf_lut: for PF table set TRUE, for VSI table set FALSE
 479  * @lut: pointer to the lut buffer provided by the caller
 480  * @lut_size: size of the lut buffer
 481  *
 482  * get the RSS lookup table, PF or VSI type
 483  **/
 484 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 485                                           bool pf_lut, u8 *lut, u16 lut_size)
 486 {
 487         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 488                                        FALSE);
 489 }
 490
 491 /**
 492  * i40e_aq_set_rss_lut
 493  * @hw: pointer to the hardware structure
 494  * @vsi_id: vsi fw index
 495  * @pf_lut: for PF table set TRUE, for VSI table set FALSE
 496  * @lut: pointer to the lut buffer provided by the caller
 497  * @lut_size: size of the lut buffer
 498  *
 499  * set the RSS lookup table, PF or VSI type
 500  **/
 501 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 502                                           bool pf_lut, u8 *lut, u16 lut_size)
 503 {
 504         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE);
 505 }
 506
 507 /**
 508  * i40e_aq_get_set_rss_key
 509  * @hw: pointer to the hw struct
 510  * @vsi_id: vsi fw index
 511  * @key: pointer to key info struct
 512  * @set: set TRUE to set the key, FALSE to get the key
 513  *
 514  * get the RSS key per VSI
 515  **/
 516 static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 517                                       u16 vsi_id,
 518                                       struct i40e_aqc_get_set_rss_key_data *key,
 519                                       bool set)
 520 {
 521         enum i40e_status_code status;
 522         struct i40e_aq_desc desc;
 523         struct i40e_aqc_get_set_rss_key *cmd_resp =
 524                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 525         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 526
 527         if (set)
 528                 i40e_fill_default_direct_cmd_desc(&desc,
 529                                                   i40e_aqc_opc_set_rss_key);
 530         else
 531                 i40e_fill_default_direct_cmd_desc(&desc,
 532                                                   i40e_aqc_opc_get_rss_key);
 533
 534         /* Indirect command */
 535         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 536         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 537
 538         cmd_resp->vsi_id =
 539                         CPU_TO_LE16((u16)((vsi_id <<
 540                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 541                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 542         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 543
 544         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 545
 546         return status;
 547 }
 548
 549 /**
 550  * i40e_aq_get_rss_key
 551  * @hw: pointer to the hw struct
 552  * @vsi_id: vsi fw index
 553  * @key: pointer to key info struct
 554  *
 555  **/
 556 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 557                                       u16 vsi_id,
 558                                       struct i40e_aqc_get_set_rss_key_data *key)
 559 {
 560         return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE);
 561 }
 562
 563 /**
 564  * i40e_aq_set_rss_key
 565  * @hw: pointer to the hw struct
 566  * @vsi_id: vsi fw index
 567  * @key: pointer to key info struct
 568  *
 569  * set the RSS key per VSI
 570  **/
 571 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 572                                       u16 vsi_id,
 573                                       struct i40e_aqc_get_set_rss_key_data *key)
 574 {
 575         return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE);
 576 }
 577
 578 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 579  * hardware to a bit-field that can be used by SW to more easily determine the
 580  * packet type.
 581  *
 582  * Macros are used to shorten the table lines and make this table human
 583  * readable.
 584  *
 585  * We store the PTYPE in the top byte of the bit field - this is just so that
 586  * we can check that the table doesn't have a row missing, as the index into
 587  * the table should be the PTYPE.
 588  *
 589  * Typical work flow:
 590  *
 591  * IF NOT i40e_ptype_lookup[ptype].known
 592  * THEN
 593  *      Packet is unknown
 594  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 595  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 596  * ELSE
 597  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 598  * ENDIF
 599  */
 600
 601 /* macro to make the table lines short */
 602 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 603         {       PTYPE, \
 604                 1, \
 605                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 606                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 607                 I40E_RX_PTYPE_##OUTER_FRAG, \
 608                 I40E_RX_PTYPE_TUNNEL_##T, \
 609                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 610                 I40E_RX_PTYPE_##TEF, \
 611                 I40E_RX_PTYPE_INNER_PROT_##I, \
 612                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 613
 614 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 615                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 616
 617 /* shorter macros makes the table fit but are terse */
 618 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 619 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 620 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 621
 622 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 623 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 624         /* L2 Packet types */
 625         I40E_PTT_UNUSED_ENTRY(0),
 626         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 627         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 628         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 629         I40E_PTT_UNUSED_ENTRY(4),
 630         I40E_PTT_UNUSED_ENTRY(5),
 631         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 632         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 633         I40E_PTT_UNUSED_ENTRY(8),
 634         I40E_PTT_UNUSED_ENTRY(9),
 635         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 636         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 637         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 638         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 639         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 640         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 641         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 642         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 643         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 644         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 645         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 646         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 647
 648         /* Non Tunneled IPv4 */
 649         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 650         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 651         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 652         I40E_PTT_UNUSED_ENTRY(25),
 653         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 654         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 655         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 656
 657         /* IPv4 --> IPv4 */
 658         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 659         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 660         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 661         I40E_PTT_UNUSED_ENTRY(32),
 662         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 663         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 664         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 665
 666         /* IPv4 --> IPv6 */
 667         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 668         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 669         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 670         I40E_PTT_UNUSED_ENTRY(39),
 671         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 672         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 673         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 674
 675         /* IPv4 --> GRE/NAT */
 676         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 677
 678         /* IPv4 --> GRE/NAT --> IPv4 */
 679         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 680         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 681         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 682         I40E_PTT_UNUSED_ENTRY(47),
 683         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 684         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 685         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 686
 687         /* IPv4 --> GRE/NAT --> IPv6 */
 688         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 689         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 690         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 691         I40E_PTT_UNUSED_ENTRY(54),
 692         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 693         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 694         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 695
 696         /* IPv4 --> GRE/NAT --> MAC */
 697         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 698
 699         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 700         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 701         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 702         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 703         I40E_PTT_UNUSED_ENTRY(62),
 704         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 705         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 706         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 707
 708         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 709         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 710         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 711         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 712         I40E_PTT_UNUSED_ENTRY(69),
 713         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 714         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 715         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 716
 717         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 718         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 719
 720         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 721         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 722         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 723         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 724         I40E_PTT_UNUSED_ENTRY(77),
 725         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 726         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 727         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 728
 729         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 730         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 731         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 732         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 733         I40E_PTT_UNUSED_ENTRY(84),
 734         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 735         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 736         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 737
 738         /* Non Tunneled IPv6 */
 739         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 740         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 741         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 742         I40E_PTT_UNUSED_ENTRY(91),
 743         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 744         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 745         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 746
 747         /* IPv6 --> IPv4 */
 748         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 749         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 750         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 751         I40E_PTT_UNUSED_ENTRY(98),
 752         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 753         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 754         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 755
 756         /* IPv6 --> IPv6 */
 757         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 758         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 759         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 760         I40E_PTT_UNUSED_ENTRY(105),
 761         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 762         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 763         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 764
 765         /* IPv6 --> GRE/NAT */
 766         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 767
 768         /* IPv6 --> GRE/NAT -> IPv4 */
 769         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 770         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 771         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 772         I40E_PTT_UNUSED_ENTRY(113),
 773         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 774         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 775         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 776
 777         /* IPv6 --> GRE/NAT -> IPv6 */
 778         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 779         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 780         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 781         I40E_PTT_UNUSED_ENTRY(120),
 782         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 783         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 784         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 785
 786         /* IPv6 --> GRE/NAT -> MAC */
 787         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 788
 789         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 790         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 791         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 792         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 793         I40E_PTT_UNUSED_ENTRY(128),
 794         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 795         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 796         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 797
 798         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 799         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 800         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 801         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 802         I40E_PTT_UNUSED_ENTRY(135),
 803         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 804         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 805         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 806
 807         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 808         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 809
 810         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 811         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 812         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 813         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 814         I40E_PTT_UNUSED_ENTRY(143),
 815         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 816         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 817         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 818
 819         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 820         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 821         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 822         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 823         I40E_PTT_UNUSED_ENTRY(150),
 824         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 825         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 826         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 827
 828         /* unused entries */
 829         I40E_PTT_UNUSED_ENTRY(154),
 830         I40E_PTT_UNUSED_ENTRY(155),
 831         I40E_PTT_UNUSED_ENTRY(156),
 832         I40E_PTT_UNUSED_ENTRY(157),
 833         I40E_PTT_UNUSED_ENTRY(158),
 834         I40E_PTT_UNUSED_ENTRY(159),
 835
 836         I40E_PTT_UNUSED_ENTRY(160),
 837         I40E_PTT_UNUSED_ENTRY(161),
 838         I40E_PTT_UNUSED_ENTRY(162),
 839         I40E_PTT_UNUSED_ENTRY(163),
 840         I40E_PTT_UNUSED_ENTRY(164),
 841         I40E_PTT_UNUSED_ENTRY(165),
 842         I40E_PTT_UNUSED_ENTRY(166),
 843         I40E_PTT_UNUSED_ENTRY(167),
 844         I40E_PTT_UNUSED_ENTRY(168),
 845         I40E_PTT_UNUSED_ENTRY(169),
 846
 847         I40E_PTT_UNUSED_ENTRY(170),
 848         I40E_PTT_UNUSED_ENTRY(171),
 849         I40E_PTT_UNUSED_ENTRY(172),
 850         I40E_PTT_UNUSED_ENTRY(173),
 851         I40E_PTT_UNUSED_ENTRY(174),
 852         I40E_PTT_UNUSED_ENTRY(175),
 853         I40E_PTT_UNUSED_ENTRY(176),
 854         I40E_PTT_UNUSED_ENTRY(177),
 855         I40E_PTT_UNUSED_ENTRY(178),
 856         I40E_PTT_UNUSED_ENTRY(179),
 857
 858         I40E_PTT_UNUSED_ENTRY(180),
 859         I40E_PTT_UNUSED_ENTRY(181),
 860         I40E_PTT_UNUSED_ENTRY(182),
 861         I40E_PTT_UNUSED_ENTRY(183),
 862         I40E_PTT_UNUSED_ENTRY(184),
 863         I40E_PTT_UNUSED_ENTRY(185),
 864         I40E_PTT_UNUSED_ENTRY(186),
 865         I40E_PTT_UNUSED_ENTRY(187),
 866         I40E_PTT_UNUSED_ENTRY(188),
 867         I40E_PTT_UNUSED_ENTRY(189),
 868
 869         I40E_PTT_UNUSED_ENTRY(190),
 870         I40E_PTT_UNUSED_ENTRY(191),
 871         I40E_PTT_UNUSED_ENTRY(192),
 872         I40E_PTT_UNUSED_ENTRY(193),
 873         I40E_PTT_UNUSED_ENTRY(194),
 874         I40E_PTT_UNUSED_ENTRY(195),
 875         I40E_PTT_UNUSED_ENTRY(196),
 876         I40E_PTT_UNUSED_ENTRY(197),
 877         I40E_PTT_UNUSED_ENTRY(198),
 878         I40E_PTT_UNUSED_ENTRY(199),
 879
 880         I40E_PTT_UNUSED_ENTRY(200),
 881         I40E_PTT_UNUSED_ENTRY(201),
 882         I40E_PTT_UNUSED_ENTRY(202),
 883         I40E_PTT_UNUSED_ENTRY(203),
 884         I40E_PTT_UNUSED_ENTRY(204),
 885         I40E_PTT_UNUSED_ENTRY(205),
 886         I40E_PTT_UNUSED_ENTRY(206),
 887         I40E_PTT_UNUSED_ENTRY(207),
 888         I40E_PTT_UNUSED_ENTRY(208),
 889         I40E_PTT_UNUSED_ENTRY(209),
 890
 891         I40E_PTT_UNUSED_ENTRY(210),
 892         I40E_PTT_UNUSED_ENTRY(211),
 893         I40E_PTT_UNUSED_ENTRY(212),
 894         I40E_PTT_UNUSED_ENTRY(213),
 895         I40E_PTT_UNUSED_ENTRY(214),
 896         I40E_PTT_UNUSED_ENTRY(215),
 897         I40E_PTT_UNUSED_ENTRY(216),
 898         I40E_PTT_UNUSED_ENTRY(217),
 899         I40E_PTT_UNUSED_ENTRY(218),
 900         I40E_PTT_UNUSED_ENTRY(219),
 901
 902         I40E_PTT_UNUSED_ENTRY(220),
 903         I40E_PTT_UNUSED_ENTRY(221),
 904         I40E_PTT_UNUSED_ENTRY(222),
 905         I40E_PTT_UNUSED_ENTRY(223),
 906         I40E_PTT_UNUSED_ENTRY(224),
 907         I40E_PTT_UNUSED_ENTRY(225),
 908         I40E_PTT_UNUSED_ENTRY(226),
 909         I40E_PTT_UNUSED_ENTRY(227),
 910         I40E_PTT_UNUSED_ENTRY(228),
 911         I40E_PTT_UNUSED_ENTRY(229),
 912
 913         I40E_PTT_UNUSED_ENTRY(230),
 914         I40E_PTT_UNUSED_ENTRY(231),
 915         I40E_PTT_UNUSED_ENTRY(232),
 916         I40E_PTT_UNUSED_ENTRY(233),
 917         I40E_PTT_UNUSED_ENTRY(234),
 918         I40E_PTT_UNUSED_ENTRY(235),
 919         I40E_PTT_UNUSED_ENTRY(236),
 920         I40E_PTT_UNUSED_ENTRY(237),
 921         I40E_PTT_UNUSED_ENTRY(238),
 922         I40E_PTT_UNUSED_ENTRY(239),
 923
 924         I40E_PTT_UNUSED_ENTRY(240),
 925         I40E_PTT_UNUSED_ENTRY(241),
 926         I40E_PTT_UNUSED_ENTRY(242),
 927         I40E_PTT_UNUSED_ENTRY(243),
 928         I40E_PTT_UNUSED_ENTRY(244),
 929         I40E_PTT_UNUSED_ENTRY(245),
 930         I40E_PTT_UNUSED_ENTRY(246),
 931         I40E_PTT_UNUSED_ENTRY(247),
 932         I40E_PTT_UNUSED_ENTRY(248),
 933         I40E_PTT_UNUSED_ENTRY(249),
 934
 935         I40E_PTT_UNUSED_ENTRY(250),
 936         I40E_PTT_UNUSED_ENTRY(251),
 937         I40E_PTT_UNUSED_ENTRY(252),
 938         I40E_PTT_UNUSED_ENTRY(253),
 939         I40E_PTT_UNUSED_ENTRY(254),
 940         I40E_PTT_UNUSED_ENTRY(255)
 941 };
 942
 943
 944 /**
 945  * i40e_validate_mac_addr - Validate unicast MAC address
 946  * @mac_addr: pointer to MAC address
 947  *
 948  * Tests a MAC address to ensure it is a valid Individual Address
 949  **/
 950 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 951 {
 952         enum i40e_status_code status = I40E_SUCCESS;
 953
 954         DEBUGFUNC("i40e_validate_mac_addr");
 955
 956         /* Broadcast addresses ARE multicast addresses
 957          * Make sure it is not a multicast address
 958          * Reject the zero address
 959          */
 960         if (I40E_IS_MULTICAST(mac_addr) ||
 961             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 962               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 963                 status = I40E_ERR_INVALID_MAC_ADDR;
 964
 965         return status;
 966 }
 967
 968 /**
 969  * i40e_init_shared_code - Initialize the shared code
 970  * @hw: pointer to hardware structure
 971  *
 972  * This assigns the MAC type and PHY code and inits the NVM.
 973  * Does not touch the hardware. This function must be called prior to any
 974  * other function in the shared code. The i40e_hw structure should be
 975  * memset to 0 prior to calling this function.  The following fields in
 976  * hw structure should be filled in prior to calling this function:
 977  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 978  * subsystem_vendor_id, and revision_id
 979  **/
 980 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 981 {
 982         enum i40e_status_code status = I40E_SUCCESS;
 983         u32 port, ari, func_rid;
 984
 985         DEBUGFUNC("i40e_init_shared_code");
 986
 987         i40e_set_mac_type(hw);
 988
 989         switch (hw->mac.type) {
 990         case I40E_MAC_XL710:
 991         case I40E_MAC_X722:
 992                 break;
 993         default:
 994                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
 995         }
 996
 997         hw->phy.get_link_info = TRUE;
 998
 999         /* Determine port number and PF number*/
1000         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1001                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1002         hw->port = (u8)port;
1003         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1004                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1005         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1006         if (ari)
1007                 hw->pf_id = (u8)(func_rid & 0xff);
1008         else
1009                 hw->pf_id = (u8)(func_rid & 0x7);
1010
1011         if (hw->mac.type == I40E_MAC_X722)
1012                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1013
1014         status = i40e_init_nvm(hw);
1015         return status;
1016 }
1017
1018 /**
1019  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1020  * @hw: pointer to the hw struct
1021  * @flags: a return indicator of what addresses were added to the addr store
1022  * @addrs: the requestor's mac addr store
1023  * @cmd_details: pointer to command details structure or NULL
1024  **/
1025 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1026                                    u16 *flags,
1027                                    struct i40e_aqc_mac_address_read_data *addrs,
1028                                    struct i40e_asq_cmd_details *cmd_details)
1029 {
1030         struct i40e_aq_desc desc;
1031         struct i40e_aqc_mac_address_read *cmd_data =
1032                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1033         enum i40e_status_code status;
1034
1035         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1036         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1037
1038         status = i40e_asq_send_command(hw, &desc, addrs,
1039                                        sizeof(*addrs), cmd_details);
1040         *flags = LE16_TO_CPU(cmd_data->command_flags);
1041
1042         return status;
1043 }
1044
1045 /**
1046  * i40e_aq_mac_address_write - Change the MAC addresses
1047  * @hw: pointer to the hw struct
1048  * @flags: indicates which MAC to be written
1049  * @mac_addr: address to write
1050  * @cmd_details: pointer to command details structure or NULL
1051  **/
1052 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1053                                     u16 flags, u8 *mac_addr,
1054                                     struct i40e_asq_cmd_details *cmd_details)
1055 {
1056         struct i40e_aq_desc desc;
1057         struct i40e_aqc_mac_address_write *cmd_data =
1058                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1059         enum i40e_status_code status;
1060
1061         i40e_fill_default_direct_cmd_desc(&desc,
1062                                           i40e_aqc_opc_mac_address_write);
1063         cmd_data->command_flags = CPU_TO_LE16(flags);
1064         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1065         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1066                                         ((u32)mac_addr[3] << 16) |
1067                                         ((u32)mac_addr[4] << 8) |
1068                                         mac_addr[5]);
1069
1070         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1071
1072         return status;
1073 }
1074
1075 /**
1076  * i40e_get_mac_addr - get MAC address
1077  * @hw: pointer to the HW structure
1078  * @mac_addr: pointer to MAC address
1079  *
1080  * Reads the adapter's MAC address from register
1081  **/
1082 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1083 {
1084         struct i40e_aqc_mac_address_read_data addrs;
1085         enum i40e_status_code status;
1086         u16 flags = 0;
1087
1088         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1089
1090         if (flags & I40E_AQC_LAN_ADDR_VALID)
1091                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1092
1093         return status;
1094 }
1095
1096 /**
1097  * i40e_get_port_mac_addr - get Port MAC address
1098  * @hw: pointer to the HW structure
1099  * @mac_addr: pointer to Port MAC address
1100  *
1101  * Reads the adapter's Port MAC address
1102  **/
1103 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1104 {
1105         struct i40e_aqc_mac_address_read_data addrs;
1106         enum i40e_status_code status;
1107         u16 flags = 0;
1108
1109         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1110         if (status)
1111                 return status;
1112
1113         if (flags & I40E_AQC_PORT_ADDR_VALID)
1114                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1115         else
1116                 status = I40E_ERR_INVALID_MAC_ADDR;
1117
1118         return status;
1119 }
1120
1121 /**
1122  * i40e_pre_tx_queue_cfg - pre tx queue configure
1123  * @hw: pointer to the HW structure
1124  * @queue: target pf queue index
1125  * @enable: state change request
1126  *
1127  * Handles hw requirement to indicate intention to enable
1128  * or disable target queue.
1129  **/
1130 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1131 {
1132         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1133         u32 reg_block = 0;
1134         u32 reg_val;
1135
1136         if (abs_queue_idx >= 128) {
1137                 reg_block = abs_queue_idx / 128;
1138                 abs_queue_idx %= 128;
1139         }
1140
1141         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1142         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1143         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1144
1145         if (enable)
1146                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1147         else
1148                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1149
1150         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1151 }
1152
1153 /**
1154  *  i40e_read_pba_string - Reads part number string from EEPROM
1155  *  @hw: pointer to hardware structure
1156  *  @pba_num: stores the part number string from the EEPROM
1157  *  @pba_num_size: part number string buffer length
1158  *
1159  *  Reads the part number string from the EEPROM.
1160  **/
1161 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1162                                             u32 pba_num_size)
1163 {
1164         enum i40e_status_code status = I40E_SUCCESS;
1165         u16 pba_word = 0;
1166         u16 pba_size = 0;
1167         u16 pba_ptr = 0;
1168         u16 i = 0;
1169
1170         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1171         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1172                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1173                 return status;
1174         }
1175
1176         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1177         if (status != I40E_SUCCESS) {
1178                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1179                 return status;
1180         }
1181
1182         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1183         if (status != I40E_SUCCESS) {
1184                 DEBUGOUT("Failed to read PBA Block size.\n");
1185                 return status;
1186         }
1187
1188         /* Subtract one to get PBA word count (PBA Size word is included in
1189          * total size)
1190          */
1191         pba_size--;
1192         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1193                 DEBUGOUT("Buffer to small for PBA data.\n");
1194                 return I40E_ERR_PARAM;
1195         }
1196
1197         for (i = 0; i < pba_size; i++) {
1198                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1199                 if (status != I40E_SUCCESS) {
1200                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1201                         return status;
1202                 }
1203
1204                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1205                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1206         }
1207         pba_num[(pba_size * 2)] = '\0';
1208
1209         return status;
1210 }
1211
1212 /**
1213  * i40e_get_media_type - Gets media type
1214  * @hw: pointer to the hardware structure
1215  **/
1216 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1217 {
1218         enum i40e_media_type media;
1219
1220         switch (hw->phy.link_info.phy_type) {
1221         case I40E_PHY_TYPE_10GBASE_SR:
1222         case I40E_PHY_TYPE_10GBASE_LR:
1223         case I40E_PHY_TYPE_1000BASE_SX:
1224         case I40E_PHY_TYPE_1000BASE_LX:
1225         case I40E_PHY_TYPE_40GBASE_SR4:
1226         case I40E_PHY_TYPE_40GBASE_LR4:
1227                 media = I40E_MEDIA_TYPE_FIBER;
1228                 break;
1229         case I40E_PHY_TYPE_100BASE_TX:
1230         case I40E_PHY_TYPE_1000BASE_T:
1231         case I40E_PHY_TYPE_10GBASE_T:
1232                 media = I40E_MEDIA_TYPE_BASET;
1233                 break;
1234         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1235         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1236         case I40E_PHY_TYPE_10GBASE_CR1:
1237         case I40E_PHY_TYPE_40GBASE_CR4:
1238         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1239         case I40E_PHY_TYPE_40GBASE_AOC:
1240         case I40E_PHY_TYPE_10GBASE_AOC:
1241                 media = I40E_MEDIA_TYPE_DA;
1242                 break;
1243         case I40E_PHY_TYPE_1000BASE_KX:
1244         case I40E_PHY_TYPE_10GBASE_KX4:
1245         case I40E_PHY_TYPE_10GBASE_KR:
1246         case I40E_PHY_TYPE_40GBASE_KR4:
1247         case I40E_PHY_TYPE_20GBASE_KR2:
1248                 media = I40E_MEDIA_TYPE_BACKPLANE;
1249                 break;
1250         case I40E_PHY_TYPE_SGMII:
1251         case I40E_PHY_TYPE_XAUI:
1252         case I40E_PHY_TYPE_XFI:
1253         case I40E_PHY_TYPE_XLAUI:
1254         case I40E_PHY_TYPE_XLPPI:
1255         default:
1256                 media = I40E_MEDIA_TYPE_UNKNOWN;
1257                 break;
1258         }
1259
1260         return media;
1261 }
1262
1263 #define I40E_PF_RESET_WAIT_COUNT        200
1264 /**
1265  * i40e_pf_reset - Reset the PF
1266  * @hw: pointer to the hardware structure
1267  *
1268  * Assuming someone else has triggered a global reset,
1269  * assure the global reset is complete and then reset the PF
1270  **/
1271 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1272 {
1273         u32 cnt = 0;
1274         u32 cnt1 = 0;
1275         u32 reg = 0;
1276         u32 grst_del;
1277
1278         /* Poll for Global Reset steady state in case of recent GRST.
1279          * The grst delay value is in 100ms units, and we'll wait a
1280          * couple counts longer to be sure we don't just miss the end.
1281          */
1282         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1283                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1284                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1285
1286         grst_del = grst_del * 20;
1287
1288         for (cnt = 0; cnt < grst_del; cnt++) {
1289                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1290                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1291                         break;
1292                 i40e_msec_delay(100);
1293         }
1294         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1295                 DEBUGOUT("Global reset polling failed to complete.\n");
1296                 return I40E_ERR_RESET_FAILED;
1297         }
1298
1299         /* Now Wait for the FW to be ready */
1300         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1301                 reg = rd32(hw, I40E_GLNVM_ULD);
1302                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1303                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1304                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1305                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1306                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1307                         break;
1308                 }
1309                 i40e_msec_delay(10);
1310         }
1311         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1312                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1313                 DEBUGOUT("wait for FW Reset complete timedout\n");
1314                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1315                 return I40E_ERR_RESET_FAILED;
1316         }
1317
1318         /* If there was a Global Reset in progress when we got here,
1319          * we don't need to do the PF Reset
1320          */
1321         if (!cnt) {
1322                 reg = rd32(hw, I40E_PFGEN_CTRL);
1323                 wr32(hw, I40E_PFGEN_CTRL,
1324                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1325                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1326                         reg = rd32(hw, I40E_PFGEN_CTRL);
1327                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1328                                 break;
1329                         i40e_msec_delay(1);
1330                 }
1331                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1332                         DEBUGOUT("PF reset polling failed to complete.\n");
1333                         return I40E_ERR_RESET_FAILED;
1334                 }
1335         }
1336
1337         i40e_clear_pxe_mode(hw);
1338
1339
1340         return I40E_SUCCESS;
1341 }
1342
1343 /**
1344  * i40e_clear_hw - clear out any left over hw state
1345  * @hw: pointer to the hw struct
1346  *
1347  * Clear queues and interrupts, typically called at init time,
1348  * but after the capabilities have been found so we know how many
1349  * queues and msix vectors have been allocated.
1350  **/
1351 void i40e_clear_hw(struct i40e_hw *hw)
1352 {
1353         u32 num_queues, base_queue;
1354         u32 num_pf_int;
1355         u32 num_vf_int;
1356         u32 num_vfs;
1357         u32 i, j;
1358         u32 val;
1359         u32 eol = 0x7ff;
1360
1361         /* get number of interrupts, queues, and vfs */
1362         val = rd32(hw, I40E_GLPCI_CNF2);
1363         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1364                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1365         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1366                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1367
1368         val = rd32(hw, I40E_PFLAN_QALLOC);
1369         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1370                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1371         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1372                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1373         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1374                 num_queues = (j - base_queue) + 1;
1375         else
1376                 num_queues = 0;
1377
1378         val = rd32(hw, I40E_PF_VT_PFALLOC);
1379         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1380                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1381         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1382                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1383         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1384                 num_vfs = (j - i) + 1;
1385         else
1386                 num_vfs = 0;
1387
1388         /* stop all the interrupts */
1389         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1390         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1391         for (i = 0; i < num_pf_int - 2; i++)
1392                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1393
1394         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1395         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1396         wr32(hw, I40E_PFINT_LNKLST0, val);
1397         for (i = 0; i < num_pf_int - 2; i++)
1398                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1399         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1400         for (i = 0; i < num_vfs; i++)
1401                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1402         for (i = 0; i < num_vf_int - 2; i++)
1403                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1404
1405         /* warn the HW of the coming Tx disables */
1406         for (i = 0; i < num_queues; i++) {
1407                 u32 abs_queue_idx = base_queue + i;
1408                 u32 reg_block = 0;
1409
1410                 if (abs_queue_idx >= 128) {
1411                         reg_block = abs_queue_idx / 128;
1412                         abs_queue_idx %= 128;
1413                 }
1414
1415                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1416                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1417                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1418                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1419
1420                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1421         }
1422         i40e_usec_delay(400);
1423
1424         /* stop all the queues */
1425         for (i = 0; i < num_queues; i++) {
1426                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1427                 wr32(hw, I40E_QTX_ENA(i), 0);
1428                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1429                 wr32(hw, I40E_QRX_ENA(i), 0);
1430         }
1431
1432         /* short wait for all queue disables to settle */
1433         i40e_usec_delay(50);
1434 }
1435
1436 /**
1437  * i40e_clear_pxe_mode - clear pxe operations mode
1438  * @hw: pointer to the hw struct
1439  *
1440  * Make sure all PXE mode settings are cleared, including things
1441  * like descriptor fetch/write-back mode.
1442  **/
1443 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1444 {
1445         if (i40e_check_asq_alive(hw))
1446                 i40e_aq_clear_pxe_mode(hw, NULL);
1447 }
1448
1449 /**
1450  * i40e_led_is_mine - helper to find matching led
1451  * @hw: pointer to the hw struct
1452  * @idx: index into GPIO registers
1453  *
1454  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1455  */
1456 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1457 {
1458         u32 gpio_val = 0;
1459         u32 port;
1460
1461         if (!hw->func_caps.led[idx])
1462                 return 0;
1463
1464         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1465         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1466                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1467
1468         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1469          * if it is not our port then ignore
1470          */
1471         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1472             (port != hw->port))
1473                 return 0;
1474
1475         return gpio_val;
1476 }
1477
1478 #define I40E_COMBINED_ACTIVITY 0xA
1479 #define I40E_FILTER_ACTIVITY 0xE
1480 #define I40E_LINK_ACTIVITY 0xC
1481 #define I40E_MAC_ACTIVITY 0xD
1482 #define I40E_LED0 22
1483
1484 /**
1485  * i40e_led_get - return current on/off mode
1486  * @hw: pointer to the hw struct
1487  *
1488  * The value returned is the 'mode' field as defined in the
1489  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1490  * values are variations of possible behaviors relating to
1491  * blink, link, and wire.
1492  **/
1493 u32 i40e_led_get(struct i40e_hw *hw)
1494 {
1495         u32 current_mode = 0;
1496         u32 mode = 0;
1497         int i;
1498
1499         /* as per the documentation GPIO 22-29 are the LED
1500          * GPIO pins named LED0..LED7
1501          */
1502         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1503                 u32 gpio_val = i40e_led_is_mine(hw, i);
1504
1505                 if (!gpio_val)
1506                         continue;
1507
1508                 /* ignore gpio LED src mode entries related to the activity
1509                  *  LEDs
1510                  */
1511                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1512                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1513                 switch (current_mode) {
1514                 case I40E_COMBINED_ACTIVITY:
1515                 case I40E_FILTER_ACTIVITY:
1516                 case I40E_MAC_ACTIVITY:
1517                         continue;
1518                 default:
1519                         break;
1520                 }
1521
1522                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1523                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1524                 break;
1525         }
1526
1527         return mode;
1528 }
1529
1530 /**
1531  * i40e_led_set - set new on/off mode
1532  * @hw: pointer to the hw struct
1533  * @mode: 0=off, 0xf=on (else see manual for mode details)
1534  * @blink: TRUE if the LED should blink when on, FALSE if steady
1535  *
1536  * if this function is used to turn on the blink it should
1537  * be used to disable the blink when restoring the original state.
1538  **/
1539 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1540 {
1541         u32 current_mode = 0;
1542         int i;
1543
1544         if (mode & 0xfffffff0)
1545                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1546
1547         /* as per the documentation GPIO 22-29 are the LED
1548          * GPIO pins named LED0..LED7
1549          */
1550         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1551                 u32 gpio_val = i40e_led_is_mine(hw, i);
1552
1553                 if (!gpio_val)
1554                         continue;
1555
1556                 /* ignore gpio LED src mode entries related to the activity
1557                  * LEDs
1558                  */
1559                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1560                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1561                 switch (current_mode) {
1562                 case I40E_COMBINED_ACTIVITY:
1563                 case I40E_FILTER_ACTIVITY:
1564                 case I40E_MAC_ACTIVITY:
1565                         continue;
1566                 default:
1567                         break;
1568                 }
1569
1570                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1571                 /* this & is a bit of paranoia, but serves as a range check */
1572                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1573                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1574
1575                 if (mode == I40E_LINK_ACTIVITY)
1576                         blink = FALSE;
1577
1578                 if (blink)
1579                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1580                 else
1581                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1582
1583                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1584                 break;
1585         }
1586 }
1587
1588 /* Admin command wrappers */
1589
1590 /**
1591  * i40e_aq_get_phy_capabilities
1592  * @hw: pointer to the hw struct
1593  * @abilities: structure for PHY capabilities to be filled
1594  * @qualified_modules: report Qualified Modules
1595  * @report_init: report init capabilities (active are default)
1596  * @cmd_details: pointer to command details structure or NULL
1597  *
1598  * Returns the various PHY abilities supported on the Port.
1599  **/
1600 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1601                         bool qualified_modules, bool report_init,
1602                         struct i40e_aq_get_phy_abilities_resp *abilities,
1603                         struct i40e_asq_cmd_details *cmd_details)
1604 {
1605         struct i40e_aq_desc desc;
1606         enum i40e_status_code status;
1607         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1608
1609         if (!abilities)
1610                 return I40E_ERR_PARAM;
1611
1612         i40e_fill_default_direct_cmd_desc(&desc,
1613                                           i40e_aqc_opc_get_phy_abilities);
1614
1615         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1616         if (abilities_size > I40E_AQ_LARGE_BUF)
1617                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1618
1619         if (qualified_modules)
1620                 desc.params.external.param0 |=
1621                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1622
1623         if (report_init)
1624                 desc.params.external.param0 |=
1625                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1626
1627         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1628                                     cmd_details);
1629
1630         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1631                 status = I40E_ERR_UNKNOWN_PHY;
1632
1633         if (report_init) {
1634                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1635                 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1636         }
1637
1638         return status;
1639 }
1640
1641 /**
1642  * i40e_aq_set_phy_config
1643  * @hw: pointer to the hw struct
1644  * @config: structure with PHY configuration to be set
1645  * @cmd_details: pointer to command details structure or NULL
1646  *
1647  * Set the various PHY configuration parameters
1648  * supported on the Port.One or more of the Set PHY config parameters may be
1649  * ignored in an MFP mode as the PF may not have the privilege to set some
1650  * of the PHY Config parameters. This status will be indicated by the
1651  * command response.
1652  **/
1653 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1654                                 struct i40e_aq_set_phy_config *config,
1655                                 struct i40e_asq_cmd_details *cmd_details)
1656 {
1657         struct i40e_aq_desc desc;
1658         struct i40e_aq_set_phy_config *cmd =
1659                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1660         enum i40e_status_code status;
1661
1662         if (!config)
1663                 return I40E_ERR_PARAM;
1664
1665         i40e_fill_default_direct_cmd_desc(&desc,
1666                                           i40e_aqc_opc_set_phy_config);
1667
1668         *cmd = *config;
1669
1670         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1671
1672         return status;
1673 }
1674
1675 /**
1676  * i40e_set_fc
1677  * @hw: pointer to the hw struct
1678  *
1679  * Set the requested flow control mode using set_phy_config.
1680  **/
1681 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1682                                   bool atomic_restart)
1683 {
1684         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1685         struct i40e_aq_get_phy_abilities_resp abilities;
1686         struct i40e_aq_set_phy_config config;
1687         enum i40e_status_code status;
1688         u8 pause_mask = 0x0;
1689
1690         *aq_failures = 0x0;
1691
1692         switch (fc_mode) {
1693         case I40E_FC_FULL:
1694                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1695                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1696                 break;
1697         case I40E_FC_RX_PAUSE:
1698                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1699                 break;
1700         case I40E_FC_TX_PAUSE:
1701                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1702                 break;
1703         default:
1704                 break;
1705         }
1706
1707         /* Get the current phy config */
1708         status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities,
1709                                               NULL);
1710         if (status) {
1711                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1712                 return status;
1713         }
1714
1715         memset(&config, 0, sizeof(config));
1716         /* clear the old pause settings */
1717         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1718                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1719         /* set the new abilities */
1720         config.abilities |= pause_mask;
1721         /* If the abilities have changed, then set the new config */
1722         if (config.abilities != abilities.abilities) {
1723                 /* Auto restart link so settings take effect */
1724                 if (atomic_restart)
1725                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1726                 /* Copy over all the old settings */
1727                 config.phy_type = abilities.phy_type;
1728                 config.link_speed = abilities.link_speed;
1729                 config.eee_capability = abilities.eee_capability;
1730                 config.eeer = abilities.eeer_val;
1731                 config.low_power_ctrl = abilities.d3_lpan;
1732                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1733
1734                 if (status)
1735                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1736         }
1737         /* Update the link info */
1738         status = i40e_update_link_info(hw);
1739         if (status) {
1740                 /* Wait a little bit (on 40G cards it sometimes takes a really
1741                  * long time for link to come back from the atomic reset)
1742                  * and try once more
1743                  */
1744                 i40e_msec_delay(1000);
1745                 status = i40e_update_link_info(hw);
1746         }
1747         if (status)
1748                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1749
1750         return status;
1751 }
1752
1753 /**
1754  * i40e_aq_set_mac_config
1755  * @hw: pointer to the hw struct
1756  * @max_frame_size: Maximum Frame Size to be supported by the port
1757  * @crc_en: Tell HW to append a CRC to outgoing frames
1758  * @pacing: Pacing configurations
1759  * @cmd_details: pointer to command details structure or NULL
1760  *
1761  * Configure MAC settings for frame size, jumbo frame support and the
1762  * addition of a CRC by the hardware.
1763  **/
1764 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1765                                 u16 max_frame_size,
1766                                 bool crc_en, u16 pacing,
1767                                 struct i40e_asq_cmd_details *cmd_details)
1768 {
1769         struct i40e_aq_desc desc;
1770         struct i40e_aq_set_mac_config *cmd =
1771                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1772         enum i40e_status_code status;
1773
1774         if (max_frame_size == 0)
1775                 return I40E_ERR_PARAM;
1776
1777         i40e_fill_default_direct_cmd_desc(&desc,
1778                                           i40e_aqc_opc_set_mac_config);
1779
1780         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1781         cmd->params = ((u8)pacing & 0x0F) << 3;
1782         if (crc_en)
1783                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1784
1785         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1786
1787         return status;
1788 }
1789
1790 /**
1791  * i40e_aq_clear_pxe_mode
1792  * @hw: pointer to the hw struct
1793  * @cmd_details: pointer to command details structure or NULL
1794  *
1795  * Tell the firmware that the driver is taking over from PXE
1796  **/
1797 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1798                         struct i40e_asq_cmd_details *cmd_details)
1799 {
1800         enum i40e_status_code status;
1801         struct i40e_aq_desc desc;
1802         struct i40e_aqc_clear_pxe *cmd =
1803                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1804
1805         i40e_fill_default_direct_cmd_desc(&desc,
1806                                           i40e_aqc_opc_clear_pxe_mode);
1807
1808         cmd->rx_cnt = 0x2;
1809
1810         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1811
1812         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1813
1814         return status;
1815 }
1816
1817 /**
1818  * i40e_aq_set_link_restart_an
1819  * @hw: pointer to the hw struct
1820  * @enable_link: if TRUE: enable link, if FALSE: disable link
1821  * @cmd_details: pointer to command details structure or NULL
1822  *
1823  * Sets up the link and restarts the Auto-Negotiation over the link.
1824  **/
1825 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1826                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1827 {
1828         struct i40e_aq_desc desc;
1829         struct i40e_aqc_set_link_restart_an *cmd =
1830                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1831         enum i40e_status_code status;
1832
1833         i40e_fill_default_direct_cmd_desc(&desc,
1834                                           i40e_aqc_opc_set_link_restart_an);
1835
1836         cmd->command = I40E_AQ_PHY_RESTART_AN;
1837         if (enable_link)
1838                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1839         else
1840                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1841
1842         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1843
1844         return status;
1845 }
1846
1847 /**
1848  * i40e_aq_get_link_info
1849  * @hw: pointer to the hw struct
1850  * @enable_lse: enable/disable LinkStatusEvent reporting
1851  * @link: pointer to link status structure - optional
1852  * @cmd_details: pointer to command details structure or NULL
1853  *
1854  * Returns the link status of the adapter.
1855  **/
1856 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1857                                 bool enable_lse, struct i40e_link_status *link,
1858                                 struct i40e_asq_cmd_details *cmd_details)
1859 {
1860         struct i40e_aq_desc desc;
1861         struct i40e_aqc_get_link_status *resp =
1862                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1863         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1864         enum i40e_status_code status;
1865         bool tx_pause, rx_pause;
1866         u16 command_flags;
1867
1868         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1869
1870         if (enable_lse)
1871                 command_flags = I40E_AQ_LSE_ENABLE;
1872         else
1873                 command_flags = I40E_AQ_LSE_DISABLE;
1874         resp->command_flags = CPU_TO_LE16(command_flags);
1875
1876         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1877
1878         if (status != I40E_SUCCESS)
1879                 goto aq_get_link_info_exit;
1880
1881         /* save off old link status information */
1882         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1883                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1884
1885         /* update link status */
1886         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1887         hw->phy.media_type = i40e_get_media_type(hw);
1888         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1889         hw_link_info->link_info = resp->link_info;
1890         hw_link_info->an_info = resp->an_info;
1891         hw_link_info->ext_info = resp->ext_info;
1892         hw_link_info->loopback = resp->loopback;
1893         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1894         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1895
1896         /* update fc info */
1897         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1898         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1899         if (tx_pause & rx_pause)
1900                 hw->fc.current_mode = I40E_FC_FULL;
1901         else if (tx_pause)
1902                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1903         else if (rx_pause)
1904                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1905         else
1906                 hw->fc.current_mode = I40E_FC_NONE;
1907
1908         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1909                 hw_link_info->crc_enable = TRUE;
1910         else
1911                 hw_link_info->crc_enable = FALSE;
1912
1913         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1914                 hw_link_info->lse_enable = TRUE;
1915         else
1916                 hw_link_info->lse_enable = FALSE;
1917
1918         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1919              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1920                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1921
1922         /* save link status information */
1923         if (link)
1924                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1925                             I40E_NONDMA_TO_NONDMA);
1926
1927         /* flag cleared so helper functions don't call AQ again */
1928         hw->phy.get_link_info = FALSE;
1929
1930 aq_get_link_info_exit:
1931         return status;
1932 }
1933
1934 /**
1935  * i40e_aq_set_phy_int_mask
1936  * @hw: pointer to the hw struct
1937  * @mask: interrupt mask to be set
1938  * @cmd_details: pointer to command details structure or NULL
1939  *
1940  * Set link interrupt mask.
1941  **/
1942 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1943                                 u16 mask,
1944                                 struct i40e_asq_cmd_details *cmd_details)
1945 {
1946         struct i40e_aq_desc desc;
1947         struct i40e_aqc_set_phy_int_mask *cmd =
1948                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1949         enum i40e_status_code status;
1950
1951         i40e_fill_default_direct_cmd_desc(&desc,
1952                                           i40e_aqc_opc_set_phy_int_mask);
1953
1954         cmd->event_mask = CPU_TO_LE16(mask);
1955
1956         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1957
1958         return status;
1959 }
1960
1961 /**
1962  * i40e_aq_get_local_advt_reg
1963  * @hw: pointer to the hw struct
1964  * @advt_reg: local AN advertisement register value
1965  * @cmd_details: pointer to command details structure or NULL
1966  *
1967  * Get the Local AN advertisement register value.
1968  **/
1969 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1970                                 u64 *advt_reg,
1971                                 struct i40e_asq_cmd_details *cmd_details)
1972 {
1973         struct i40e_aq_desc desc;
1974         struct i40e_aqc_an_advt_reg *resp =
1975                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1976         enum i40e_status_code status;
1977
1978         i40e_fill_default_direct_cmd_desc(&desc,
1979                                           i40e_aqc_opc_get_local_advt_reg);
1980
1981         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1982
1983         if (status != I40E_SUCCESS)
1984                 goto aq_get_local_advt_reg_exit;
1985
1986         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1987         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1988
1989 aq_get_local_advt_reg_exit:
1990         return status;
1991 }
1992
1993 /**
1994  * i40e_aq_set_local_advt_reg
1995  * @hw: pointer to the hw struct
1996  * @advt_reg: local AN advertisement register value
1997  * @cmd_details: pointer to command details structure or NULL
1998  *
1999  * Get the Local AN advertisement register value.
2000  **/
2001 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2002                                 u64 advt_reg,
2003                                 struct i40e_asq_cmd_details *cmd_details)
2004 {
2005         struct i40e_aq_desc desc;
2006         struct i40e_aqc_an_advt_reg *cmd =
2007                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2008         enum i40e_status_code status;
2009
2010         i40e_fill_default_direct_cmd_desc(&desc,
2011                                           i40e_aqc_opc_get_local_advt_reg);
2012
2013         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2014         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2015
2016         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2017
2018         return status;
2019 }
2020
2021 /**
2022  * i40e_aq_get_partner_advt
2023  * @hw: pointer to the hw struct
2024  * @advt_reg: AN partner advertisement register value
2025  * @cmd_details: pointer to command details structure or NULL
2026  *
2027  * Get the link partner AN advertisement register value.
2028  **/
2029 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2030                                 u64 *advt_reg,
2031                                 struct i40e_asq_cmd_details *cmd_details)
2032 {
2033         struct i40e_aq_desc desc;
2034         struct i40e_aqc_an_advt_reg *resp =
2035                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2036         enum i40e_status_code status;
2037
2038         i40e_fill_default_direct_cmd_desc(&desc,
2039                                           i40e_aqc_opc_get_partner_advt);
2040
2041         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2042
2043         if (status != I40E_SUCCESS)
2044                 goto aq_get_partner_advt_exit;
2045
2046         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2047         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2048
2049 aq_get_partner_advt_exit:
2050         return status;
2051 }
2052
2053 /**
2054  * i40e_aq_set_lb_modes
2055  * @hw: pointer to the hw struct
2056  * @lb_modes: loopback mode to be set
2057  * @cmd_details: pointer to command details structure or NULL
2058  *
2059  * Sets loopback modes.
2060  **/
2061 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2062                                 u16 lb_modes,
2063                                 struct i40e_asq_cmd_details *cmd_details)
2064 {
2065         struct i40e_aq_desc desc;
2066         struct i40e_aqc_set_lb_mode *cmd =
2067                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2068         enum i40e_status_code status;
2069
2070         i40e_fill_default_direct_cmd_desc(&desc,
2071                                           i40e_aqc_opc_set_lb_modes);
2072
2073         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2074
2075         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2076
2077         return status;
2078 }
2079
2080 /**
2081  * i40e_aq_set_phy_debug
2082  * @hw: pointer to the hw struct
2083  * @cmd_flags: debug command flags
2084  * @cmd_details: pointer to command details structure or NULL
2085  *
2086  * Reset the external PHY.
2087  **/
2088 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2089                                 struct i40e_asq_cmd_details *cmd_details)
2090 {
2091         struct i40e_aq_desc desc;
2092         struct i40e_aqc_set_phy_debug *cmd =
2093                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2094         enum i40e_status_code status;
2095
2096         i40e_fill_default_direct_cmd_desc(&desc,
2097                                           i40e_aqc_opc_set_phy_debug);
2098
2099         cmd->command_flags = cmd_flags;
2100
2101         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2102
2103         return status;
2104 }
2105
2106 /**
2107  * i40e_aq_add_vsi
2108  * @hw: pointer to the hw struct
2109  * @vsi_ctx: pointer to a vsi context struct
2110  * @cmd_details: pointer to command details structure or NULL
2111  *
2112  * Add a VSI context to the hardware.
2113 **/
2114 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2115                                 struct i40e_vsi_context *vsi_ctx,
2116                                 struct i40e_asq_cmd_details *cmd_details)
2117 {
2118         struct i40e_aq_desc desc;
2119         struct i40e_aqc_add_get_update_vsi *cmd =
2120                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2121         struct i40e_aqc_add_get_update_vsi_completion *resp =
2122                 (struct i40e_aqc_add_get_update_vsi_completion *)
2123                 &desc.params.raw;
2124         enum i40e_status_code status;
2125
2126         i40e_fill_default_direct_cmd_desc(&desc,
2127                                           i40e_aqc_opc_add_vsi);
2128
2129         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2130         cmd->connection_type = vsi_ctx->connection_type;
2131         cmd->vf_id = vsi_ctx->vf_num;
2132         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2133
2134         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2135
2136         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2137                                     sizeof(vsi_ctx->info), cmd_details);
2138
2139         if (status != I40E_SUCCESS)
2140                 goto aq_add_vsi_exit;
2141
2142         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2143         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2144         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2145         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2146
2147 aq_add_vsi_exit:
2148         return status;
2149 }
2150
2151 /**
2152  * i40e_aq_set_default_vsi
2153  * @hw: pointer to the hw struct
2154  * @seid: vsi number
2155  * @cmd_details: pointer to command details structure or NULL
2156  **/
2157 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2158                                 u16 seid,
2159                                 struct i40e_asq_cmd_details *cmd_details)
2160 {
2161         struct i40e_aq_desc desc;
2162         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2163                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2164                 &desc.params.raw;
2165         enum i40e_status_code status;
2166
2167         i40e_fill_default_direct_cmd_desc(&desc,
2168                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2169
2170         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2171         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2172         cmd->seid = CPU_TO_LE16(seid);
2173
2174         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2175
2176         return status;
2177 }
2178
2179 /**
2180  * i40e_aq_clear_default_vsi
2181  * @hw: pointer to the hw struct
2182  * @seid: vsi number
2183  * @cmd_details: pointer to command details structure or NULL
2184  **/
2185 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2186                                 u16 seid,
2187                                 struct i40e_asq_cmd_details *cmd_details)
2188 {
2189         struct i40e_aq_desc desc;
2190         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2191                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2192                 &desc.params.raw;
2193         enum i40e_status_code status;
2194
2195         i40e_fill_default_direct_cmd_desc(&desc,
2196                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2197
2198         cmd->promiscuous_flags = CPU_TO_LE16(0);
2199         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2200         cmd->seid = CPU_TO_LE16(seid);
2201
2202         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2203
2204         return status;
2205 }
2206
2207 /**
2208  * i40e_aq_set_vsi_unicast_promiscuous
2209  * @hw: pointer to the hw struct
2210  * @seid: vsi number
2211  * @set: set unicast promiscuous enable/disable
2212  * @cmd_details: pointer to command details structure or NULL
2213  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2214  **/
2215 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2216                                 u16 seid, bool set,
2217                                 struct i40e_asq_cmd_details *cmd_details,
2218                                 bool rx_only_promisc)
2219 {
2220         struct i40e_aq_desc desc;
2221         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2222                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2223         enum i40e_status_code status;
2224         u16 flags = 0;
2225
2226         i40e_fill_default_direct_cmd_desc(&desc,
2227                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2228
2229         if (set) {
2230                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2231                 if (rx_only_promisc &&
2232                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2233                      (hw->aq.api_maj_ver > 1)))
2234                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2235         }
2236
2237         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2238
2239         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2240         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2241              (hw->aq.api_maj_ver > 1))
2242                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2243
2244         cmd->seid = CPU_TO_LE16(seid);
2245         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2246
2247         return status;
2248 }
2249
2250 /**
2251  * i40e_aq_set_vsi_multicast_promiscuous
2252  * @hw: pointer to the hw struct
2253  * @seid: vsi number
2254  * @set: set multicast promiscuous enable/disable
2255  * @cmd_details: pointer to command details structure or NULL
2256  **/
2257 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2258                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2259 {
2260         struct i40e_aq_desc desc;
2261         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2262                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2263         enum i40e_status_code status;
2264         u16 flags = 0;
2265
2266         i40e_fill_default_direct_cmd_desc(&desc,
2267                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2268
2269         if (set)
2270                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2271
2272         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2273
2274         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2275
2276         cmd->seid = CPU_TO_LE16(seid);
2277         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2278
2279         return status;
2280 }
2281
2282 /**
2283  * i40e_aq_set_vsi_mc_promisc_on_vlan
2284  * @hw: pointer to the hw struct
2285  * @seid: vsi number
2286  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2287  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2288  * @cmd_details: pointer to command details structure or NULL
2289  **/
2290 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2291                                 u16 seid, bool enable, u16 vid,
2292                                 struct i40e_asq_cmd_details *cmd_details)
2293 {
2294         struct i40e_aq_desc desc;
2295         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2296                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2297         enum i40e_status_code status;
2298         u16 flags = 0;
2299
2300         i40e_fill_default_direct_cmd_desc(&desc,
2301                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2302
2303         if (enable)
2304                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2305
2306         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2307         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2308         cmd->seid = CPU_TO_LE16(seid);
2309         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2310
2311         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2312
2313         return status;
2314 }
2315
2316 /**
2317  * i40e_aq_set_vsi_uc_promisc_on_vlan
2318  * @hw: pointer to the hw struct
2319  * @seid: vsi number
2320  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2321  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2322  * @cmd_details: pointer to command details structure or NULL
2323  **/
2324 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2325                                 u16 seid, bool enable, u16 vid,
2326                                 struct i40e_asq_cmd_details *cmd_details)
2327 {
2328         struct i40e_aq_desc desc;
2329         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2330                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2331         enum i40e_status_code status;
2332         u16 flags = 0;
2333
2334         i40e_fill_default_direct_cmd_desc(&desc,
2335                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2336
2337         if (enable)
2338                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2339
2340         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2341         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2342         cmd->seid = CPU_TO_LE16(seid);
2343         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2344
2345         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2346
2347         return status;
2348 }
2349
2350 /**
2351  * i40e_aq_set_vsi_broadcast
2352  * @hw: pointer to the hw struct
2353  * @seid: vsi number
2354  * @set_filter: TRUE to set filter, FALSE to clear filter
2355  * @cmd_details: pointer to command details structure or NULL
2356  *
2357  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2358  **/
2359 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2360                                 u16 seid, bool set_filter,
2361                                 struct i40e_asq_cmd_details *cmd_details)
2362 {
2363         struct i40e_aq_desc desc;
2364         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2365                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2366         enum i40e_status_code status;
2367
2368         i40e_fill_default_direct_cmd_desc(&desc,
2369                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2370
2371         if (set_filter)
2372                 cmd->promiscuous_flags
2373                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2374         else
2375                 cmd->promiscuous_flags
2376                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2377
2378         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2379         cmd->seid = CPU_TO_LE16(seid);
2380         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2381
2382         return status;
2383 }
2384
2385 /**
2386  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2387  * @hw: pointer to the hw struct
2388  * @seid: vsi number
2389  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2390  * @cmd_details: pointer to command details structure or NULL
2391  **/
2392 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2393                                 u16 seid, bool enable,
2394                                 struct i40e_asq_cmd_details *cmd_details)
2395 {
2396         struct i40e_aq_desc desc;
2397         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2398                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2399         enum i40e_status_code status;
2400         u16 flags = 0;
2401
2402         i40e_fill_default_direct_cmd_desc(&desc,
2403                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2404         if (enable)
2405                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2406
2407         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2408         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2409         cmd->seid = CPU_TO_LE16(seid);
2410
2411         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2412
2413         return status;
2414 }
2415
2416 /**
2417  * i40e_get_vsi_params - get VSI configuration info
2418  * @hw: pointer to the hw struct
2419  * @vsi_ctx: pointer to a vsi context struct
2420  * @cmd_details: pointer to command details structure or NULL
2421  **/
2422 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2423                                 struct i40e_vsi_context *vsi_ctx,
2424                                 struct i40e_asq_cmd_details *cmd_details)
2425 {
2426         struct i40e_aq_desc desc;
2427         struct i40e_aqc_add_get_update_vsi *cmd =
2428                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2429         struct i40e_aqc_add_get_update_vsi_completion *resp =
2430                 (struct i40e_aqc_add_get_update_vsi_completion *)
2431                 &desc.params.raw;
2432         enum i40e_status_code status;
2433
2434         i40e_fill_default_direct_cmd_desc(&desc,
2435                                           i40e_aqc_opc_get_vsi_parameters);
2436
2437         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2438
2439         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2440
2441         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2442                                     sizeof(vsi_ctx->info), NULL);
2443
2444         if (status != I40E_SUCCESS)
2445                 goto aq_get_vsi_params_exit;
2446
2447         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2448         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2449         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2450         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2451
2452 aq_get_vsi_params_exit:
2453         return status;
2454 }
2455
2456 /**
2457  * i40e_aq_update_vsi_params
2458  * @hw: pointer to the hw struct
2459  * @vsi_ctx: pointer to a vsi context struct
2460  * @cmd_details: pointer to command details structure or NULL
2461  *
2462  * Update a VSI context.
2463  **/
2464 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2465                                 struct i40e_vsi_context *vsi_ctx,
2466                                 struct i40e_asq_cmd_details *cmd_details)
2467 {
2468         struct i40e_aq_desc desc;
2469         struct i40e_aqc_add_get_update_vsi *cmd =
2470                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2471         struct i40e_aqc_add_get_update_vsi_completion *resp =
2472                 (struct i40e_aqc_add_get_update_vsi_completion *)
2473                 &desc.params.raw;
2474         enum i40e_status_code status;
2475
2476         i40e_fill_default_direct_cmd_desc(&desc,
2477                                           i40e_aqc_opc_update_vsi_parameters);
2478         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2479
2480         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2481
2482         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2483                                     sizeof(vsi_ctx->info), cmd_details);
2484
2485         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2486         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2487
2488         return status;
2489 }
2490
2491 /**
2492  * i40e_aq_get_switch_config
2493  * @hw: pointer to the hardware structure
2494  * @buf: pointer to the result buffer
2495  * @buf_size: length of input buffer
2496  * @start_seid: seid to start for the report, 0 == beginning
2497  * @cmd_details: pointer to command details structure or NULL
2498  *
2499  * Fill the buf with switch configuration returned from AdminQ command
2500  **/
2501 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2502                                 struct i40e_aqc_get_switch_config_resp *buf,
2503                                 u16 buf_size, u16 *start_seid,
2504                                 struct i40e_asq_cmd_details *cmd_details)
2505 {
2506         struct i40e_aq_desc desc;
2507         struct i40e_aqc_switch_seid *scfg =
2508                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2509         enum i40e_status_code status;
2510
2511         i40e_fill_default_direct_cmd_desc(&desc,
2512                                           i40e_aqc_opc_get_switch_config);
2513         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2514         if (buf_size > I40E_AQ_LARGE_BUF)
2515                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2516         scfg->seid = CPU_TO_LE16(*start_seid);
2517
2518         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2519         *start_seid = LE16_TO_CPU(scfg->seid);
2520
2521         return status;
2522 }
2523
2524 /**
2525  * i40e_aq_set_switch_config
2526  * @hw: pointer to the hardware structure
2527  * @flags: bit flag values to set
2528  * @valid_flags: which bit flags to set
2529  * @cmd_details: pointer to command details structure or NULL
2530  *
2531  * Set switch configuration bits
2532  **/
2533 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2534                                 u16 flags, u16 valid_flags,
2535                                 struct i40e_asq_cmd_details *cmd_details)
2536 {
2537         struct i40e_aq_desc desc;
2538         struct i40e_aqc_set_switch_config *scfg =
2539                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2540         enum i40e_status_code status;
2541
2542         i40e_fill_default_direct_cmd_desc(&desc,
2543                                           i40e_aqc_opc_set_switch_config);
2544         scfg->flags = CPU_TO_LE16(flags);
2545         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2546
2547         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2548
2549         return status;
2550 }
2551
2552 /**
2553  * i40e_aq_get_firmware_version
2554  * @hw: pointer to the hw struct
2555  * @fw_major_version: firmware major version
2556  * @fw_minor_version: firmware minor version
2557  * @fw_build: firmware build number
2558  * @api_major_version: major queue version
2559  * @api_minor_version: minor queue version
2560  * @cmd_details: pointer to command details structure or NULL
2561  *
2562  * Get the firmware version from the admin queue commands
2563  **/
2564 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2565                                 u16 *fw_major_version, u16 *fw_minor_version,
2566                                 u32 *fw_build,
2567                                 u16 *api_major_version, u16 *api_minor_version,
2568                                 struct i40e_asq_cmd_details *cmd_details)
2569 {
2570         struct i40e_aq_desc desc;
2571         struct i40e_aqc_get_version *resp =
2572                 (struct i40e_aqc_get_version *)&desc.params.raw;
2573         enum i40e_status_code status;
2574
2575         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2576
2577         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2578
2579         if (status == I40E_SUCCESS) {
2580                 if (fw_major_version != NULL)
2581                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2582                 if (fw_minor_version != NULL)
2583                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2584                 if (fw_build != NULL)
2585                         *fw_build = LE32_TO_CPU(resp->fw_build);
2586                 if (api_major_version != NULL)
2587                         *api_major_version = LE16_TO_CPU(resp->api_major);
2588                 if (api_minor_version != NULL)
2589                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2590
2591                 /* A workaround to fix the API version in SW */
2592                 if (api_major_version && api_minor_version &&
2593                     fw_major_version && fw_minor_version &&
2594                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2595                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2596                      (*fw_major_version > 4)))
2597                         *api_minor_version = 2;
2598         }
2599
2600         return status;
2601 }
2602
2603 /**
2604  * i40e_aq_send_driver_version
2605  * @hw: pointer to the hw struct
2606  * @dv: driver's major, minor version
2607  * @cmd_details: pointer to command details structure or NULL
2608  *
2609  * Send the driver version to the firmware
2610  **/
2611 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2612                                 struct i40e_driver_version *dv,
2613                                 struct i40e_asq_cmd_details *cmd_details)
2614 {
2615         struct i40e_aq_desc desc;
2616         struct i40e_aqc_driver_version *cmd =
2617                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2618         enum i40e_status_code status;
2619         u16 len;
2620
2621         if (dv == NULL)
2622                 return I40E_ERR_PARAM;
2623
2624         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2625
2626         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2627         cmd->driver_major_ver = dv->major_version;
2628         cmd->driver_minor_ver = dv->minor_version;
2629         cmd->driver_build_ver = dv->build_version;
2630         cmd->driver_subbuild_ver = dv->subbuild_version;
2631
2632         len = 0;
2633         while (len < sizeof(dv->driver_string) &&
2634                (dv->driver_string[len] < 0x80) &&
2635                dv->driver_string[len])
2636                 len++;
2637         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2638                                        len, cmd_details);
2639
2640         return status;
2641 }
2642
2643 /**
2644  * i40e_get_link_status - get status of the HW network link
2645  * @hw: pointer to the hw struct
2646  * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown)
2647  *
2648  * Variable link_up TRUE if link is up, FALSE if link is down.
2649  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2650  *
2651  * Side effect: LinkStatusEvent reporting becomes enabled
2652  **/
2653 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2654 {
2655         enum i40e_status_code status = I40E_SUCCESS;
2656
2657         if (hw->phy.get_link_info) {
2658                 status = i40e_update_link_info(hw);
2659
2660                 if (status != I40E_SUCCESS)
2661                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2662                                    status);
2663         }
2664
2665         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2666
2667         return status;
2668 }
2669
2670 /**
2671  * i40e_updatelink_status - update status of the HW network link
2672  * @hw: pointer to the hw struct
2673  **/
2674 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2675 {
2676         struct i40e_aq_get_phy_abilities_resp abilities;
2677         enum i40e_status_code status = I40E_SUCCESS;
2678
2679         status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2680         if (status)
2681                 return status;
2682
2683         if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2684                 status = i40e_aq_get_phy_capabilities(hw, FALSE, false,
2685                                                       &abilities, NULL);
2686                 if (status)
2687                         return status;
2688
2689                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2690                         sizeof(hw->phy.link_info.module_type));
2691         }
2692         return status;
2693 }
2694
2695
2696 /**
2697  * i40e_get_link_speed
2698  * @hw: pointer to the hw struct
2699  *
2700  * Returns the link speed of the adapter.
2701  **/
2702 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2703 {
2704         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2705         enum i40e_status_code status = I40E_SUCCESS;
2706
2707         if (hw->phy.get_link_info) {
2708                 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2709
2710                 if (status != I40E_SUCCESS)
2711                         goto i40e_link_speed_exit;
2712         }
2713
2714         speed = hw->phy.link_info.link_speed;
2715
2716 i40e_link_speed_exit:
2717         return speed;
2718 }
2719
2720 /**
2721  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2722  * @hw: pointer to the hw struct
2723  * @uplink_seid: the MAC or other gizmo SEID
2724  * @downlink_seid: the VSI SEID
2725  * @enabled_tc: bitmap of TCs to be enabled
2726  * @default_port: TRUE for default port VSI, FALSE for control port
2727  * @veb_seid: pointer to where to put the resulting VEB SEID
2728  * @enable_stats: TRUE to turn on VEB stats
2729  * @cmd_details: pointer to command details structure or NULL
2730  *
2731  * This asks the FW to add a VEB between the uplink and downlink
2732  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2733  **/
2734 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2735                                 u16 downlink_seid, u8 enabled_tc,
2736                                 bool default_port, u16 *veb_seid,
2737                                 bool enable_stats,
2738                                 struct i40e_asq_cmd_details *cmd_details)
2739 {
2740         struct i40e_aq_desc desc;
2741         struct i40e_aqc_add_veb *cmd =
2742                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2743         struct i40e_aqc_add_veb_completion *resp =
2744                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2745         enum i40e_status_code status;
2746         u16 veb_flags = 0;
2747
2748         /* SEIDs need to either both be set or both be 0 for floating VEB */
2749         if (!!uplink_seid != !!downlink_seid)
2750                 return I40E_ERR_PARAM;
2751
2752         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2753
2754         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2755         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2756         cmd->enable_tcs = enabled_tc;
2757         if (!uplink_seid)
2758                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2759         if (default_port)
2760                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2761         else
2762                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2763
2764         /* reverse logic here: set the bitflag to disable the stats */
2765         if (!enable_stats)
2766                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2767
2768         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2769
2770         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2771
2772         if (!status && veb_seid)
2773                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2774
2775         return status;
2776 }
2777
2778 /**
2779  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2780  * @hw: pointer to the hw struct
2781  * @veb_seid: the SEID of the VEB to query
2782  * @switch_id: the uplink switch id
2783  * @floating: set to TRUE if the VEB is floating
2784  * @statistic_index: index of the stats counter block for this VEB
2785  * @vebs_used: number of VEB's used by function
2786  * @vebs_free: total VEB's not reserved by any function
2787  * @cmd_details: pointer to command details structure or NULL
2788  *
2789  * This retrieves the parameters for a particular VEB, specified by
2790  * uplink_seid, and returns them to the caller.
2791  **/
2792 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2793                                 u16 veb_seid, u16 *switch_id,
2794                                 bool *floating, u16 *statistic_index,
2795                                 u16 *vebs_used, u16 *vebs_free,
2796                                 struct i40e_asq_cmd_details *cmd_details)
2797 {
2798         struct i40e_aq_desc desc;
2799         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2800                 (struct i40e_aqc_get_veb_parameters_completion *)
2801                 &desc.params.raw;
2802         enum i40e_status_code status;
2803
2804         if (veb_seid == 0)
2805                 return I40E_ERR_PARAM;
2806
2807         i40e_fill_default_direct_cmd_desc(&desc,
2808                                           i40e_aqc_opc_get_veb_parameters);
2809         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2810
2811         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2812         if (status)
2813                 goto get_veb_exit;
2814
2815         if (switch_id)
2816                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2817         if (statistic_index)
2818                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2819         if (vebs_used)
2820                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2821         if (vebs_free)
2822                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2823         if (floating) {
2824                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2825
2826                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2827                         *floating = TRUE;
2828                 else
2829                         *floating = FALSE;
2830         }
2831
2832 get_veb_exit:
2833         return status;
2834 }
2835
2836 /**
2837  * i40e_aq_add_macvlan
2838  * @hw: pointer to the hw struct
2839  * @seid: VSI for the mac address
2840  * @mv_list: list of macvlans to be added
2841  * @count: length of the list
2842  * @cmd_details: pointer to command details structure or NULL
2843  *
2844  * Add MAC/VLAN addresses to the HW filtering
2845  **/
2846 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2847                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2848                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2849 {
2850         struct i40e_aq_desc desc;
2851         struct i40e_aqc_macvlan *cmd =
2852                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2853         enum i40e_status_code status;
2854         u16 buf_size;
2855         int i;
2856
2857         if (count == 0 || !mv_list || !hw)
2858                 return I40E_ERR_PARAM;
2859
2860         buf_size = count * sizeof(*mv_list);
2861
2862         /* prep the rest of the request */
2863         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2864         cmd->num_addresses = CPU_TO_LE16(count);
2865         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2866         cmd->seid[1] = 0;
2867         cmd->seid[2] = 0;
2868
2869         for (i = 0; i < count; i++)
2870                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2871                         mv_list[i].flags |=
2872                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2873
2874         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2875         if (buf_size > I40E_AQ_LARGE_BUF)
2876                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2877
2878         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2879                                        cmd_details);
2880
2881         return status;
2882 }
2883
2884 /**
2885  * i40e_aq_remove_macvlan
2886  * @hw: pointer to the hw struct
2887  * @seid: VSI for the mac address
2888  * @mv_list: list of macvlans to be removed
2889  * @count: length of the list
2890  * @cmd_details: pointer to command details structure or NULL
2891  *
2892  * Remove MAC/VLAN addresses from the HW filtering
2893  **/
2894 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2895                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2896                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2897 {
2898         struct i40e_aq_desc desc;
2899         struct i40e_aqc_macvlan *cmd =
2900                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2901         enum i40e_status_code status;
2902         u16 buf_size;
2903
2904         if (count == 0 || !mv_list || !hw)
2905                 return I40E_ERR_PARAM;
2906
2907         buf_size = count * sizeof(*mv_list);
2908
2909         /* prep the rest of the request */
2910         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2911         cmd->num_addresses = CPU_TO_LE16(count);
2912         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2913         cmd->seid[1] = 0;
2914         cmd->seid[2] = 0;
2915
2916         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2917         if (buf_size > I40E_AQ_LARGE_BUF)
2918                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2919
2920         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2921                                        cmd_details);
2922
2923         return status;
2924 }
2925
2926 /**
2927  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2928  * @hw: pointer to the hw struct
2929  * @opcode: AQ opcode for add or delete mirror rule
2930  * @sw_seid: Switch SEID (to which rule refers)
2931  * @rule_type: Rule Type (ingress/egress/VLAN)
2932  * @id: Destination VSI SEID or Rule ID
2933  * @count: length of the list
2934  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2935  * @cmd_details: pointer to command details structure or NULL
2936  * @rule_id: Rule ID returned from FW
2937  * @rule_used: Number of rules used in internal switch
2938  * @rule_free: Number of rules free in internal switch
2939  *
2940  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2941  * VEBs/VEPA elements only
2942  **/
2943 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
2944                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2945                         u16 count, __le16 *mr_list,
2946                         struct i40e_asq_cmd_details *cmd_details,
2947                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2948 {
2949         struct i40e_aq_desc desc;
2950         struct i40e_aqc_add_delete_mirror_rule *cmd =
2951                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2952         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2953         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2954         enum i40e_status_code status;
2955         u16 buf_size;
2956
2957         buf_size = count * sizeof(*mr_list);
2958
2959         /* prep the rest of the request */
2960         i40e_fill_default_direct_cmd_desc(&desc, opcode);
2961         cmd->seid = CPU_TO_LE16(sw_seid);
2962         cmd->rule_type = CPU_TO_LE16(rule_type &
2963                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
2964         cmd->num_entries = CPU_TO_LE16(count);
2965         /* Dest VSI for add, rule_id for delete */
2966         cmd->destination = CPU_TO_LE16(id);
2967         if (mr_list) {
2968                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2969                                                 I40E_AQ_FLAG_RD));
2970                 if (buf_size > I40E_AQ_LARGE_BUF)
2971                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2972         }
2973
2974         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2975                                        cmd_details);
2976         if (status == I40E_SUCCESS ||
2977             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2978                 if (rule_id)
2979                         *rule_id = LE16_TO_CPU(resp->rule_id);
2980                 if (rules_used)
2981                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
2982                 if (rules_free)
2983                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
2984         }
2985         return status;
2986 }
2987
2988 /**
2989  * i40e_aq_add_mirrorrule - add a mirror rule
2990  * @hw: pointer to the hw struct
2991  * @sw_seid: Switch SEID (to which rule refers)
2992  * @rule_type: Rule Type (ingress/egress/VLAN)
2993  * @dest_vsi: SEID of VSI to which packets will be mirrored
2994  * @count: length of the list
2995  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2996  * @cmd_details: pointer to command details structure or NULL
2997  * @rule_id: Rule ID returned from FW
2998  * @rule_used: Number of rules used in internal switch
2999  * @rule_free: Number of rules free in internal switch
3000  *
3001  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3002  **/
3003 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3004                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3005                         struct i40e_asq_cmd_details *cmd_details,
3006                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3007 {
3008         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3009             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3010                 if (count == 0 || !mr_list)
3011                         return I40E_ERR_PARAM;
3012         }
3013
3014         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3015                                   rule_type, dest_vsi, count, mr_list,
3016                                   cmd_details, rule_id, rules_used, rules_free);
3017 }
3018
3019 /**
3020  * i40e_aq_delete_mirrorrule - delete a mirror rule
3021  * @hw: pointer to the hw struct
3022  * @sw_seid: Switch SEID (to which rule refers)
3023  * @rule_type: Rule Type (ingress/egress/VLAN)
3024  * @count: length of the list
3025  * @rule_id: Rule ID that is returned in the receive desc as part of
3026  *              add_mirrorrule.
3027  * @mr_list: list of mirrored VLAN IDs to be removed
3028  * @cmd_details: pointer to command details structure or NULL
3029  * @rule_used: Number of rules used in internal switch
3030  * @rule_free: Number of rules free in internal switch
3031  *
3032  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3033  **/
3034 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3035                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3036                         struct i40e_asq_cmd_details *cmd_details,
3037                         u16 *rules_used, u16 *rules_free)
3038 {
3039         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3040         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3041                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3042                  * mirroring. For other rule_type, count and rule_type should
3043                  * not matter.
3044                  */
3045                 if (count == 0 || !mr_list)
3046                         return I40E_ERR_PARAM;
3047         }
3048
3049         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3050                                   rule_type, rule_id, count, mr_list,
3051                                   cmd_details, NULL, rules_used, rules_free);
3052 }
3053
3054 /**
3055  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3056  * @hw: pointer to the hw struct
3057  * @seid: VSI for the vlan filters
3058  * @v_list: list of vlan filters to be added
3059  * @count: length of the list
3060  * @cmd_details: pointer to command details structure or NULL
3061  **/
3062 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3063                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3064                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3065 {
3066         struct i40e_aq_desc desc;
3067         struct i40e_aqc_macvlan *cmd =
3068                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3069         enum i40e_status_code status;
3070         u16 buf_size;
3071
3072         if (count == 0 || !v_list || !hw)
3073                 return I40E_ERR_PARAM;
3074
3075         buf_size = count * sizeof(*v_list);
3076
3077         /* prep the rest of the request */
3078         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3079         cmd->num_addresses = CPU_TO_LE16(count);
3080         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3081         cmd->seid[1] = 0;
3082         cmd->seid[2] = 0;
3083
3084         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3085         if (buf_size > I40E_AQ_LARGE_BUF)
3086                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3087
3088         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3089                                        cmd_details);
3090
3091         return status;
3092 }
3093
3094 /**
3095  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3096  * @hw: pointer to the hw struct
3097  * @seid: VSI for the vlan filters
3098  * @v_list: list of macvlans to be removed
3099  * @count: length of the list
3100  * @cmd_details: pointer to command details structure or NULL
3101  **/
3102 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3103                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3104                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3105 {
3106         struct i40e_aq_desc desc;
3107         struct i40e_aqc_macvlan *cmd =
3108                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3109         enum i40e_status_code status;
3110         u16 buf_size;
3111
3112         if (count == 0 || !v_list || !hw)
3113                 return I40E_ERR_PARAM;
3114
3115         buf_size = count * sizeof(*v_list);
3116
3117         /* prep the rest of the request */
3118         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3119         cmd->num_addresses = CPU_TO_LE16(count);
3120         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3121         cmd->seid[1] = 0;
3122         cmd->seid[2] = 0;
3123
3124         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3125         if (buf_size > I40E_AQ_LARGE_BUF)
3126                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3127
3128         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3129                                        cmd_details);
3130
3131         return status;
3132 }
3133
3134 /**
3135  * i40e_aq_send_msg_to_vf
3136  * @hw: pointer to the hardware structure
3137  * @vfid: vf id to send msg
3138  * @v_opcode: opcodes for VF-PF communication
3139  * @v_retval: return error code
3140  * @msg: pointer to the msg buffer
3141  * @msglen: msg length
3142  * @cmd_details: pointer to command details
3143  *
3144  * send msg to vf
3145  **/
3146 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3147                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3148                                 struct i40e_asq_cmd_details *cmd_details)
3149 {
3150         struct i40e_aq_desc desc;
3151         struct i40e_aqc_pf_vf_message *cmd =
3152                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3153         enum i40e_status_code status;
3154
3155         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3156         cmd->id = CPU_TO_LE32(vfid);
3157         desc.cookie_high = CPU_TO_LE32(v_opcode);
3158         desc.cookie_low = CPU_TO_LE32(v_retval);
3159         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3160         if (msglen) {
3161                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3162                                                 I40E_AQ_FLAG_RD));
3163                 if (msglen > I40E_AQ_LARGE_BUF)
3164                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3165                 desc.datalen = CPU_TO_LE16(msglen);
3166         }
3167         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3168
3169         return status;
3170 }
3171
3172 /**
3173  * i40e_aq_debug_read_register
3174  * @hw: pointer to the hw struct
3175  * @reg_addr: register address
3176  * @reg_val: register value
3177  * @cmd_details: pointer to command details structure or NULL
3178  *
3179  * Read the register using the admin queue commands
3180  **/
3181 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3182                                 u32 reg_addr, u64 *reg_val,
3183                                 struct i40e_asq_cmd_details *cmd_details)
3184 {
3185         struct i40e_aq_desc desc;
3186         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3187                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3188         enum i40e_status_code status;
3189
3190         if (reg_val == NULL)
3191                 return I40E_ERR_PARAM;
3192
3193         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3194
3195         cmd_resp->address = CPU_TO_LE32(reg_addr);
3196
3197         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3198
3199         if (status == I40E_SUCCESS) {
3200                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3201                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3202         }
3203
3204         return status;
3205 }
3206
3207 /**
3208  * i40e_aq_debug_write_register
3209  * @hw: pointer to the hw struct
3210  * @reg_addr: register address
3211  * @reg_val: register value
3212  * @cmd_details: pointer to command details structure or NULL
3213  *
3214  * Write to a register using the admin queue commands
3215  **/
3216 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3217                                 u32 reg_addr, u64 reg_val,
3218                                 struct i40e_asq_cmd_details *cmd_details)
3219 {
3220         struct i40e_aq_desc desc;
3221         struct i40e_aqc_debug_reg_read_write *cmd =
3222                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3223         enum i40e_status_code status;
3224
3225         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3226
3227         cmd->address = CPU_TO_LE32(reg_addr);
3228         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3229         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3230
3231         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3232
3233         return status;
3234 }
3235
3236 /**
3237  * i40e_aq_request_resource
3238  * @hw: pointer to the hw struct
3239  * @resource: resource id
3240  * @access: access type
3241  * @sdp_number: resource number
3242  * @timeout: the maximum time in ms that the driver may hold the resource
3243  * @cmd_details: pointer to command details structure or NULL
3244  *
3245  * requests common resource using the admin queue commands
3246  **/
3247 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3248                                 enum i40e_aq_resources_ids resource,
3249                                 enum i40e_aq_resource_access_type access,
3250                                 u8 sdp_number, u64 *timeout,
3251                                 struct i40e_asq_cmd_details *cmd_details)
3252 {
3253         struct i40e_aq_desc desc;
3254         struct i40e_aqc_request_resource *cmd_resp =
3255                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3256         enum i40e_status_code status;
3257
3258         DEBUGFUNC("i40e_aq_request_resource");
3259
3260         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3261
3262         cmd_resp->resource_id = CPU_TO_LE16(resource);
3263         cmd_resp->access_type = CPU_TO_LE16(access);
3264         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3265
3266         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3267         /* The completion specifies the maximum time in ms that the driver
3268          * may hold the resource in the Timeout field.
3269          * If the resource is held by someone else, the command completes with
3270          * busy return value and the timeout field indicates the maximum time
3271          * the current owner of the resource has to free it.
3272          */
3273         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3274                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3275
3276         return status;
3277 }
3278
3279 /**
3280  * i40e_aq_release_resource
3281  * @hw: pointer to the hw struct
3282  * @resource: resource id
3283  * @sdp_number: resource number
3284  * @cmd_details: pointer to command details structure or NULL
3285  *
3286  * release common resource using the admin queue commands
3287  **/
3288 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3289                                 enum i40e_aq_resources_ids resource,
3290                                 u8 sdp_number,
3291                                 struct i40e_asq_cmd_details *cmd_details)
3292 {
3293         struct i40e_aq_desc desc;
3294         struct i40e_aqc_request_resource *cmd =
3295                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3296         enum i40e_status_code status;
3297
3298         DEBUGFUNC("i40e_aq_release_resource");
3299
3300         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3301
3302         cmd->resource_id = CPU_TO_LE16(resource);
3303         cmd->resource_number = CPU_TO_LE32(sdp_number);
3304
3305         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3306
3307         return status;
3308 }
3309
3310 /**
3311  * i40e_aq_read_nvm
3312  * @hw: pointer to the hw struct
3313  * @module_pointer: module pointer location in words from the NVM beginning
3314  * @offset: byte offset from the module beginning
3315  * @length: length of the section to be read (in bytes from the offset)
3316  * @data: command buffer (size [bytes] = length)
3317  * @last_command: tells if this is the last command in a series
3318  * @cmd_details: pointer to command details structure or NULL
3319  *
3320  * Read the NVM using the admin queue commands
3321  **/
3322 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3323                                 u32 offset, u16 length, void *data,
3324                                 bool last_command,
3325                                 struct i40e_asq_cmd_details *cmd_details)
3326 {
3327         struct i40e_aq_desc desc;
3328         struct i40e_aqc_nvm_update *cmd =
3329                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3330         enum i40e_status_code status;
3331
3332         DEBUGFUNC("i40e_aq_read_nvm");
3333
3334         /* In offset the highest byte must be zeroed. */
3335         if (offset & 0xFF000000) {
3336                 status = I40E_ERR_PARAM;
3337                 goto i40e_aq_read_nvm_exit;
3338         }
3339
3340         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3341
3342         /* If this is the last command in a series, set the proper flag. */
3343         if (last_command)
3344                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3345         cmd->module_pointer = module_pointer;
3346         cmd->offset = CPU_TO_LE32(offset);
3347         cmd->length = CPU_TO_LE16(length);
3348
3349         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3350         if (length > I40E_AQ_LARGE_BUF)
3351                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3352
3353         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3354
3355 i40e_aq_read_nvm_exit:
3356         return status;
3357 }
3358
3359 /**
3360  * i40e_aq_read_nvm_config - read an nvm config block
3361  * @hw: pointer to the hw struct
3362  * @cmd_flags: NVM access admin command bits
3363  * @field_id: field or feature id
3364  * @data: buffer for result
3365  * @buf_size: buffer size
3366  * @element_count: pointer to count of elements read by FW
3367  * @cmd_details: pointer to command details structure or NULL
3368  **/
3369 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3370                                 u8 cmd_flags, u32 field_id, void *data,
3371                                 u16 buf_size, u16 *element_count,
3372                                 struct i40e_asq_cmd_details *cmd_details)
3373 {
3374         struct i40e_aq_desc desc;
3375         struct i40e_aqc_nvm_config_read *cmd =
3376                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3377         enum i40e_status_code status;
3378
3379         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3380         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3381         if (buf_size > I40E_AQ_LARGE_BUF)
3382                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3383
3384         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3385         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3386         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3387                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3388         else
3389                 cmd->element_id_msw = 0;
3390
3391         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3392
3393         if (!status && element_count)
3394                 *element_count = LE16_TO_CPU(cmd->element_count);
3395
3396         return status;
3397 }
3398
3399 /**
3400  * i40e_aq_write_nvm_config - write an nvm config block
3401  * @hw: pointer to the hw struct
3402  * @cmd_flags: NVM access admin command bits
3403  * @data: buffer for result
3404  * @buf_size: buffer size
3405  * @element_count: count of elements to be written
3406  * @cmd_details: pointer to command details structure or NULL
3407  **/
3408 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3409                                 u8 cmd_flags, void *data, u16 buf_size,
3410                                 u16 element_count,
3411                                 struct i40e_asq_cmd_details *cmd_details)
3412 {
3413         struct i40e_aq_desc desc;
3414         struct i40e_aqc_nvm_config_write *cmd =
3415                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3416         enum i40e_status_code status;
3417
3418         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3419         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3420         if (buf_size > I40E_AQ_LARGE_BUF)
3421                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3422
3423         cmd->element_count = CPU_TO_LE16(element_count);
3424         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3425         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3426
3427         return status;
3428 }
3429
3430 /**
3431  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3432  * @hw: pointer to the hw struct
3433  * @cmd_details: pointer to command details structure or NULL
3434  **/
3435 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3436                                 void *buff, u16 buff_size,
3437                                 struct i40e_asq_cmd_details *cmd_details)
3438 {
3439         struct i40e_aq_desc desc;
3440         enum i40e_status_code status;
3441
3442
3443         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3444         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3445         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3446                 status = I40E_ERR_NOT_IMPLEMENTED;
3447
3448         return status;
3449 }
3450
3451 /**
3452  * i40e_aq_erase_nvm
3453  * @hw: pointer to the hw struct
3454  * @module_pointer: module pointer location in words from the NVM beginning
3455  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3456  * @length: length of the section to be erased (expressed in 4 KB)
3457  * @last_command: tells if this is the last command in a series
3458  * @cmd_details: pointer to command details structure or NULL
3459  *
3460  * Erase the NVM sector using the admin queue commands
3461  **/
3462 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3463                                 u32 offset, u16 length, bool last_command,
3464                                 struct i40e_asq_cmd_details *cmd_details)
3465 {
3466         struct i40e_aq_desc desc;
3467         struct i40e_aqc_nvm_update *cmd =
3468                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3469         enum i40e_status_code status;
3470
3471         DEBUGFUNC("i40e_aq_erase_nvm");
3472
3473         /* In offset the highest byte must be zeroed. */
3474         if (offset & 0xFF000000) {
3475                 status = I40E_ERR_PARAM;
3476                 goto i40e_aq_erase_nvm_exit;
3477         }
3478
3479         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3480
3481         /* If this is the last command in a series, set the proper flag. */
3482         if (last_command)
3483                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3484         cmd->module_pointer = module_pointer;
3485         cmd->offset = CPU_TO_LE32(offset);
3486         cmd->length = CPU_TO_LE16(length);
3487
3488         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3489
3490 i40e_aq_erase_nvm_exit:
3491         return status;
3492 }
3493
3494 /**
3495  * i40e_parse_discover_capabilities
3496  * @hw: pointer to the hw struct
3497  * @buff: pointer to a buffer containing device/function capability records
3498  * @cap_count: number of capability records in the list
3499  * @list_type_opc: type of capabilities list to parse
3500  *
3501  * Parse the device/function capabilities list.
3502  **/
3503 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3504                                      u32 cap_count,
3505                                      enum i40e_admin_queue_opc list_type_opc)
3506 {
3507         struct i40e_aqc_list_capabilities_element_resp *cap;
3508         u32 valid_functions, num_functions;
3509         u32 number, logical_id, phys_id;
3510         struct i40e_hw_capabilities *p;
3511         u8 major_rev;
3512         u32 i = 0;
3513         u16 id;
3514
3515         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3516
3517         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3518                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3519         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3520                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3521         else
3522                 return;
3523
3524         for (i = 0; i < cap_count; i++, cap++) {
3525                 id = LE16_TO_CPU(cap->id);
3526                 number = LE32_TO_CPU(cap->number);
3527                 logical_id = LE32_TO_CPU(cap->logical_id);
3528                 phys_id = LE32_TO_CPU(cap->phys_id);
3529                 major_rev = cap->major_rev;
3530
3531                 switch (id) {
3532                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3533                         p->switch_mode = number;
3534                         i40e_debug(hw, I40E_DEBUG_INIT,
3535                                    "HW Capability: Switch mode = %d\n",
3536                                    p->switch_mode);
3537                         break;
3538                 case I40E_AQ_CAP_ID_MNG_MODE:
3539                         p->management_mode = number;
3540                         i40e_debug(hw, I40E_DEBUG_INIT,
3541                                    "HW Capability: Management Mode = %d\n",
3542                                    p->management_mode);
3543                         break;
3544                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3545                         p->npar_enable = number;
3546                         i40e_debug(hw, I40E_DEBUG_INIT,
3547                                    "HW Capability: NPAR enable = %d\n",
3548                                    p->npar_enable);
3549                         break;
3550                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3551                         p->os2bmc = number;
3552                         i40e_debug(hw, I40E_DEBUG_INIT,
3553                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3554                         break;
3555                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3556                         p->valid_functions = number;
3557                         i40e_debug(hw, I40E_DEBUG_INIT,
3558                                    "HW Capability: Valid Functions = %d\n",
3559                                    p->valid_functions);
3560                         break;
3561                 case I40E_AQ_CAP_ID_SRIOV:
3562                         if (number == 1)
3563                                 p->sr_iov_1_1 = TRUE;
3564                         i40e_debug(hw, I40E_DEBUG_INIT,
3565                                    "HW Capability: SR-IOV = %d\n",
3566                                    p->sr_iov_1_1);
3567                         break;
3568                 case I40E_AQ_CAP_ID_VF:
3569                         p->num_vfs = number;
3570                         p->vf_base_id = logical_id;
3571                         i40e_debug(hw, I40E_DEBUG_INIT,
3572                                    "HW Capability: VF count = %d\n",
3573                                    p->num_vfs);
3574                         i40e_debug(hw, I40E_DEBUG_INIT,
3575                                    "HW Capability: VF base_id = %d\n",
3576                                    p->vf_base_id);
3577                         break;
3578                 case I40E_AQ_CAP_ID_VMDQ:
3579                         if (number == 1)
3580                                 p->vmdq = TRUE;
3581                         i40e_debug(hw, I40E_DEBUG_INIT,
3582                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3583                         break;
3584                 case I40E_AQ_CAP_ID_8021QBG:
3585                         if (number == 1)
3586                                 p->evb_802_1_qbg = TRUE;
3587                         i40e_debug(hw, I40E_DEBUG_INIT,
3588                                    "HW Capability: 802.1Qbg = %d\n", number);
3589                         break;
3590                 case I40E_AQ_CAP_ID_8021QBR:
3591                         if (number == 1)
3592                                 p->evb_802_1_qbh = TRUE;
3593                         i40e_debug(hw, I40E_DEBUG_INIT,
3594                                    "HW Capability: 802.1Qbh = %d\n", number);
3595                         break;
3596                 case I40E_AQ_CAP_ID_VSI:
3597                         p->num_vsis = number;
3598                         i40e_debug(hw, I40E_DEBUG_INIT,
3599                                    "HW Capability: VSI count = %d\n",
3600                                    p->num_vsis);
3601                         break;
3602                 case I40E_AQ_CAP_ID_DCB:
3603                         if (number == 1) {
3604                                 p->dcb = TRUE;
3605                                 p->enabled_tcmap = logical_id;
3606                                 p->maxtc = phys_id;
3607                         }
3608                         i40e_debug(hw, I40E_DEBUG_INIT,
3609                                    "HW Capability: DCB = %d\n", p->dcb);
3610                         i40e_debug(hw, I40E_DEBUG_INIT,
3611                                    "HW Capability: TC Mapping = %d\n",
3612                                    logical_id);
3613                         i40e_debug(hw, I40E_DEBUG_INIT,
3614                                    "HW Capability: TC Max = %d\n", p->maxtc);
3615                         break;
3616                 case I40E_AQ_CAP_ID_FCOE:
3617                         if (number == 1)
3618                                 p->fcoe = TRUE;
3619                         i40e_debug(hw, I40E_DEBUG_INIT,
3620                                    "HW Capability: FCOE = %d\n", p->fcoe);
3621                         break;
3622                 case I40E_AQ_CAP_ID_ISCSI:
3623                         if (number == 1)
3624                                 p->iscsi = TRUE;
3625                         i40e_debug(hw, I40E_DEBUG_INIT,
3626                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3627                         break;
3628                 case I40E_AQ_CAP_ID_RSS:
3629                         p->rss = TRUE;
3630                         p->rss_table_size = number;
3631                         p->rss_table_entry_width = logical_id;
3632                         i40e_debug(hw, I40E_DEBUG_INIT,
3633                                    "HW Capability: RSS = %d\n", p->rss);
3634                         i40e_debug(hw, I40E_DEBUG_INIT,
3635                                    "HW Capability: RSS table size = %d\n",
3636                                    p->rss_table_size);
3637                         i40e_debug(hw, I40E_DEBUG_INIT,
3638                                    "HW Capability: RSS table width = %d\n",
3639                                    p->rss_table_entry_width);
3640                         break;
3641                 case I40E_AQ_CAP_ID_RXQ:
3642                         p->num_rx_qp = number;
3643                         p->base_queue = phys_id;
3644                         i40e_debug(hw, I40E_DEBUG_INIT,
3645                                    "HW Capability: Rx QP = %d\n", number);
3646                         i40e_debug(hw, I40E_DEBUG_INIT,
3647                                    "HW Capability: base_queue = %d\n",
3648                                    p->base_queue);
3649                         break;
3650                 case I40E_AQ_CAP_ID_TXQ:
3651                         p->num_tx_qp = number;
3652                         p->base_queue = phys_id;
3653                         i40e_debug(hw, I40E_DEBUG_INIT,
3654                                    "HW Capability: Tx QP = %d\n", number);
3655                         i40e_debug(hw, I40E_DEBUG_INIT,
3656                                    "HW Capability: base_queue = %d\n",
3657                                    p->base_queue);
3658                         break;
3659                 case I40E_AQ_CAP_ID_MSIX:
3660                         p->num_msix_vectors = number;
3661                         i40e_debug(hw, I40E_DEBUG_INIT,
3662                                    "HW Capability: MSIX vector count = %d\n",
3663                                    p->num_msix_vectors);
3664                         break;
3665                 case I40E_AQ_CAP_ID_VF_MSIX:
3666                         p->num_msix_vectors_vf = number;
3667                         i40e_debug(hw, I40E_DEBUG_INIT,
3668                                    "HW Capability: MSIX VF vector count = %d\n",
3669                                    p->num_msix_vectors_vf);
3670                         break;
3671                 case I40E_AQ_CAP_ID_FLEX10:
3672                         if (major_rev == 1) {
3673                                 if (number == 1) {
3674                                         p->flex10_enable = TRUE;
3675                                         p->flex10_capable = TRUE;
3676                                 }
3677                         } else {
3678                                 /* Capability revision >= 2 */
3679                                 if (number & 1)
3680                                         p->flex10_enable = TRUE;
3681                                 if (number & 2)
3682                                         p->flex10_capable = TRUE;
3683                         }
3684                         p->flex10_mode = logical_id;
3685                         p->flex10_status = phys_id;
3686                         i40e_debug(hw, I40E_DEBUG_INIT,
3687                                    "HW Capability: Flex10 mode = %d\n",
3688                                    p->flex10_mode);
3689                         i40e_debug(hw, I40E_DEBUG_INIT,
3690                                    "HW Capability: Flex10 status = %d\n",
3691                                    p->flex10_status);
3692                         break;
3693                 case I40E_AQ_CAP_ID_CEM:
3694                         if (number == 1)
3695                                 p->mgmt_cem = TRUE;
3696                         i40e_debug(hw, I40E_DEBUG_INIT,
3697                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3698                         break;
3699                 case I40E_AQ_CAP_ID_IWARP:
3700                         if (number == 1)
3701                                 p->iwarp = TRUE;
3702                         i40e_debug(hw, I40E_DEBUG_INIT,
3703                                    "HW Capability: iWARP = %d\n", p->iwarp);
3704                         break;
3705                 case I40E_AQ_CAP_ID_LED:
3706                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3707                                 p->led[phys_id] = TRUE;
3708                         i40e_debug(hw, I40E_DEBUG_INIT,
3709                                    "HW Capability: LED - PIN %d\n", phys_id);
3710                         break;
3711                 case I40E_AQ_CAP_ID_SDP:
3712                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3713                                 p->sdp[phys_id] = TRUE;
3714                         i40e_debug(hw, I40E_DEBUG_INIT,
3715                                    "HW Capability: SDP - PIN %d\n", phys_id);
3716                         break;
3717                 case I40E_AQ_CAP_ID_MDIO:
3718                         if (number == 1) {
3719                                 p->mdio_port_num = phys_id;
3720                                 p->mdio_port_mode = logical_id;
3721                         }
3722                         i40e_debug(hw, I40E_DEBUG_INIT,
3723                                    "HW Capability: MDIO port number = %d\n",
3724                                    p->mdio_port_num);
3725                         i40e_debug(hw, I40E_DEBUG_INIT,
3726                                    "HW Capability: MDIO port mode = %d\n",
3727                                    p->mdio_port_mode);
3728                         break;
3729                 case I40E_AQ_CAP_ID_1588:
3730                         if (number == 1)
3731                                 p->ieee_1588 = TRUE;
3732                         i40e_debug(hw, I40E_DEBUG_INIT,
3733                                    "HW Capability: IEEE 1588 = %d\n",
3734                                    p->ieee_1588);
3735                         break;
3736                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3737                         p->fd = TRUE;
3738                         p->fd_filters_guaranteed = number;
3739                         p->fd_filters_best_effort = logical_id;
3740                         i40e_debug(hw, I40E_DEBUG_INIT,
3741                                    "HW Capability: Flow Director = 1\n");
3742                         i40e_debug(hw, I40E_DEBUG_INIT,
3743                                    "HW Capability: Guaranteed FD filters = %d\n",
3744                                    p->fd_filters_guaranteed);
3745                         break;
3746                 case I40E_AQ_CAP_ID_WSR_PROT:
3747                         p->wr_csr_prot = (u64)number;
3748                         p->wr_csr_prot |= (u64)logical_id << 32;
3749                         i40e_debug(hw, I40E_DEBUG_INIT,
3750                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3751                                    (p->wr_csr_prot & 0xffff));
3752                         break;
3753                 case I40E_AQ_CAP_ID_NVM_MGMT:
3754                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3755                                 p->sec_rev_disabled = TRUE;
3756                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3757                                 p->update_disabled = TRUE;
3758                         break;
3759                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3760                         hw->num_wol_proxy_filters = (u16)number;
3761                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3762                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3763                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3764                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3765                         else
3766                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3767                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3768                         p->proxy_support = p->proxy_support;
3769                         i40e_debug(hw, I40E_DEBUG_INIT,
3770                                    "HW Capability: WOL proxy filters = %d\n",
3771                                    hw->num_wol_proxy_filters);
3772                         break;
3773                 default:
3774                         break;
3775                 }
3776         }
3777
3778         if (p->fcoe)
3779                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3780
3781         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3782         p->fcoe = FALSE;
3783
3784         /* count the enabled ports (aka the "not disabled" ports) */
3785         hw->num_ports = 0;
3786         for (i = 0; i < 4; i++) {
3787                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3788                 u64 port_cfg = 0;
3789
3790                 /* use AQ read to get the physical register offset instead
3791                  * of the port relative offset
3792                  */
3793                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3794                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3795                         hw->num_ports++;
3796         }
3797
3798         valid_functions = p->valid_functions;
3799         num_functions = 0;
3800         while (valid_functions) {
3801                 if (valid_functions & 1)
3802                         num_functions++;
3803                 valid_functions >>= 1;
3804         }
3805
3806         /* partition id is 1-based, and functions are evenly spread
3807          * across the ports as partitions
3808          */
3809         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3810         hw->num_partitions = num_functions / hw->num_ports;
3811
3812         /* additional HW specific goodies that might
3813          * someday be HW version specific
3814          */
3815         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3816 }
3817
3818 /**
3819  * i40e_aq_discover_capabilities
3820  * @hw: pointer to the hw struct
3821  * @buff: a virtual buffer to hold the capabilities
3822  * @buff_size: Size of the virtual buffer
3823  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3824  * @list_type_opc: capabilities type to discover - pass in the command opcode
3825  * @cmd_details: pointer to command details structure or NULL
3826  *
3827  * Get the device capabilities descriptions from the firmware
3828  **/
3829 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3830                                 void *buff, u16 buff_size, u16 *data_size,
3831                                 enum i40e_admin_queue_opc list_type_opc,
3832                                 struct i40e_asq_cmd_details *cmd_details)
3833 {
3834         struct i40e_aqc_list_capabilites *cmd;
3835         struct i40e_aq_desc desc;
3836         enum i40e_status_code status = I40E_SUCCESS;
3837
3838         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3839
3840         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3841                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3842                 status = I40E_ERR_PARAM;
3843                 goto exit;
3844         }
3845
3846         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3847
3848         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3849         if (buff_size > I40E_AQ_LARGE_BUF)
3850                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3851
3852         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3853         *data_size = LE16_TO_CPU(desc.datalen);
3854
3855         if (status)
3856                 goto exit;
3857
3858         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3859                                          list_type_opc);
3860
3861 exit:
3862         return status;
3863 }
3864
3865 /**
3866  * i40e_aq_update_nvm
3867  * @hw: pointer to the hw struct
3868  * @module_pointer: module pointer location in words from the NVM beginning
3869  * @offset: byte offset from the module beginning
3870  * @length: length of the section to be written (in bytes from the offset)
3871  * @data: command buffer (size [bytes] = length)
3872  * @last_command: tells if this is the last command in a series
3873  * @cmd_details: pointer to command details structure or NULL
3874  *
3875  * Update the NVM using the admin queue commands
3876  **/
3877 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3878                                 u32 offset, u16 length, void *data,
3879                                 bool last_command,
3880                                 struct i40e_asq_cmd_details *cmd_details)
3881 {
3882         struct i40e_aq_desc desc;
3883         struct i40e_aqc_nvm_update *cmd =
3884                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3885         enum i40e_status_code status;
3886
3887         DEBUGFUNC("i40e_aq_update_nvm");
3888
3889         /* In offset the highest byte must be zeroed. */
3890         if (offset & 0xFF000000) {
3891                 status = I40E_ERR_PARAM;
3892                 goto i40e_aq_update_nvm_exit;
3893         }
3894
3895         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3896
3897         /* If this is the last command in a series, set the proper flag. */
3898         if (last_command)
3899                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3900         cmd->module_pointer = module_pointer;
3901         cmd->offset = CPU_TO_LE32(offset);
3902         cmd->length = CPU_TO_LE16(length);
3903
3904         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3905         if (length > I40E_AQ_LARGE_BUF)
3906                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3907
3908         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3909
3910 i40e_aq_update_nvm_exit:
3911         return status;
3912 }
3913
3914 /**
3915  * i40e_aq_get_lldp_mib
3916  * @hw: pointer to the hw struct
3917  * @bridge_type: type of bridge requested
3918  * @mib_type: Local, Remote or both Local and Remote MIBs
3919  * @buff: pointer to a user supplied buffer to store the MIB block
3920  * @buff_size: size of the buffer (in bytes)
3921  * @local_len : length of the returned Local LLDP MIB
3922  * @remote_len: length of the returned Remote LLDP MIB
3923  * @cmd_details: pointer to command details structure or NULL
3924  *
3925  * Requests the complete LLDP MIB (entire packet).
3926  **/
3927 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3928                                 u8 mib_type, void *buff, u16 buff_size,
3929                                 u16 *local_len, u16 *remote_len,
3930                                 struct i40e_asq_cmd_details *cmd_details)
3931 {
3932         struct i40e_aq_desc desc;
3933         struct i40e_aqc_lldp_get_mib *cmd =
3934                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3935         struct i40e_aqc_lldp_get_mib *resp =
3936                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3937         enum i40e_status_code status;
3938
3939         if (buff_size == 0 || !buff)
3940                 return I40E_ERR_PARAM;
3941
3942         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3943         /* Indirect Command */
3944         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3945
3946         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3947         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3948                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3949
3950         desc.datalen = CPU_TO_LE16(buff_size);
3951
3952         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3953         if (buff_size > I40E_AQ_LARGE_BUF)
3954                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3955
3956         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3957         if (!status) {
3958                 if (local_len != NULL)
3959                         *local_len = LE16_TO_CPU(resp->local_len);
3960                 if (remote_len != NULL)
3961                         *remote_len = LE16_TO_CPU(resp->remote_len);
3962         }
3963
3964         return status;
3965 }
3966
3967  /**
3968  * i40e_aq_set_lldp_mib - Set the LLDP MIB
3969  * @hw: pointer to the hw struct
3970  * @mib_type: Local, Remote or both Local and Remote MIBs
3971  * @buff: pointer to a user supplied buffer to store the MIB block
3972  * @buff_size: size of the buffer (in bytes)
3973  * @cmd_details: pointer to command details structure or NULL
3974  *
3975  * Set the LLDP MIB.
3976  **/
3977 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3978                                 u8 mib_type, void *buff, u16 buff_size,
3979                                 struct i40e_asq_cmd_details *cmd_details)
3980 {
3981         struct i40e_aq_desc desc;
3982         struct i40e_aqc_lldp_set_local_mib *cmd =
3983                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3984         enum i40e_status_code status;
3985
3986         if (buff_size == 0 || !buff)
3987                 return I40E_ERR_PARAM;
3988
3989         i40e_fill_default_direct_cmd_desc(&desc,
3990                                 i40e_aqc_opc_lldp_set_local_mib);
3991         /* Indirect Command */
3992         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3993         if (buff_size > I40E_AQ_LARGE_BUF)
3994                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3995         desc.datalen = CPU_TO_LE16(buff_size);
3996
3997         cmd->type = mib_type;
3998         cmd->length = CPU_TO_LE16(buff_size);
3999         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4000         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4001
4002         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4003         return status;
4004 }
4005
4006 /**
4007  * i40e_aq_cfg_lldp_mib_change_event
4008  * @hw: pointer to the hw struct
4009  * @enable_update: Enable or Disable event posting
4010  * @cmd_details: pointer to command details structure or NULL
4011  *
4012  * Enable or Disable posting of an event on ARQ when LLDP MIB
4013  * associated with the interface changes
4014  **/
4015 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4016                                 bool enable_update,
4017                                 struct i40e_asq_cmd_details *cmd_details)
4018 {
4019         struct i40e_aq_desc desc;
4020         struct i40e_aqc_lldp_update_mib *cmd =
4021                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4022         enum i40e_status_code status;
4023
4024         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4025
4026         if (!enable_update)
4027                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4028
4029         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4030
4031         return status;
4032 }
4033
4034 /**
4035  * i40e_aq_add_lldp_tlv
4036  * @hw: pointer to the hw struct
4037  * @bridge_type: type of bridge
4038  * @buff: buffer with TLV to add
4039  * @buff_size: length of the buffer
4040  * @tlv_len: length of the TLV to be added
4041  * @mib_len: length of the LLDP MIB returned in response
4042  * @cmd_details: pointer to command details structure or NULL
4043  *
4044  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4045  * it is responsibility of the caller to make sure that the TLV is not
4046  * already present in the LLDPDU.
4047  * In return firmware will write the complete LLDP MIB with the newly
4048  * added TLV in the response buffer.
4049  **/
4050 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4051                                 void *buff, u16 buff_size, u16 tlv_len,
4052                                 u16 *mib_len,
4053                                 struct i40e_asq_cmd_details *cmd_details)
4054 {
4055         struct i40e_aq_desc desc;
4056         struct i40e_aqc_lldp_add_tlv *cmd =
4057                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4058         enum i40e_status_code status;
4059
4060         if (buff_size == 0 || !buff || tlv_len == 0)
4061                 return I40E_ERR_PARAM;
4062
4063         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4064
4065         /* Indirect Command */
4066         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4067         if (buff_size > I40E_AQ_LARGE_BUF)
4068                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4069         desc.datalen = CPU_TO_LE16(buff_size);
4070
4071         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4072                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4073         cmd->len = CPU_TO_LE16(tlv_len);
4074
4075         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4076         if (!status) {
4077                 if (mib_len != NULL)
4078                         *mib_len = LE16_TO_CPU(desc.datalen);
4079         }
4080
4081         return status;
4082 }
4083
4084 /**
4085  * i40e_aq_update_lldp_tlv
4086  * @hw: pointer to the hw struct
4087  * @bridge_type: type of bridge
4088  * @buff: buffer with TLV to update
4089  * @buff_size: size of the buffer holding original and updated TLVs
4090  * @old_len: Length of the Original TLV
4091  * @new_len: Length of the Updated TLV
4092  * @offset: offset of the updated TLV in the buff
4093  * @mib_len: length of the returned LLDP MIB
4094  * @cmd_details: pointer to command details structure or NULL
4095  *
4096  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4097  * Firmware will place the complete LLDP MIB in response buffer with the
4098  * updated TLV.
4099  **/
4100 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4101                                 u8 bridge_type, void *buff, u16 buff_size,
4102                                 u16 old_len, u16 new_len, u16 offset,
4103                                 u16 *mib_len,
4104                                 struct i40e_asq_cmd_details *cmd_details)
4105 {
4106         struct i40e_aq_desc desc;
4107         struct i40e_aqc_lldp_update_tlv *cmd =
4108                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4109         enum i40e_status_code status;
4110
4111         if (buff_size == 0 || !buff || offset == 0 ||
4112             old_len == 0 || new_len == 0)
4113                 return I40E_ERR_PARAM;
4114
4115         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4116
4117         /* Indirect Command */
4118         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4119         if (buff_size > I40E_AQ_LARGE_BUF)
4120                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4121         desc.datalen = CPU_TO_LE16(buff_size);
4122
4123         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4124                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4125         cmd->old_len = CPU_TO_LE16(old_len);
4126         cmd->new_offset = CPU_TO_LE16(offset);
4127         cmd->new_len = CPU_TO_LE16(new_len);
4128
4129         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4130         if (!status) {
4131                 if (mib_len != NULL)
4132                         *mib_len = LE16_TO_CPU(desc.datalen);
4133         }
4134
4135         return status;
4136 }
4137
4138 /**
4139  * i40e_aq_delete_lldp_tlv
4140  * @hw: pointer to the hw struct
4141  * @bridge_type: type of bridge
4142  * @buff: pointer to a user supplied buffer that has the TLV
4143  * @buff_size: length of the buffer
4144  * @tlv_len: length of the TLV to be deleted
4145  * @mib_len: length of the returned LLDP MIB
4146  * @cmd_details: pointer to command details structure or NULL
4147  *
4148  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4149  * The firmware places the entire LLDP MIB in the response buffer.
4150  **/
4151 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4152                                 u8 bridge_type, void *buff, u16 buff_size,
4153                                 u16 tlv_len, u16 *mib_len,
4154                                 struct i40e_asq_cmd_details *cmd_details)
4155 {
4156         struct i40e_aq_desc desc;
4157         struct i40e_aqc_lldp_add_tlv *cmd =
4158                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4159         enum i40e_status_code status;
4160
4161         if (buff_size == 0 || !buff)
4162                 return I40E_ERR_PARAM;
4163
4164         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4165
4166         /* Indirect Command */
4167         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4168         if (buff_size > I40E_AQ_LARGE_BUF)
4169                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4170         desc.datalen = CPU_TO_LE16(buff_size);
4171         cmd->len = CPU_TO_LE16(tlv_len);
4172         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4173                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4174
4175         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4176         if (!status) {
4177                 if (mib_len != NULL)
4178                         *mib_len = LE16_TO_CPU(desc.datalen);
4179         }
4180
4181         return status;
4182 }
4183
4184 /**
4185  * i40e_aq_stop_lldp
4186  * @hw: pointer to the hw struct
4187  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4188  * @cmd_details: pointer to command details structure or NULL
4189  *
4190  * Stop or Shutdown the embedded LLDP Agent
4191  **/
4192 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4193                                 struct i40e_asq_cmd_details *cmd_details)
4194 {
4195         struct i40e_aq_desc desc;
4196         struct i40e_aqc_lldp_stop *cmd =
4197                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4198         enum i40e_status_code status;
4199
4200         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4201
4202         if (shutdown_agent)
4203                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4204
4205         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4206
4207         return status;
4208 }
4209
4210 /**
4211  * i40e_aq_start_lldp
4212  * @hw: pointer to the hw struct
4213  * @cmd_details: pointer to command details structure or NULL
4214  *
4215  * Start the embedded LLDP Agent on all ports.
4216  **/
4217 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4218                                 struct i40e_asq_cmd_details *cmd_details)
4219 {
4220         struct i40e_aq_desc desc;
4221         struct i40e_aqc_lldp_start *cmd =
4222                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4223         enum i40e_status_code status;
4224
4225         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4226
4227         cmd->command = I40E_AQ_LLDP_AGENT_START;
4228
4229         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4230
4231         return status;
4232 }
4233
4234 /**
4235  * i40e_aq_get_cee_dcb_config
4236  * @hw: pointer to the hw struct
4237  * @buff: response buffer that stores CEE operational configuration
4238  * @buff_size: size of the buffer passed
4239  * @cmd_details: pointer to command details structure or NULL
4240  *
4241  * Get CEE DCBX mode operational configuration from firmware
4242  **/
4243 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4244                                 void *buff, u16 buff_size,
4245                                 struct i40e_asq_cmd_details *cmd_details)
4246 {
4247         struct i40e_aq_desc desc;
4248         enum i40e_status_code status;
4249
4250         if (buff_size == 0 || !buff)
4251                 return I40E_ERR_PARAM;
4252
4253         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4254
4255         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4256         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4257                                        cmd_details);
4258
4259         return status;
4260 }
4261
4262 /**
4263  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4264  * @hw: pointer to the hw struct
4265  * @start_agent: True if DCBx Agent needs to be Started
4266  *                              False if DCBx Agent needs to be Stopped
4267  * @cmd_details: pointer to command details structure or NULL
4268  *
4269  * Start/Stop the embedded dcbx Agent
4270  **/
4271 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4272                                 bool start_agent,
4273                                 struct i40e_asq_cmd_details *cmd_details)
4274 {
4275         struct i40e_aq_desc desc;
4276         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4277                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4278                                 &desc.params.raw;
4279         enum i40e_status_code status;
4280
4281         i40e_fill_default_direct_cmd_desc(&desc,
4282                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4283
4284         if (start_agent)
4285                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4286
4287         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4288
4289         return status;
4290 }
4291
4292 /**
4293  * i40e_aq_add_udp_tunnel
4294  * @hw: pointer to the hw struct
4295  * @udp_port: the UDP port to add
4296  * @header_len: length of the tunneling header length in DWords
4297  * @protocol_index: protocol index type
4298  * @filter_index: pointer to filter index
4299  * @cmd_details: pointer to command details structure or NULL
4300  **/
4301 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4302                                 u16 udp_port, u8 protocol_index,
4303                                 u8 *filter_index,
4304                                 struct i40e_asq_cmd_details *cmd_details)
4305 {
4306         struct i40e_aq_desc desc;
4307         struct i40e_aqc_add_udp_tunnel *cmd =
4308                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4309         struct i40e_aqc_del_udp_tunnel_completion *resp =
4310                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4311         enum i40e_status_code status;
4312
4313         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4314
4315         cmd->udp_port = CPU_TO_LE16(udp_port);
4316         cmd->protocol_type = protocol_index;
4317
4318         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4319
4320         if (!status && filter_index)
4321                 *filter_index = resp->index;
4322
4323         return status;
4324 }
4325
4326 /**
4327  * i40e_aq_del_udp_tunnel
4328  * @hw: pointer to the hw struct
4329  * @index: filter index
4330  * @cmd_details: pointer to command details structure or NULL
4331  **/
4332 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4333                                 struct i40e_asq_cmd_details *cmd_details)
4334 {
4335         struct i40e_aq_desc desc;
4336         struct i40e_aqc_remove_udp_tunnel *cmd =
4337                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4338         enum i40e_status_code status;
4339
4340         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4341
4342         cmd->index = index;
4343
4344         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4345
4346         return status;
4347 }
4348
4349 /**
4350  * i40e_aq_get_switch_resource_alloc (0x0204)
4351  * @hw: pointer to the hw struct
4352  * @num_entries: pointer to u8 to store the number of resource entries returned
4353  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4354  *        to store the resource information for all resource types.  Each
4355  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4356  * @count: size, in bytes, of the buffer provided
4357  * @cmd_details: pointer to command details structure or NULL
4358  *
4359  * Query the resources allocated to a function.
4360  **/
4361 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4362                         u8 *num_entries,
4363                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4364                         u16 count,
4365                         struct i40e_asq_cmd_details *cmd_details)
4366 {
4367         struct i40e_aq_desc desc;
4368         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4369                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4370         enum i40e_status_code status;
4371         u16 length = count * sizeof(*buf);
4372
4373         i40e_fill_default_direct_cmd_desc(&desc,
4374                                         i40e_aqc_opc_get_switch_resource_alloc);
4375
4376         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4377         if (length > I40E_AQ_LARGE_BUF)
4378                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4379
4380         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4381
4382         if (!status && num_entries)
4383                 *num_entries = cmd_resp->num_entries;
4384
4385         return status;
4386 }
4387
4388 /**
4389  * i40e_aq_delete_element - Delete switch element
4390  * @hw: pointer to the hw struct
4391  * @seid: the SEID to delete from the switch
4392  * @cmd_details: pointer to command details structure or NULL
4393  *
4394  * This deletes a switch element from the switch.
4395  **/
4396 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4397                                 struct i40e_asq_cmd_details *cmd_details)
4398 {
4399         struct i40e_aq_desc desc;
4400         struct i40e_aqc_switch_seid *cmd =
4401                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4402         enum i40e_status_code status;
4403
4404         if (seid == 0)
4405                 return I40E_ERR_PARAM;
4406
4407         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4408
4409         cmd->seid = CPU_TO_LE16(seid);
4410
4411         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4412
4413         return status;
4414 }
4415
4416 /**
4417  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4418  * @hw: pointer to the hw struct
4419  * @flags: component flags
4420  * @mac_seid: uplink seid (MAC SEID)
4421  * @vsi_seid: connected vsi seid
4422  * @ret_seid: seid of create pv component
4423  *
4424  * This instantiates an i40e port virtualizer with specified flags.
4425  * Depending on specified flags the port virtualizer can act as a
4426  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4427  */
4428 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4429                                        u16 mac_seid, u16 vsi_seid,
4430                                        u16 *ret_seid)
4431 {
4432         struct i40e_aq_desc desc;
4433         struct i40e_aqc_add_update_pv *cmd =
4434                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4435         struct i40e_aqc_add_update_pv_completion *resp =
4436                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4437         enum i40e_status_code status;
4438
4439         if (vsi_seid == 0)
4440                 return I40E_ERR_PARAM;
4441
4442         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4443         cmd->command_flags = CPU_TO_LE16(flags);
4444         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4445         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4446
4447         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4448         if (!status && ret_seid)
4449                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4450
4451         return status;
4452 }
4453
4454 /**
4455  * i40e_aq_add_tag - Add an S/E-tag
4456  * @hw: pointer to the hw struct
4457  * @direct_to_queue: should s-tag direct flow to a specific queue
4458  * @vsi_seid: VSI SEID to use this tag
4459  * @tag: value of the tag
4460  * @queue_num: queue number, only valid is direct_to_queue is TRUE
4461  * @tags_used: return value, number of tags in use by this PF
4462  * @tags_free: return value, number of unallocated tags
4463  * @cmd_details: pointer to command details structure or NULL
4464  *
4465  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4466  * the number of tags allocated by the PF, and the number of unallocated
4467  * tags available.
4468  **/
4469 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4470                                 u16 vsi_seid, u16 tag, u16 queue_num,
4471                                 u16 *tags_used, u16 *tags_free,
4472                                 struct i40e_asq_cmd_details *cmd_details)
4473 {
4474         struct i40e_aq_desc desc;
4475         struct i40e_aqc_add_tag *cmd =
4476                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4477         struct i40e_aqc_add_remove_tag_completion *resp =
4478                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4479         enum i40e_status_code status;
4480
4481         if (vsi_seid == 0)
4482                 return I40E_ERR_PARAM;
4483
4484         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4485
4486         cmd->seid = CPU_TO_LE16(vsi_seid);
4487         cmd->tag = CPU_TO_LE16(tag);
4488         if (direct_to_queue) {
4489                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4490                 cmd->queue_number = CPU_TO_LE16(queue_num);
4491         }
4492
4493         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4494
4495         if (!status) {
4496                 if (tags_used != NULL)
4497                         *tags_used = LE16_TO_CPU(resp->tags_used);
4498                 if (tags_free != NULL)
4499                         *tags_free = LE16_TO_CPU(resp->tags_free);
4500         }
4501
4502         return status;
4503 }
4504
4505 /**
4506  * i40e_aq_remove_tag - Remove an S- or E-tag
4507  * @hw: pointer to the hw struct
4508  * @vsi_seid: VSI SEID this tag is associated with
4509  * @tag: value of the S-tag to delete
4510  * @tags_used: return value, number of tags in use by this PF
4511  * @tags_free: return value, number of unallocated tags
4512  * @cmd_details: pointer to command details structure or NULL
4513  *
4514  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4515  * the number of tags allocated by the PF, and the number of unallocated
4516  * tags available.
4517  **/
4518 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4519                                 u16 tag, u16 *tags_used, u16 *tags_free,
4520                                 struct i40e_asq_cmd_details *cmd_details)
4521 {
4522         struct i40e_aq_desc desc;
4523         struct i40e_aqc_remove_tag *cmd =
4524                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4525         struct i40e_aqc_add_remove_tag_completion *resp =
4526                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4527         enum i40e_status_code status;
4528
4529         if (vsi_seid == 0)
4530                 return I40E_ERR_PARAM;
4531
4532         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4533
4534         cmd->seid = CPU_TO_LE16(vsi_seid);
4535         cmd->tag = CPU_TO_LE16(tag);
4536
4537         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4538
4539         if (!status) {
4540                 if (tags_used != NULL)
4541                         *tags_used = LE16_TO_CPU(resp->tags_used);
4542                 if (tags_free != NULL)
4543                         *tags_free = LE16_TO_CPU(resp->tags_free);
4544         }
4545
4546         return status;
4547 }
4548
4549 /**
4550  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4551  * @hw: pointer to the hw struct
4552  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4553  * @etag: value of E-tag to add
4554  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4555  * @buf: address of indirect buffer
4556  * @tags_used: return value, number of E-tags in use by this port
4557  * @tags_free: return value, number of unallocated M-tags
4558  * @cmd_details: pointer to command details structure or NULL
4559  *
4560  * This associates a multicast E-tag to a port virtualizer.  It will return
4561  * the number of tags allocated by the PF, and the number of unallocated
4562  * tags available.
4563  *
4564  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4565  * num_tags_in_buf long.
4566  **/
4567 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4568                                 u16 etag, u8 num_tags_in_buf, void *buf,
4569                                 u16 *tags_used, u16 *tags_free,
4570                                 struct i40e_asq_cmd_details *cmd_details)
4571 {
4572         struct i40e_aq_desc desc;
4573         struct i40e_aqc_add_remove_mcast_etag *cmd =
4574                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4575         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4576            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4577         enum i40e_status_code status;
4578         u16 length = sizeof(u16) * num_tags_in_buf;
4579
4580         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4581                 return I40E_ERR_PARAM;
4582
4583         i40e_fill_default_direct_cmd_desc(&desc,
4584                                           i40e_aqc_opc_add_multicast_etag);
4585
4586         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4587         cmd->etag = CPU_TO_LE16(etag);
4588         cmd->num_unicast_etags = num_tags_in_buf;
4589
4590         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4591         if (length > I40E_AQ_LARGE_BUF)
4592                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4593
4594         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4595
4596         if (!status) {
4597                 if (tags_used != NULL)
4598                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4599                 if (tags_free != NULL)
4600                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4601         }
4602
4603         return status;
4604 }
4605
4606 /**
4607  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4608  * @hw: pointer to the hw struct
4609  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4610  * @etag: value of the E-tag to remove
4611  * @tags_used: return value, number of tags in use by this port
4612  * @tags_free: return value, number of unallocated tags
4613  * @cmd_details: pointer to command details structure or NULL
4614  *
4615  * This deletes an E-tag from the port virtualizer.  It will return
4616  * the number of tags allocated by the port, and the number of unallocated
4617  * tags available.
4618  **/
4619 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4620                                 u16 etag, u16 *tags_used, u16 *tags_free,
4621                                 struct i40e_asq_cmd_details *cmd_details)
4622 {
4623         struct i40e_aq_desc desc;
4624         struct i40e_aqc_add_remove_mcast_etag *cmd =
4625                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4626         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4627            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4628         enum i40e_status_code status;
4629
4630
4631         if (pv_seid == 0)
4632                 return I40E_ERR_PARAM;
4633
4634         i40e_fill_default_direct_cmd_desc(&desc,
4635                                           i40e_aqc_opc_remove_multicast_etag);
4636
4637         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4638         cmd->etag = CPU_TO_LE16(etag);
4639
4640         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4641
4642         if (!status) {
4643                 if (tags_used != NULL)
4644                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4645                 if (tags_free != NULL)
4646                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4647         }
4648
4649         return status;
4650 }
4651
4652 /**
4653  * i40e_aq_update_tag - Update an S/E-tag
4654  * @hw: pointer to the hw struct
4655  * @vsi_seid: VSI SEID using this S-tag
4656  * @old_tag: old tag value
4657  * @new_tag: new tag value
4658  * @tags_used: return value, number of tags in use by this PF
4659  * @tags_free: return value, number of unallocated tags
4660  * @cmd_details: pointer to command details structure or NULL
4661  *
4662  * This updates the value of the tag currently attached to this VSI
4663  * in the switch complex.  It will return the number of tags allocated
4664  * by the PF, and the number of unallocated tags available.
4665  **/
4666 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4667                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4668                                 u16 *tags_free,
4669                                 struct i40e_asq_cmd_details *cmd_details)
4670 {
4671         struct i40e_aq_desc desc;
4672         struct i40e_aqc_update_tag *cmd =
4673                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4674         struct i40e_aqc_update_tag_completion *resp =
4675                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4676         enum i40e_status_code status;
4677
4678         if (vsi_seid == 0)
4679                 return I40E_ERR_PARAM;
4680
4681         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4682
4683         cmd->seid = CPU_TO_LE16(vsi_seid);
4684         cmd->old_tag = CPU_TO_LE16(old_tag);
4685         cmd->new_tag = CPU_TO_LE16(new_tag);
4686
4687         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4688
4689         if (!status) {
4690                 if (tags_used != NULL)
4691                         *tags_used = LE16_TO_CPU(resp->tags_used);
4692                 if (tags_free != NULL)
4693                         *tags_free = LE16_TO_CPU(resp->tags_free);
4694         }
4695
4696         return status;
4697 }
4698
4699 /**
4700  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4701  * @hw: pointer to the hw struct
4702  * @tcmap: TC map for request/release any ignore PFC condition
4703  * @request: request or release ignore PFC condition
4704  * @tcmap_ret: return TCs for which PFC is currently ignored
4705  * @cmd_details: pointer to command details structure or NULL
4706  *
4707  * This sends out request/release to ignore PFC condition for a TC.
4708  * It will return the TCs for which PFC is currently ignored.
4709  **/
4710 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4711                                 bool request, u8 *tcmap_ret,
4712                                 struct i40e_asq_cmd_details *cmd_details)
4713 {
4714         struct i40e_aq_desc desc;
4715         struct i40e_aqc_pfc_ignore *cmd_resp =
4716                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4717         enum i40e_status_code status;
4718
4719         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4720
4721         if (request)
4722                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4723
4724         cmd_resp->tc_bitmap = tcmap;
4725
4726         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4727
4728         if (!status) {
4729                 if (tcmap_ret != NULL)
4730                         *tcmap_ret = cmd_resp->tc_bitmap;
4731         }
4732
4733         return status;
4734 }
4735
4736 /**
4737  * i40e_aq_dcb_updated - DCB Updated Command
4738  * @hw: pointer to the hw struct
4739  * @cmd_details: pointer to command details structure or NULL
4740  *
4741  * When LLDP is handled in PF this command is used by the PF
4742  * to notify EMP that a DCB setting is modified.
4743  * When LLDP is handled in EMP this command is used by the PF
4744  * to notify EMP whenever one of the following parameters get
4745  * modified:
4746  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4747  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4748  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4749  * EMP will return when the shared RPB settings have been
4750  * recomputed and modified. The retval field in the descriptor
4751  * will be set to 0 when RPB is modified.
4752  **/
4753 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4754                                 struct i40e_asq_cmd_details *cmd_details)
4755 {
4756         struct i40e_aq_desc desc;
4757         enum i40e_status_code status;
4758
4759         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4760
4761         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4762
4763         return status;
4764 }
4765
4766 /**
4767  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4768  * @hw: pointer to the hw struct
4769  * @seid: defines the SEID of the switch for which the stats are requested
4770  * @vlan_id: the VLAN ID for which the statistics are requested
4771  * @stat_index: index of the statistics counters block assigned to this VLAN
4772  * @cmd_details: pointer to command details structure or NULL
4773  *
4774  * XL710 supports 128 smonVlanStats counters.This command is used to
4775  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4776  * switch.
4777  **/
4778 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4779                                 u16 vlan_id, u16 *stat_index,
4780                                 struct i40e_asq_cmd_details *cmd_details)
4781 {
4782         struct i40e_aq_desc desc;
4783         struct i40e_aqc_add_remove_statistics *cmd_resp =
4784                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4785         enum i40e_status_code status;
4786
4787         if ((seid == 0) || (stat_index == NULL))
4788                 return I40E_ERR_PARAM;
4789
4790         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4791
4792         cmd_resp->seid = CPU_TO_LE16(seid);
4793         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4794
4795         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4796
4797         if (!status && stat_index)
4798                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4799
4800         return status;
4801 }
4802
4803 /**
4804  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4805  * @hw: pointer to the hw struct
4806  * @seid: defines the SEID of the switch for which the stats are requested
4807  * @vlan_id: the VLAN ID for which the statistics are requested
4808  * @stat_index: index of the statistics counters block assigned to this VLAN
4809  * @cmd_details: pointer to command details structure or NULL
4810  *
4811  * XL710 supports 128 smonVlanStats counters.This command is used to
4812  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4813  * switch.
4814  **/
4815 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4816                                 u16 vlan_id, u16 stat_index,
4817                                 struct i40e_asq_cmd_details *cmd_details)
4818 {
4819         struct i40e_aq_desc desc;
4820         struct i40e_aqc_add_remove_statistics *cmd =
4821                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4822         enum i40e_status_code status;
4823
4824         if (seid == 0)
4825                 return I40E_ERR_PARAM;
4826
4827         i40e_fill_default_direct_cmd_desc(&desc,
4828                                           i40e_aqc_opc_remove_statistics);
4829
4830         cmd->seid = CPU_TO_LE16(seid);
4831         cmd->vlan  = CPU_TO_LE16(vlan_id);
4832         cmd->stat_index = CPU_TO_LE16(stat_index);
4833
4834         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4835
4836         return status;
4837 }
4838
4839 /**
4840  * i40e_aq_set_port_parameters - set physical port parameters.
4841  * @hw: pointer to the hw struct
4842  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4843  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4844  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4845  * @double_vlan: if set double VLAN is enabled
4846  * @cmd_details: pointer to command details structure or NULL
4847  **/
4848 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4849                                 u16 bad_frame_vsi, bool save_bad_pac,
4850                                 bool pad_short_pac, bool double_vlan,
4851                                 struct i40e_asq_cmd_details *cmd_details)
4852 {
4853         struct i40e_aqc_set_port_parameters *cmd;
4854         enum i40e_status_code status;
4855         struct i40e_aq_desc desc;
4856         u16 command_flags = 0;
4857
4858         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4859
4860         i40e_fill_default_direct_cmd_desc(&desc,
4861                                           i40e_aqc_opc_set_port_parameters);
4862
4863         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4864         if (save_bad_pac)
4865                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4866         if (pad_short_pac)
4867                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4868         if (double_vlan)
4869                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4870         cmd->command_flags = CPU_TO_LE16(command_flags);
4871
4872         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4873
4874         return status;
4875 }
4876
4877 /**
4878  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4879  * @hw: pointer to the hw struct
4880  * @seid: seid for the physical port/switching component/vsi
4881  * @buff: Indirect buffer to hold data parameters and response
4882  * @buff_size: Indirect buffer size
4883  * @opcode: Tx scheduler AQ command opcode
4884  * @cmd_details: pointer to command details structure or NULL
4885  *
4886  * Generic command handler for Tx scheduler AQ commands
4887  **/
4888 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4889                                 void *buff, u16 buff_size,
4890                                  enum i40e_admin_queue_opc opcode,
4891                                 struct i40e_asq_cmd_details *cmd_details)
4892 {
4893         struct i40e_aq_desc desc;
4894         struct i40e_aqc_tx_sched_ind *cmd =
4895                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4896         enum i40e_status_code status;
4897         bool cmd_param_flag = FALSE;
4898
4899         switch (opcode) {
4900         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4901         case i40e_aqc_opc_configure_vsi_tc_bw:
4902         case i40e_aqc_opc_enable_switching_comp_ets:
4903         case i40e_aqc_opc_modify_switching_comp_ets:
4904         case i40e_aqc_opc_disable_switching_comp_ets:
4905         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4906         case i40e_aqc_opc_configure_switching_comp_bw_config:
4907                 cmd_param_flag = TRUE;
4908                 break;
4909         case i40e_aqc_opc_query_vsi_bw_config:
4910         case i40e_aqc_opc_query_vsi_ets_sla_config:
4911         case i40e_aqc_opc_query_switching_comp_ets_config:
4912         case i40e_aqc_opc_query_port_ets_config:
4913         case i40e_aqc_opc_query_switching_comp_bw_config:
4914                 cmd_param_flag = FALSE;
4915                 break;
4916         default:
4917                 return I40E_ERR_PARAM;
4918         }
4919
4920         i40e_fill_default_direct_cmd_desc(&desc, opcode);
4921
4922         /* Indirect command */
4923         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4924         if (cmd_param_flag)
4925                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4926         if (buff_size > I40E_AQ_LARGE_BUF)
4927                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4928
4929         desc.datalen = CPU_TO_LE16(buff_size);
4930
4931         cmd->vsi_seid = CPU_TO_LE16(seid);
4932
4933         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4934
4935         return status;
4936 }
4937
4938 /**
4939  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4940  * @hw: pointer to the hw struct
4941  * @seid: VSI seid
4942  * @credit: BW limit credits (0 = disabled)
4943  * @max_credit: Max BW limit credits
4944  * @cmd_details: pointer to command details structure or NULL
4945  **/
4946 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4947                                 u16 seid, u16 credit, u8 max_credit,
4948                                 struct i40e_asq_cmd_details *cmd_details)
4949 {
4950         struct i40e_aq_desc desc;
4951         struct i40e_aqc_configure_vsi_bw_limit *cmd =
4952                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4953         enum i40e_status_code status;
4954
4955         i40e_fill_default_direct_cmd_desc(&desc,
4956                                           i40e_aqc_opc_configure_vsi_bw_limit);
4957
4958         cmd->vsi_seid = CPU_TO_LE16(seid);
4959         cmd->credit = CPU_TO_LE16(credit);
4960         cmd->max_credit = max_credit;
4961
4962         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4963
4964         return status;
4965 }
4966
4967 /**
4968  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4969  * @hw: pointer to the hw struct
4970  * @seid: switching component seid
4971  * @credit: BW limit credits (0 = disabled)
4972  * @max_bw: Max BW limit credits
4973  * @cmd_details: pointer to command details structure or NULL
4974  **/
4975 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4976                                 u16 seid, u16 credit, u8 max_bw,
4977                                 struct i40e_asq_cmd_details *cmd_details)
4978 {
4979         struct i40e_aq_desc desc;
4980         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
4981           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
4982         enum i40e_status_code status;
4983
4984         i40e_fill_default_direct_cmd_desc(&desc,
4985                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
4986
4987         cmd->seid = CPU_TO_LE16(seid);
4988         cmd->credit = CPU_TO_LE16(credit);
4989         cmd->max_bw = max_bw;
4990
4991         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4992
4993         return status;
4994 }
4995
4996 /**
4997  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
4998  * @hw: pointer to the hw struct
4999  * @seid: VSI seid
5000  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5001  * @cmd_details: pointer to command details structure or NULL
5002  **/
5003 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5004                         u16 seid,
5005                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5006                         struct i40e_asq_cmd_details *cmd_details)
5007 {
5008         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5009                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5010                                     cmd_details);
5011 }
5012
5013 /**
5014  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5015  * @hw: pointer to the hw struct
5016  * @seid: VSI seid
5017  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5018  * @cmd_details: pointer to command details structure or NULL
5019  **/
5020 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5021                         u16 seid,
5022                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5023                         struct i40e_asq_cmd_details *cmd_details)
5024 {
5025         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5026                                     i40e_aqc_opc_configure_vsi_tc_bw,
5027                                     cmd_details);
5028 }
5029
5030 /**
5031  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5032  * @hw: pointer to the hw struct
5033  * @seid: seid of the switching component
5034  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5035  * @cmd_details: pointer to command details structure or NULL
5036  **/
5037 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5038         struct i40e_hw *hw, u16 seid,
5039         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5040         struct i40e_asq_cmd_details *cmd_details)
5041 {
5042         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5043                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5044                             cmd_details);
5045 }
5046
5047 /**
5048  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5049  * @hw: pointer to the hw struct
5050  * @seid: seid of the VSI
5051  * @bw_data: Buffer to hold VSI BW configuration
5052  * @cmd_details: pointer to command details structure or NULL
5053  **/
5054 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5055                         u16 seid,
5056                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5057                         struct i40e_asq_cmd_details *cmd_details)
5058 {
5059         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5060                                     i40e_aqc_opc_query_vsi_bw_config,
5061                                     cmd_details);
5062 }
5063
5064 /**
5065  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5066  * @hw: pointer to the hw struct
5067  * @seid: seid of the VSI
5068  * @bw_data: Buffer to hold VSI BW configuration per TC
5069  * @cmd_details: pointer to command details structure or NULL
5070  **/
5071 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5072                         u16 seid,
5073                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5074                         struct i40e_asq_cmd_details *cmd_details)
5075 {
5076         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5077                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5078                                     cmd_details);
5079 }
5080
5081 /**
5082  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5083  * @hw: pointer to the hw struct
5084  * @seid: seid of the switching component
5085  * @bw_data: Buffer to hold switching component's per TC BW config
5086  * @cmd_details: pointer to command details structure or NULL
5087  **/
5088 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5089                 u16 seid,
5090                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5091                 struct i40e_asq_cmd_details *cmd_details)
5092 {
5093         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5094                                    i40e_aqc_opc_query_switching_comp_ets_config,
5095                                    cmd_details);
5096 }
5097
5098 /**
5099  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5100  * @hw: pointer to the hw struct
5101  * @seid: seid of the VSI or switching component connected to Physical Port
5102  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5103  * @cmd_details: pointer to command details structure or NULL
5104  **/
5105 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5106                         u16 seid,
5107                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5108                         struct i40e_asq_cmd_details *cmd_details)
5109 {
5110         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5111                                     i40e_aqc_opc_query_port_ets_config,
5112                                     cmd_details);
5113 }
5114
5115 /**
5116  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5117  * @hw: pointer to the hw struct
5118  * @seid: seid of the switching component
5119  * @bw_data: Buffer to hold switching component's BW configuration
5120  * @cmd_details: pointer to command details structure or NULL
5121  **/
5122 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5123                 u16 seid,
5124                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5125                 struct i40e_asq_cmd_details *cmd_details)
5126 {
5127         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5128                                     i40e_aqc_opc_query_switching_comp_bw_config,
5129                                     cmd_details);
5130 }
5131
5132 /**
5133  * i40e_validate_filter_settings
5134  * @hw: pointer to the hardware structure
5135  * @settings: Filter control settings
5136  *
5137  * Check and validate the filter control settings passed.
5138  * The function checks for the valid filter/context sizes being
5139  * passed for FCoE and PE.
5140  *
5141  * Returns I40E_SUCCESS if the values passed are valid and within
5142  * range else returns an error.
5143  **/
5144 static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5145                                 struct i40e_filter_control_settings *settings)
5146 {
5147         u32 fcoe_cntx_size, fcoe_filt_size;
5148         u32 pe_cntx_size, pe_filt_size;
5149         u32 fcoe_fmax;
5150
5151         u32 val;
5152
5153         /* Validate FCoE settings passed */
5154         switch (settings->fcoe_filt_num) {
5155         case I40E_HASH_FILTER_SIZE_1K:
5156         case I40E_HASH_FILTER_SIZE_2K:
5157         case I40E_HASH_FILTER_SIZE_4K:
5158         case I40E_HASH_FILTER_SIZE_8K:
5159         case I40E_HASH_FILTER_SIZE_16K:
5160         case I40E_HASH_FILTER_SIZE_32K:
5161                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5162                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5163                 break;
5164         default:
5165                 return I40E_ERR_PARAM;
5166         }
5167
5168         switch (settings->fcoe_cntx_num) {
5169         case I40E_DMA_CNTX_SIZE_512:
5170         case I40E_DMA_CNTX_SIZE_1K:
5171         case I40E_DMA_CNTX_SIZE_2K:
5172         case I40E_DMA_CNTX_SIZE_4K:
5173                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5174                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5175                 break;
5176         default:
5177                 return I40E_ERR_PARAM;
5178         }
5179
5180         /* Validate PE settings passed */
5181         switch (settings->pe_filt_num) {
5182         case I40E_HASH_FILTER_SIZE_1K:
5183         case I40E_HASH_FILTER_SIZE_2K:
5184         case I40E_HASH_FILTER_SIZE_4K:
5185         case I40E_HASH_FILTER_SIZE_8K:
5186         case I40E_HASH_FILTER_SIZE_16K:
5187         case I40E_HASH_FILTER_SIZE_32K:
5188         case I40E_HASH_FILTER_SIZE_64K:
5189         case I40E_HASH_FILTER_SIZE_128K:
5190         case I40E_HASH_FILTER_SIZE_256K:
5191         case I40E_HASH_FILTER_SIZE_512K:
5192         case I40E_HASH_FILTER_SIZE_1M:
5193                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5194                 pe_filt_size <<= (u32)settings->pe_filt_num;
5195                 break;
5196         default:
5197                 return I40E_ERR_PARAM;
5198         }
5199
5200         switch (settings->pe_cntx_num) {
5201         case I40E_DMA_CNTX_SIZE_512:
5202         case I40E_DMA_CNTX_SIZE_1K:
5203         case I40E_DMA_CNTX_SIZE_2K:
5204         case I40E_DMA_CNTX_SIZE_4K:
5205         case I40E_DMA_CNTX_SIZE_8K:
5206         case I40E_DMA_CNTX_SIZE_16K:
5207         case I40E_DMA_CNTX_SIZE_32K:
5208         case I40E_DMA_CNTX_SIZE_64K:
5209         case I40E_DMA_CNTX_SIZE_128K:
5210         case I40E_DMA_CNTX_SIZE_256K:
5211                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5212                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5213                 break;
5214         default:
5215                 return I40E_ERR_PARAM;
5216         }
5217
5218         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5219         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5220         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5221                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5222         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5223                 return I40E_ERR_INVALID_SIZE;
5224
5225         return I40E_SUCCESS;
5226 }
5227
5228 /**
5229  * i40e_set_filter_control
5230  * @hw: pointer to the hardware structure
5231  * @settings: Filter control settings
5232  *
5233  * Set the Queue Filters for PE/FCoE and enable filters required
5234  * for a single PF. It is expected that these settings are programmed
5235  * at the driver initialization time.
5236  **/
5237 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5238                                 struct i40e_filter_control_settings *settings)
5239 {
5240         enum i40e_status_code ret = I40E_SUCCESS;
5241         u32 hash_lut_size = 0;
5242         u32 val;
5243
5244         if (!settings)
5245                 return I40E_ERR_PARAM;
5246
5247         /* Validate the input settings */
5248         ret = i40e_validate_filter_settings(hw, settings);
5249         if (ret)
5250                 return ret;
5251
5252         /* Read the PF Queue Filter control register */
5253         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5254
5255         /* Program required PE hash buckets for the PF */
5256         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5257         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5258                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5259         /* Program required PE contexts for the PF */
5260         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5261         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5262                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5263
5264         /* Program required FCoE hash buckets for the PF */
5265         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5266         val |= ((u32)settings->fcoe_filt_num <<
5267                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5268                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5269         /* Program required FCoE DDP contexts for the PF */
5270         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5271         val |= ((u32)settings->fcoe_cntx_num <<
5272                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5273                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5274
5275         /* Program Hash LUT size for the PF */
5276         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5277         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5278                 hash_lut_size = 1;
5279         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5280                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5281
5282         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5283         if (settings->enable_fdir)
5284                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5285         if (settings->enable_ethtype)
5286                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5287         if (settings->enable_macvlan)
5288                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5289
5290         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5291
5292         return I40E_SUCCESS;
5293 }
5294
5295 /**
5296  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5297  * @hw: pointer to the hw struct
5298  * @mac_addr: MAC address to use in the filter
5299  * @ethtype: Ethertype to use in the filter
5300  * @flags: Flags that needs to be applied to the filter
5301  * @vsi_seid: seid of the control VSI
5302  * @queue: VSI queue number to send the packet to
5303  * @is_add: Add control packet filter if True else remove
5304  * @stats: Structure to hold information on control filter counts
5305  * @cmd_details: pointer to command details structure or NULL
5306  *
5307  * This command will Add or Remove control packet filter for a control VSI.
5308  * In return it will update the total number of perfect filter count in
5309  * the stats member.
5310  **/
5311 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5312                                 u8 *mac_addr, u16 ethtype, u16 flags,
5313                                 u16 vsi_seid, u16 queue, bool is_add,
5314                                 struct i40e_control_filter_stats *stats,
5315                                 struct i40e_asq_cmd_details *cmd_details)
5316 {
5317         struct i40e_aq_desc desc;
5318         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5319                 (struct i40e_aqc_add_remove_control_packet_filter *)
5320                 &desc.params.raw;
5321         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5322                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5323                 &desc.params.raw;
5324         enum i40e_status_code status;
5325
5326         if (vsi_seid == 0)
5327                 return I40E_ERR_PARAM;
5328
5329         if (is_add) {
5330                 i40e_fill_default_direct_cmd_desc(&desc,
5331                                 i40e_aqc_opc_add_control_packet_filter);
5332                 cmd->queue = CPU_TO_LE16(queue);
5333         } else {
5334                 i40e_fill_default_direct_cmd_desc(&desc,
5335                                 i40e_aqc_opc_remove_control_packet_filter);
5336         }
5337
5338         if (mac_addr)
5339                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5340                             I40E_NONDMA_TO_NONDMA);
5341
5342         cmd->etype = CPU_TO_LE16(ethtype);
5343         cmd->flags = CPU_TO_LE16(flags);
5344         cmd->seid = CPU_TO_LE16(vsi_seid);
5345
5346         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5347
5348         if (!status && stats) {
5349                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5350                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5351                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5352                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5353         }
5354
5355         return status;
5356 }
5357
5358 /**
5359  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5360  * @hw: pointer to the hw struct
5361  * @seid: VSI seid to add ethertype filter from
5362  **/
5363 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5364 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5365                                                     u16 seid)
5366 {
5367         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5368                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5369                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5370         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5371         enum i40e_status_code status;
5372
5373         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5374                                                        seid, 0, TRUE, NULL,
5375                                                        NULL);
5376         if (status)
5377                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5378 }
5379
5380 /**
5381  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5382  * @filters: list of cloud filters
5383  * @filter_count: length of list
5384  *
5385  * There's an issue in the device where the Geneve VNI layout needs
5386  * to be shifted 1 byte over from the VxLAN VNI
5387  **/
5388 static void i40e_fix_up_geneve_vni(
5389         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5390         u8 filter_count)
5391 {
5392         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5393         int i;
5394
5395         for (i = 0; i < filter_count; i++) {
5396                 u16 tnl_type;
5397                 u32 ti;
5398
5399                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5400                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5401                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5402                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5403                         ti = LE32_TO_CPU(f[i].tenant_id);
5404                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5405                 }
5406         }
5407 }
5408
5409 /**
5410  * i40e_aq_add_cloud_filters
5411  * @hw: pointer to the hardware structure
5412  * @seid: VSI seid to add cloud filters from
5413  * @filters: Buffer which contains the filters to be added
5414  * @filter_count: number of filters contained in the buffer
5415  *
5416  * Set the cloud filters for a given VSI.  The contents of the
5417  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5418  * in by the caller of the function.
5419  *
5420  **/
5421 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5422         u16 seid,
5423         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5424         u8 filter_count)
5425 {
5426         struct i40e_aq_desc desc;
5427         struct i40e_aqc_add_remove_cloud_filters *cmd =
5428         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5429         enum i40e_status_code status;
5430         u16 buff_len;
5431
5432         i40e_fill_default_direct_cmd_desc(&desc,
5433                                           i40e_aqc_opc_add_cloud_filters);
5434
5435         buff_len = filter_count * sizeof(*filters);
5436         desc.datalen = CPU_TO_LE16(buff_len);
5437         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5438         cmd->num_filters = filter_count;
5439         cmd->seid = CPU_TO_LE16(seid);
5440
5441         i40e_fix_up_geneve_vni(filters, filter_count);
5442
5443         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5444
5445         return status;
5446 }
5447
5448 /**
5449  * i40e_aq_remove_cloud_filters
5450  * @hw: pointer to the hardware structure
5451  * @seid: VSI seid to remove cloud filters from
5452  * @filters: Buffer which contains the filters to be removed
5453  * @filter_count: number of filters contained in the buffer
5454  *
5455  * Remove the cloud filters for a given VSI.  The contents of the
5456  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5457  * in by the caller of the function.
5458  *
5459  **/
5460 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5461                 u16 seid,
5462                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5463                 u8 filter_count)
5464 {
5465         struct i40e_aq_desc desc;
5466         struct i40e_aqc_add_remove_cloud_filters *cmd =
5467         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5468         enum i40e_status_code status;
5469         u16 buff_len;
5470
5471         i40e_fill_default_direct_cmd_desc(&desc,
5472                                           i40e_aqc_opc_remove_cloud_filters);
5473
5474         buff_len = filter_count * sizeof(*filters);
5475         desc.datalen = CPU_TO_LE16(buff_len);
5476         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5477         cmd->num_filters = filter_count;
5478         cmd->seid = CPU_TO_LE16(seid);
5479
5480         i40e_fix_up_geneve_vni(filters, filter_count);
5481
5482         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5483
5484         return status;
5485 }
5486
5487 /**
5488  * i40e_aq_alternate_write
5489  * @hw: pointer to the hardware structure
5490  * @reg_addr0: address of first dword to be read
5491  * @reg_val0: value to be written under 'reg_addr0'
5492  * @reg_addr1: address of second dword to be read
5493  * @reg_val1: value to be written under 'reg_addr1'
5494  *
5495  * Write one or two dwords to alternate structure. Fields are indicated
5496  * by 'reg_addr0' and 'reg_addr1' register numbers.
5497  *
5498  **/
5499 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5500                                 u32 reg_addr0, u32 reg_val0,
5501                                 u32 reg_addr1, u32 reg_val1)
5502 {
5503         struct i40e_aq_desc desc;
5504         struct i40e_aqc_alternate_write *cmd_resp =
5505                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5506         enum i40e_status_code status;
5507
5508         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5509         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5510         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5511         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5512         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5513
5514         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5515
5516         return status;
5517 }
5518
5519 /**
5520  * i40e_aq_alternate_write_indirect
5521  * @hw: pointer to the hardware structure
5522  * @addr: address of a first register to be modified
5523  * @dw_count: number of alternate structure fields to write
5524  * @buffer: pointer to the command buffer
5525  *
5526  * Write 'dw_count' dwords from 'buffer' to alternate structure
5527  * starting at 'addr'.
5528  *
5529  **/
5530 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5531                                 u32 addr, u32 dw_count, void *buffer)
5532 {
5533         struct i40e_aq_desc desc;
5534         struct i40e_aqc_alternate_ind_write *cmd_resp =
5535                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5536         enum i40e_status_code status;
5537
5538         if (buffer == NULL)
5539                 return I40E_ERR_PARAM;
5540
5541         /* Indirect command */
5542         i40e_fill_default_direct_cmd_desc(&desc,
5543                                          i40e_aqc_opc_alternate_write_indirect);
5544
5545         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5546         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5547         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5548                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5549
5550         cmd_resp->address = CPU_TO_LE32(addr);
5551         cmd_resp->length = CPU_TO_LE32(dw_count);
5552
5553         status = i40e_asq_send_command(hw, &desc, buffer,
5554                                        I40E_LO_DWORD(4*dw_count), NULL);
5555
5556         return status;
5557 }
5558
5559 /**
5560  * i40e_aq_alternate_read
5561  * @hw: pointer to the hardware structure
5562  * @reg_addr0: address of first dword to be read
5563  * @reg_val0: pointer for data read from 'reg_addr0'
5564  * @reg_addr1: address of second dword to be read
5565  * @reg_val1: pointer for data read from 'reg_addr1'
5566  *
5567  * Read one or two dwords from alternate structure. Fields are indicated
5568  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5569  * is not passed then only register at 'reg_addr0' is read.
5570  *
5571  **/
5572 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5573                                 u32 reg_addr0, u32 *reg_val0,
5574                                 u32 reg_addr1, u32 *reg_val1)
5575 {
5576         struct i40e_aq_desc desc;
5577         struct i40e_aqc_alternate_write *cmd_resp =
5578                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5579         enum i40e_status_code status;
5580
5581         if (reg_val0 == NULL)
5582                 return I40E_ERR_PARAM;
5583
5584         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5585         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5586         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5587
5588         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5589
5590         if (status == I40E_SUCCESS) {
5591                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5592
5593                 if (reg_val1 != NULL)
5594                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5595         }
5596
5597         return status;
5598 }
5599
5600 /**
5601  * i40e_aq_alternate_read_indirect
5602  * @hw: pointer to the hardware structure
5603  * @addr: address of the alternate structure field
5604  * @dw_count: number of alternate structure fields to read
5605  * @buffer: pointer to the command buffer
5606  *
5607  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5608  * place them in 'buffer'. The buffer should be allocated by caller.
5609  *
5610  **/
5611 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5612                                 u32 addr, u32 dw_count, void *buffer)
5613 {
5614         struct i40e_aq_desc desc;
5615         struct i40e_aqc_alternate_ind_write *cmd_resp =
5616                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5617         enum i40e_status_code status;
5618
5619         if (buffer == NULL)
5620                 return I40E_ERR_PARAM;
5621
5622         /* Indirect command */
5623         i40e_fill_default_direct_cmd_desc(&desc,
5624                 i40e_aqc_opc_alternate_read_indirect);
5625
5626         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5627         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5628         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5629                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5630
5631         cmd_resp->address = CPU_TO_LE32(addr);
5632         cmd_resp->length = CPU_TO_LE32(dw_count);
5633
5634         status = i40e_asq_send_command(hw, &desc, buffer,
5635                                        I40E_LO_DWORD(4*dw_count), NULL);
5636
5637         return status;
5638 }
5639
5640 /**
5641  *  i40e_aq_alternate_clear
5642  *  @hw: pointer to the HW structure.
5643  *
5644  *  Clear the alternate structures of the port from which the function
5645  *  is called.
5646  *
5647  **/
5648 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5649 {
5650         struct i40e_aq_desc desc;
5651         enum i40e_status_code status;
5652
5653         i40e_fill_default_direct_cmd_desc(&desc,
5654                                           i40e_aqc_opc_alternate_clear_port);
5655
5656         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5657
5658         return status;
5659 }
5660
5661 /**
5662  *  i40e_aq_alternate_write_done
5663  *  @hw: pointer to the HW structure.
5664  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5665  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5666  *
5667  *  Indicates to the FW that alternate structures have been changed.
5668  *
5669  **/
5670 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5671                 u8 bios_mode, bool *reset_needed)
5672 {
5673         struct i40e_aq_desc desc;
5674         struct i40e_aqc_alternate_write_done *cmd =
5675                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5676         enum i40e_status_code status;
5677
5678         if (reset_needed == NULL)
5679                 return I40E_ERR_PARAM;
5680
5681         i40e_fill_default_direct_cmd_desc(&desc,
5682                                           i40e_aqc_opc_alternate_write_done);
5683
5684         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5685
5686         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5687         if (!status && reset_needed)
5688                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5689                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5690
5691         return status;
5692 }
5693
5694 /**
5695  *  i40e_aq_set_oem_mode
5696  *  @hw: pointer to the HW structure.
5697  *  @oem_mode: the OEM mode to be used
5698  *
5699  *  Sets the device to a specific operating mode. Currently the only supported
5700  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5701  *
5702  **/
5703 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5704                 u8 oem_mode)
5705 {
5706         struct i40e_aq_desc desc;
5707         struct i40e_aqc_alternate_write_done *cmd =
5708                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5709         enum i40e_status_code status;
5710
5711         i40e_fill_default_direct_cmd_desc(&desc,
5712                                           i40e_aqc_opc_alternate_set_mode);
5713
5714         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5715
5716         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5717
5718         return status;
5719 }
5720
5721 /**
5722  * i40e_aq_resume_port_tx
5723  * @hw: pointer to the hardware structure
5724  * @cmd_details: pointer to command details structure or NULL
5725  *
5726  * Resume port's Tx traffic
5727  **/
5728 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5729                                 struct i40e_asq_cmd_details *cmd_details)
5730 {
5731         struct i40e_aq_desc desc;
5732         enum i40e_status_code status;
5733
5734         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5735
5736         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5737
5738         return status;
5739 }
5740
5741 /**
5742  * i40e_set_pci_config_data - store PCI bus info
5743  * @hw: pointer to hardware structure
5744  * @link_status: the link status word from PCI config space
5745  *
5746  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5747  **/
5748 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5749 {
5750         hw->bus.type = i40e_bus_type_pci_express;
5751
5752         switch (link_status & I40E_PCI_LINK_WIDTH) {
5753         case I40E_PCI_LINK_WIDTH_1:
5754                 hw->bus.width = i40e_bus_width_pcie_x1;
5755                 break;
5756         case I40E_PCI_LINK_WIDTH_2:
5757                 hw->bus.width = i40e_bus_width_pcie_x2;
5758                 break;
5759         case I40E_PCI_LINK_WIDTH_4:
5760                 hw->bus.width = i40e_bus_width_pcie_x4;
5761                 break;
5762         case I40E_PCI_LINK_WIDTH_8:
5763                 hw->bus.width = i40e_bus_width_pcie_x8;
5764                 break;
5765         default:
5766                 hw->bus.width = i40e_bus_width_unknown;
5767                 break;
5768         }
5769
5770         switch (link_status & I40E_PCI_LINK_SPEED) {
5771         case I40E_PCI_LINK_SPEED_2500:
5772                 hw->bus.speed = i40e_bus_speed_2500;
5773                 break;
5774         case I40E_PCI_LINK_SPEED_5000:
5775                 hw->bus.speed = i40e_bus_speed_5000;
5776                 break;
5777         case I40E_PCI_LINK_SPEED_8000:
5778                 hw->bus.speed = i40e_bus_speed_8000;
5779                 break;
5780         default:
5781                 hw->bus.speed = i40e_bus_speed_unknown;
5782                 break;
5783         }
5784 }
5785
5786 /**
5787  * i40e_aq_debug_dump
5788  * @hw: pointer to the hardware structure
5789  * @cluster_id: specific cluster to dump
5790  * @table_id: table id within cluster
5791  * @start_index: index of line in the block to read
5792  * @buff_size: dump buffer size
5793  * @buff: dump buffer
5794  * @ret_buff_size: actual buffer size returned
5795  * @ret_next_table: next block to read
5796  * @ret_next_index: next index to read
5797  *
5798  * Dump internal FW/HW data for debug purposes.
5799  *
5800  **/
5801 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5802                                 u8 table_id, u32 start_index, u16 buff_size,
5803                                 void *buff, u16 *ret_buff_size,
5804                                 u8 *ret_next_table, u32 *ret_next_index,
5805                                 struct i40e_asq_cmd_details *cmd_details)
5806 {
5807         struct i40e_aq_desc desc;
5808         struct i40e_aqc_debug_dump_internals *cmd =
5809                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5810         struct i40e_aqc_debug_dump_internals *resp =
5811                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5812         enum i40e_status_code status;
5813
5814         if (buff_size == 0 || !buff)
5815                 return I40E_ERR_PARAM;
5816
5817         i40e_fill_default_direct_cmd_desc(&desc,
5818                                           i40e_aqc_opc_debug_dump_internals);
5819         /* Indirect Command */
5820         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5821         if (buff_size > I40E_AQ_LARGE_BUF)
5822                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5823
5824         cmd->cluster_id = cluster_id;
5825         cmd->table_id = table_id;
5826         cmd->idx = CPU_TO_LE32(start_index);
5827
5828         desc.datalen = CPU_TO_LE16(buff_size);
5829
5830         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5831         if (!status) {
5832                 if (ret_buff_size != NULL)
5833                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5834                 if (ret_next_table != NULL)
5835                         *ret_next_table = resp->table_id;
5836                 if (ret_next_index != NULL)
5837                         *ret_next_index = LE32_TO_CPU(resp->idx);
5838         }
5839
5840         return status;
5841 }
5842
5843 /**
5844  * i40e_read_bw_from_alt_ram
5845  * @hw: pointer to the hardware structure
5846  * @max_bw: pointer for max_bw read
5847  * @min_bw: pointer for min_bw read
5848  * @min_valid: pointer for bool that is TRUE if min_bw is a valid value
5849  * @max_valid: pointer for bool that is TRUE if max_bw is a valid value
5850  *
5851  * Read bw from the alternate ram for the given pf
5852  **/
5853 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5854                                         u32 *max_bw, u32 *min_bw,
5855                                         bool *min_valid, bool *max_valid)
5856 {
5857         enum i40e_status_code status;
5858         u32 max_bw_addr, min_bw_addr;
5859
5860         /* Calculate the address of the min/max bw registers */
5861         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5862                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
5863                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5864         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5865                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
5866                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5867
5868         /* Read the bandwidths from alt ram */
5869         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5870                                         min_bw_addr, min_bw);
5871
5872         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5873                 *min_valid = TRUE;
5874         else
5875                 *min_valid = FALSE;
5876
5877         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5878                 *max_valid = TRUE;
5879         else
5880                 *max_valid = FALSE;
5881
5882         return status;
5883 }
5884
5885 /**
5886  * i40e_aq_configure_partition_bw
5887  * @hw: pointer to the hardware structure
5888  * @bw_data: Buffer holding valid pfs and bw limits
5889  * @cmd_details: pointer to command details
5890  *
5891  * Configure partitions guaranteed/max bw
5892  **/
5893 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5894                         struct i40e_aqc_configure_partition_bw_data *bw_data,
5895                         struct i40e_asq_cmd_details *cmd_details)
5896 {
5897         enum i40e_status_code status;
5898         struct i40e_aq_desc desc;
5899         u16 bwd_size = sizeof(*bw_data);
5900
5901         i40e_fill_default_direct_cmd_desc(&desc,
5902                                 i40e_aqc_opc_configure_partition_bw);
5903
5904         /* Indirect command */
5905         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5906         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5907
5908         if (bwd_size > I40E_AQ_LARGE_BUF)
5909                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5910
5911         desc.datalen = CPU_TO_LE16(bwd_size);
5912
5913         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5914
5915         return status;
5916 }
5917
5918 /**
5919  * i40e_read_phy_register
5920  * @hw: pointer to the HW structure
5921  * @page: registers page number
5922  * @reg: register address in the page
5923  * @phy_adr: PHY address on MDIO interface
5924  * @value: PHY register value
5925  *
5926  * Reads specified PHY register value
5927  **/
5928 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
5929                                              u8 page, u16 reg, u8 phy_addr,
5930                                              u16 *value)
5931 {
5932         enum i40e_status_code status = I40E_ERR_TIMEOUT;
5933         u32 command  = 0;
5934         u16 retry = 1000;
5935         u8 port_num = (u8)hw->func_caps.mdio_port_num;
5936
5937         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
5938                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
5939                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
5940                   (I40E_MDIO_OPCODE_ADDRESS) |
5941                   (I40E_MDIO_STCODE) |
5942                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
5943                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
5944         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
5945         do {
5946                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
5947                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
5948                         status = I40E_SUCCESS;
5949                         break;
5950                 }
5951                 i40e_usec_delay(10);
5952                 retry--;
5953         } while (retry);
5954
5955         if (status) {
5956                 i40e_debug(hw, I40E_DEBUG_PHY,
5957                            "PHY: Can't write command to external PHY.\n");
5958                 goto phy_read_end;
5959         }
5960
5961         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
5962                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
5963                   (I40E_MDIO_OPCODE_READ) |
5964                   (I40E_MDIO_STCODE) |
5965                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
5966                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
5967         status = I40E_ERR_TIMEOUT;
5968         retry = 1000;
5969         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
5970         do {
5971                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
5972                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
5973                         status = I40E_SUCCESS;
5974                         break;
5975                 }
5976                 i40e_usec_delay(10);
5977                 retry--;
5978         } while (retry);
5979
5980         if (!status) {
5981                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
5982                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
5983                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
5984         } else {
5985                 i40e_debug(hw, I40E_DEBUG_PHY,
5986                            "PHY: Can't read register value from external PHY.\n");
5987         }
5988
5989 phy_read_end:
5990         return status;
5991 }
5992
5993 /**
5994  * i40e_write_phy_register
5995  * @hw: pointer to the HW structure
5996  * @page: registers page number
5997  * @reg: register address in the page
5998  * @phy_adr: PHY address on MDIO interface
5999  * @value: PHY register value
6000  *
6001  * Writes value to specified PHY register
6002  **/
6003 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6004                                               u8 page, u16 reg, u8 phy_addr,
6005                                               u16 value)
6006 {
6007         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6008         u32 command  = 0;
6009         u16 retry = 1000;
6010         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6011
6012         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6013                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6014                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6015                   (I40E_MDIO_OPCODE_ADDRESS) |
6016                   (I40E_MDIO_STCODE) |
6017                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6018                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6019         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6020         do {
6021                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6022                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6023                         status = I40E_SUCCESS;
6024                         break;
6025                 }
6026                 i40e_usec_delay(10);
6027                 retry--;
6028         } while (retry);
6029         if (status) {
6030                 i40e_debug(hw, I40E_DEBUG_PHY,
6031                            "PHY: Can't write command to external PHY.\n");
6032                 goto phy_write_end;
6033         }
6034
6035         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6036         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6037
6038         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6039                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6040                   (I40E_MDIO_OPCODE_WRITE) |
6041                   (I40E_MDIO_STCODE) |
6042                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6043                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6044         status = I40E_ERR_TIMEOUT;
6045         retry = 1000;
6046         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6047         do {
6048                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6049                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6050                         status = I40E_SUCCESS;
6051                         break;
6052                 }
6053                 i40e_usec_delay(10);
6054                 retry--;
6055         } while (retry);
6056
6057 phy_write_end:
6058         return status;
6059 }
6060
6061 /**
6062  * i40e_get_phy_address
6063  * @hw: pointer to the HW structure
6064  * @dev_num: PHY port num that address we want
6065  * @phy_addr: Returned PHY address
6066  *
6067  * Gets PHY address for current port
6068  **/
6069 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6070 {
6071         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6072         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6073
6074         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6075 }
6076
6077 /**
6078  * i40e_blink_phy_led
6079  * @hw: pointer to the HW structure
6080  * @time: time how long led will blinks in secs
6081  * @interval: gap between LED on and off in msecs
6082  *
6083  * Blinks PHY link LED
6084  **/
6085 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6086                                               u32 time, u32 interval)
6087 {
6088         enum i40e_status_code status = I40E_SUCCESS;
6089         u32 i;
6090         u16 led_ctl = 0;
6091         u16 gpio_led_port;
6092         u16 led_reg;
6093         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6094         u8 phy_addr = 0;
6095         u8 port_num;
6096
6097         i = rd32(hw, I40E_PFGEN_PORTNUM);
6098         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6099         phy_addr = i40e_get_phy_address(hw, port_num);
6100
6101         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6102              led_addr++) {
6103                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6104                                                 led_addr, phy_addr, &led_reg);
6105                 if (status)
6106                         goto phy_blinking_end;
6107                 led_ctl = led_reg;
6108                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6109                         led_reg = 0;
6110                         status = i40e_write_phy_register(hw,
6111                                                          I40E_PHY_COM_REG_PAGE,
6112                                                          led_addr, phy_addr,
6113                                                          led_reg);
6114                         if (status)
6115                                 goto phy_blinking_end;
6116                         break;
6117                 }
6118         }
6119
6120         if (time > 0 && interval > 0) {
6121                 for (i = 0; i < time * 1000; i += interval) {
6122                         status = i40e_read_phy_register(hw,
6123                                                         I40E_PHY_COM_REG_PAGE,
6124                                                         led_addr, phy_addr,
6125                                                         &led_reg);
6126                         if (status)
6127                                 goto restore_config;
6128                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6129                                 led_reg = 0;
6130                         else
6131                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6132                         status = i40e_write_phy_register(hw,
6133                                                          I40E_PHY_COM_REG_PAGE,
6134                                                          led_addr, phy_addr,
6135                                                          led_reg);
6136                         if (status)
6137                                 goto restore_config;
6138                         i40e_msec_delay(interval);
6139                 }
6140         }
6141
6142 restore_config:
6143         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6144                                          phy_addr, led_ctl);
6145
6146 phy_blinking_end:
6147         return status;
6148 }
6149
6150 /**
6151  * i40e_led_get_phy - return current on/off mode
6152  * @hw: pointer to the hw struct
6153  * @led_addr: address of led register to use
6154  * @val: original value of register to use
6155  *
6156  **/
6157 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6158                                        u16 *val)
6159 {
6160         enum i40e_status_code status = I40E_SUCCESS;
6161         u16 gpio_led_port;
6162         u8 phy_addr = 0;
6163         u16 reg_val;
6164         u16 temp_addr;
6165         u8 port_num;
6166         u32 i;
6167
6168         temp_addr = I40E_PHY_LED_PROV_REG_1;
6169         i = rd32(hw, I40E_PFGEN_PORTNUM);
6170         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6171         phy_addr = i40e_get_phy_address(hw, port_num);
6172
6173         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6174              temp_addr++) {
6175                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6176                                                 temp_addr, phy_addr, &reg_val);
6177                 if (status)
6178                         return status;
6179                 *val = reg_val;
6180                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6181                         *led_addr = temp_addr;
6182                         break;
6183                 }
6184         }
6185         return status;
6186 }
6187
6188 /**
6189  * i40e_led_set_phy
6190  * @hw: pointer to the HW structure
6191  * @on: TRUE or FALSE
6192  * @mode: original val plus bit for set or ignore
6193  * Set led's on or off when controlled by the PHY
6194  *
6195  **/
6196 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6197                                        u16 led_addr, u32 mode)
6198 {
6199         enum i40e_status_code status = I40E_SUCCESS;
6200         u16 led_ctl = 0;
6201         u16 led_reg = 0;
6202         u8 phy_addr = 0;
6203         u8 port_num;
6204         u32 i;
6205
6206         i = rd32(hw, I40E_PFGEN_PORTNUM);
6207         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6208         phy_addr = i40e_get_phy_address(hw, port_num);
6209
6210         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6211                                         phy_addr, &led_reg);
6212         if (status)
6213                 return status;
6214         led_ctl = led_reg;
6215         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6216                 led_reg = 0;
6217                 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6218                                                  led_addr, phy_addr, led_reg);
6219                 if (status)
6220                         return status;
6221         }
6222         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6223                                         led_addr, phy_addr, &led_reg);
6224         if (status)
6225                 goto restore_config;
6226         if (on)
6227                 led_reg = I40E_PHY_LED_MANUAL_ON;
6228         else
6229                 led_reg = 0;
6230         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6231                                          led_addr, phy_addr, led_reg);
6232         if (status)
6233                 goto restore_config;
6234         if (mode & I40E_PHY_LED_MODE_ORIG) {
6235                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6236                 status = i40e_write_phy_register(hw,
6237                                                  I40E_PHY_COM_REG_PAGE,
6238                                                  led_addr, phy_addr, led_ctl);
6239         }
6240         return status;
6241 restore_config:
6242         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6243                                          phy_addr, led_ctl);
6244         return status;
6245 }
6246
6247 /**
6248  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6249  * @hw: pointer to the hw struct
6250  * @reg_addr: register address
6251  * @reg_val: ptr to register value
6252  * @cmd_details: pointer to command details structure or NULL
6253  *
6254  * Use the firmware to read the Rx control register,
6255  * especially useful if the Rx unit is under heavy pressure
6256  **/
6257 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6258                                 u32 reg_addr, u32 *reg_val,
6259                                 struct i40e_asq_cmd_details *cmd_details)
6260 {
6261         struct i40e_aq_desc desc;
6262         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6263                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6264         enum i40e_status_code status;
6265
6266         if (reg_val == NULL)
6267                 return I40E_ERR_PARAM;
6268
6269         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6270
6271         cmd_resp->address = CPU_TO_LE32(reg_addr);
6272
6273         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6274
6275         if (status == I40E_SUCCESS)
6276                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6277
6278         return status;
6279 }
6280
6281 /**
6282  * i40e_read_rx_ctl - read from an Rx control register
6283  * @hw: pointer to the hw struct
6284  * @reg_addr: register address
6285  **/
6286 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6287 {
6288         enum i40e_status_code status = I40E_SUCCESS;
6289         bool use_register;
6290         int retry = 5;
6291         u32 val = 0;
6292
6293         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6294         if (!use_register) {
6295 do_retry:
6296                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6297                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6298                         i40e_msec_delay(1);
6299                         retry--;
6300                         goto do_retry;
6301                 }
6302         }
6303
6304         /* if the AQ access failed, try the old-fashioned way */
6305         if (status || use_register)
6306                 val = rd32(hw, reg_addr);
6307
6308         return val;
6309 }
6310
6311 /**
6312  * i40e_aq_rx_ctl_write_register
6313  * @hw: pointer to the hw struct
6314  * @reg_addr: register address
6315  * @reg_val: register value
6316  * @cmd_details: pointer to command details structure or NULL
6317  *
6318  * Use the firmware to write to an Rx control register,
6319  * especially useful if the Rx unit is under heavy pressure
6320  **/
6321 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6322                                 u32 reg_addr, u32 reg_val,
6323                                 struct i40e_asq_cmd_details *cmd_details)
6324 {
6325         struct i40e_aq_desc desc;
6326         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6327                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6328         enum i40e_status_code status;
6329
6330         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6331
6332         cmd->address = CPU_TO_LE32(reg_addr);
6333         cmd->value = CPU_TO_LE32(reg_val);
6334
6335         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6336
6337         return status;
6338 }
6339
6340 /**
6341  * i40e_write_rx_ctl - write to an Rx control register
6342  * @hw: pointer to the hw struct
6343  * @reg_addr: register address
6344  * @reg_val: register value
6345  **/
6346 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6347 {
6348         enum i40e_status_code status = I40E_SUCCESS;
6349         bool use_register;
6350         int retry = 5;
6351
6352         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6353         if (!use_register) {
6354 do_retry:
6355                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6356                                                        reg_val, NULL);
6357                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6358                         i40e_msec_delay(1);
6359                         retry--;
6360                         goto do_retry;
6361                 }
6362         }
6363
6364         /* if the AQ access failed, try the old-fashioned way */
6365         if (status || use_register)
6366                 wr32(hw, reg_addr, reg_val);
6367 }
6368
6369 /**
6370  * i40e_aq_send_msg_to_pf
6371  * @hw: pointer to the hardware structure
6372  * @v_opcode: opcodes for VF-PF communication
6373  * @v_retval: return error code
6374  * @msg: pointer to the msg buffer
6375  * @msglen: msg length
6376  * @cmd_details: pointer to command details
6377  *
6378  * Send message to PF driver using admin queue. By default, this message
6379  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6380  * completion before returning.
6381  **/
6382 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6383                                 enum i40e_virtchnl_ops v_opcode,
6384                                 enum i40e_status_code v_retval,
6385                                 u8 *msg, u16 msglen,
6386                                 struct i40e_asq_cmd_details *cmd_details)
6387 {
6388         struct i40e_aq_desc desc;
6389         struct i40e_asq_cmd_details details;
6390         enum i40e_status_code status;
6391
6392         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6393         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6394         desc.cookie_high = CPU_TO_LE32(v_opcode);
6395         desc.cookie_low = CPU_TO_LE32(v_retval);
6396         if (msglen) {
6397                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6398                                                 | I40E_AQ_FLAG_RD));
6399                 if (msglen > I40E_AQ_LARGE_BUF)
6400                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6401                 desc.datalen = CPU_TO_LE16(msglen);
6402         }
6403         if (!cmd_details) {
6404                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6405                 details.async = TRUE;
6406                 cmd_details = &details;
6407         }
6408         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6409                                        msglen, cmd_details);
6410         return status;
6411 }
6412
6413 /**
6414  * i40e_vf_parse_hw_config
6415  * @hw: pointer to the hardware structure
6416  * @msg: pointer to the virtual channel VF resource structure
6417  *
6418  * Given a VF resource message from the PF, populate the hw struct
6419  * with appropriate information.
6420  **/
6421 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6422                              struct i40e_virtchnl_vf_resource *msg)
6423 {
6424         struct i40e_virtchnl_vsi_resource *vsi_res;
6425         int i;
6426
6427         vsi_res = &msg->vsi_res[0];
6428
6429         hw->dev_caps.num_vsis = msg->num_vsis;
6430         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6431         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6432         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6433         hw->dev_caps.dcb = msg->vf_offload_flags &
6434                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6435         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6436                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6437         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6438                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6439         for (i = 0; i < msg->num_vsis; i++) {
6440                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6441                         i40e_memcpy(hw->mac.perm_addr,
6442                                     vsi_res->default_mac_addr,
6443                                     I40E_ETH_LENGTH_OF_ADDRESS,
6444                                     I40E_NONDMA_TO_NONDMA);
6445                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6446                                     I40E_ETH_LENGTH_OF_ADDRESS,
6447                                     I40E_NONDMA_TO_NONDMA);
6448                 }
6449                 vsi_res++;
6450         }
6451 }
6452
6453 /**
6454  * i40e_vf_reset
6455  * @hw: pointer to the hardware structure
6456  *
6457  * Send a VF_RESET message to the PF. Does not wait for response from PF
6458  * as none will be forthcoming. Immediately after calling this function,
6459  * the admin queue should be shut down and (optionally) reinitialized.
6460  **/
6461 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6462 {
6463         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6464                                       I40E_SUCCESS, NULL, 0, NULL);
6465 }
6466
6467 /**
6468  * i40e_aq_set_arp_proxy_config
6469  * @hw: pointer to the HW structure
6470  * @proxy_config - pointer to proxy config command table struct
6471  * @cmd_details: pointer to command details
6472  *
6473  * Set ARP offload parameters from pre-populated
6474  * i40e_aqc_arp_proxy_data struct
6475  **/
6476 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6477                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6478                                 struct i40e_asq_cmd_details *cmd_details)
6479 {
6480         struct i40e_aq_desc desc;
6481         enum i40e_status_code status;
6482
6483         if (!proxy_config)
6484                 return I40E_ERR_PARAM;
6485
6486         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6487
6488         desc.params.external.addr_high =
6489                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6490         desc.params.external.addr_low =
6491                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6492
6493         status = i40e_asq_send_command(hw, &desc, proxy_config,
6494                                        sizeof(struct i40e_aqc_arp_proxy_data),
6495                                        cmd_details);
6496
6497         return status;
6498 }
6499
6500 /**
6501  * i40e_aq_opc_set_ns_proxy_table_entry
6502  * @hw: pointer to the HW structure
6503  * @ns_proxy_table_entry: pointer to NS table entry command struct
6504  * @cmd_details: pointer to command details
6505  *
6506  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6507  * from pre-populated i40e_aqc_ns_proxy_data struct
6508  **/
6509 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6510                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6511                         struct i40e_asq_cmd_details *cmd_details)
6512 {
6513         struct i40e_aq_desc desc;
6514         enum i40e_status_code status;
6515
6516         if (!ns_proxy_table_entry)
6517                 return I40E_ERR_PARAM;
6518
6519         i40e_fill_default_direct_cmd_desc(&desc,
6520                                 i40e_aqc_opc_set_ns_proxy_table_entry);
6521
6522         desc.params.external.addr_high =
6523                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6524         desc.params.external.addr_low =
6525                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6526
6527         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6528                                        sizeof(struct i40e_aqc_ns_proxy_data),
6529                                        cmd_details);
6530
6531         return status;
6532 }
6533
6534 /**
6535  * i40e_aq_set_clear_wol_filter
6536  * @hw: pointer to the hw struct
6537  * @filter_index: index of filter to modify (0-7)
6538  * @filter: buffer containing filter to be set
6539  * @set_filter: TRUE to set filter, FALSE to clear filter
6540  * @no_wol_tco: if TRUE, pass through packets cannot cause wake-up
6541  *              if FALSE, pass through packets may cause wake-up
6542  * @filter_valid: TRUE if filter action is valid
6543  * @no_wol_tco_valid: TRUE if no WoL in TCO traffic action valid
6544  * @cmd_details: pointer to command details structure or NULL
6545  *
6546  * Set or clear WoL filter for port attached to the PF
6547  **/
6548 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6549                                 u8 filter_index,
6550                                 struct i40e_aqc_set_wol_filter_data *filter,
6551                                 bool set_filter, bool no_wol_tco,
6552                                 bool filter_valid, bool no_wol_tco_valid,
6553                                 struct i40e_asq_cmd_details *cmd_details)
6554 {
6555         struct i40e_aq_desc desc;
6556         struct i40e_aqc_set_wol_filter *cmd =
6557                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6558         enum i40e_status_code status;
6559         u16 cmd_flags = 0;
6560         u16 valid_flags = 0;
6561         u16 buff_len = 0;
6562
6563         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6564
6565         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6566                 return  I40E_ERR_PARAM;
6567         cmd->filter_index = CPU_TO_LE16(filter_index);
6568
6569         if (set_filter) {
6570                 if (!filter)
6571                         return  I40E_ERR_PARAM;
6572                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6573                 buff_len = sizeof(*filter);
6574         }
6575         if (no_wol_tco)
6576                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6577         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6578
6579         if (filter_valid)
6580                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6581         if (no_wol_tco_valid)
6582                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6583         cmd->valid_flags = CPU_TO_LE16(valid_flags);
6584
6585         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6586         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6587
6588         status = i40e_asq_send_command(hw, &desc, filter,
6589                                        buff_len, cmd_details);
6590
6591         return status;
6592 }
6593
6594 /**
6595  * i40e_aq_get_wake_event_reason
6596  * @hw: pointer to the hw struct
6597  * @wake_reason: return value, index of matching filter
6598  * @cmd_details: pointer to command details structure or NULL
6599  *
6600  * Get information for the reason of a Wake Up event
6601  **/
6602 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6603                                 u16 *wake_reason,
6604                                 struct i40e_asq_cmd_details *cmd_details)
6605 {
6606         struct i40e_aq_desc desc;
6607         struct i40e_aqc_get_wake_reason_completion *resp =
6608                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6609         enum i40e_status_code status;
6610
6611         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6612
6613         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6614
6615         if (status == I40E_SUCCESS)
6616                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6617
6618         return status;
6619 }
6620