1 /******************************************************************************
3 Copyright (c) 2013-2018, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "i40e_osdep.h"
36 #include "i40e_register.h"
37 #include "i40e_type.h"
39 #include "i40e_lan_hmc.h"
40 #include "i40e_prototype.h"
42 /* lan specific interface functions */
45 * i40e_align_l2obj_base - aligns base object pointer to 512 bytes
46 * @offset: base address offset needing alignment
48 * Aligns the layer 2 function private memory so it's 512-byte aligned.
50 static u64 i40e_align_l2obj_base(u64 offset)
52 u64 aligned_offset = offset;
54 if ((offset % I40E_HMC_L2OBJ_BASE_ALIGNMENT) > 0)
55 aligned_offset += (I40E_HMC_L2OBJ_BASE_ALIGNMENT -
56 (offset % I40E_HMC_L2OBJ_BASE_ALIGNMENT));
58 return aligned_offset;
62 * i40e_calculate_l2fpm_size - calculates layer 2 FPM memory size
63 * @txq_num: number of Tx queues needing backing context
64 * @rxq_num: number of Rx queues needing backing context
65 * @fcoe_cntx_num: amount of FCoE statefull contexts needing backing context
66 * @fcoe_filt_num: number of FCoE filters needing backing context
68 * Calculates the maximum amount of memory for the function required, based
69 * on the number of resources it must provide context for.
71 u64 i40e_calculate_l2fpm_size(u32 txq_num, u32 rxq_num,
72 u32 fcoe_cntx_num, u32 fcoe_filt_num)
76 fpm_size = txq_num * I40E_HMC_OBJ_SIZE_TXQ;
77 fpm_size = i40e_align_l2obj_base(fpm_size);
79 fpm_size += (rxq_num * I40E_HMC_OBJ_SIZE_RXQ);
80 fpm_size = i40e_align_l2obj_base(fpm_size);
82 fpm_size += (fcoe_cntx_num * I40E_HMC_OBJ_SIZE_FCOE_CNTX);
83 fpm_size = i40e_align_l2obj_base(fpm_size);
85 fpm_size += (fcoe_filt_num * I40E_HMC_OBJ_SIZE_FCOE_FILT);
86 fpm_size = i40e_align_l2obj_base(fpm_size);
92 * i40e_init_lan_hmc - initialize i40e_hmc_info struct
93 * @hw: pointer to the HW structure
94 * @txq_num: number of Tx queues needing backing context
95 * @rxq_num: number of Rx queues needing backing context
96 * @fcoe_cntx_num: amount of FCoE statefull contexts needing backing context
97 * @fcoe_filt_num: number of FCoE filters needing backing context
99 * This function will be called once per physical function initialization.
100 * It will fill out the i40e_hmc_obj_info structure for LAN objects based on
101 * the driver's provided input, as well as information from the HMC itself
105 * - HMC Resource Profile has been selected before calling this function.
107 enum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
108 u32 rxq_num, u32 fcoe_cntx_num,
111 struct i40e_hmc_obj_info *obj, *full_obj;
112 enum i40e_status_code ret_code = I40E_SUCCESS;
116 hw->hmc.signature = I40E_HMC_INFO_SIGNATURE;
117 hw->hmc.hmc_fn_id = hw->pf_id;
119 /* allocate memory for hmc_obj */
120 ret_code = i40e_allocate_virt_mem(hw, &hw->hmc.hmc_obj_virt_mem,
121 sizeof(struct i40e_hmc_obj_info) * I40E_HMC_LAN_MAX);
123 goto init_lan_hmc_out;
124 hw->hmc.hmc_obj = (struct i40e_hmc_obj_info *)
125 hw->hmc.hmc_obj_virt_mem.va;
127 /* The full object will be used to create the LAN HMC SD */
128 full_obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_FULL];
129 full_obj->max_cnt = 0;
134 /* Tx queue context information */
135 obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_TX];
136 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX);
139 size_exp = rd32(hw, I40E_GLHMC_LANTXOBJSZ);
140 obj->size = BIT_ULL(size_exp);
142 /* validate values requested by driver don't exceed HMC capacity */
143 if (txq_num > obj->max_cnt) {
144 ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
145 DEBUGOUT3("i40e_init_lan_hmc: Tx context: asks for 0x%x but max allowed is 0x%x, returns error %d\n",
146 txq_num, obj->max_cnt, ret_code);
150 /* aggregate values into the full LAN object for later */
151 full_obj->max_cnt += obj->max_cnt;
152 full_obj->cnt += obj->cnt;
154 /* Rx queue context information */
155 obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_RX];
156 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX);
158 obj->base = hw->hmc.hmc_obj[I40E_HMC_LAN_TX].base +
159 (hw->hmc.hmc_obj[I40E_HMC_LAN_TX].cnt *
160 hw->hmc.hmc_obj[I40E_HMC_LAN_TX].size);
161 obj->base = i40e_align_l2obj_base(obj->base);
162 size_exp = rd32(hw, I40E_GLHMC_LANRXOBJSZ);
163 obj->size = BIT_ULL(size_exp);
165 /* validate values requested by driver don't exceed HMC capacity */
166 if (rxq_num > obj->max_cnt) {
167 ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
168 DEBUGOUT3("i40e_init_lan_hmc: Rx context: asks for 0x%x but max allowed is 0x%x, returns error %d\n",
169 rxq_num, obj->max_cnt, ret_code);
173 /* aggregate values into the full LAN object for later */
174 full_obj->max_cnt += obj->max_cnt;
175 full_obj->cnt += obj->cnt;
177 /* FCoE context information */
178 obj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX];
179 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEMAX);
180 obj->cnt = fcoe_cntx_num;
181 obj->base = hw->hmc.hmc_obj[I40E_HMC_LAN_RX].base +
182 (hw->hmc.hmc_obj[I40E_HMC_LAN_RX].cnt *
183 hw->hmc.hmc_obj[I40E_HMC_LAN_RX].size);
184 obj->base = i40e_align_l2obj_base(obj->base);
185 size_exp = rd32(hw, I40E_GLHMC_FCOEDDPOBJSZ);
186 obj->size = BIT_ULL(size_exp);
188 /* validate values requested by driver don't exceed HMC capacity */
189 if (fcoe_cntx_num > obj->max_cnt) {
190 ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
191 DEBUGOUT3("i40e_init_lan_hmc: FCoE context: asks for 0x%x but max allowed is 0x%x, returns error %d\n",
192 fcoe_cntx_num, obj->max_cnt, ret_code);
196 /* aggregate values into the full LAN object for later */
197 full_obj->max_cnt += obj->max_cnt;
198 full_obj->cnt += obj->cnt;
200 /* FCoE filter information */
201 obj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_FILT];
202 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEFMAX);
203 obj->cnt = fcoe_filt_num;
204 obj->base = hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX].base +
205 (hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX].cnt *
206 hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX].size);
207 obj->base = i40e_align_l2obj_base(obj->base);
208 size_exp = rd32(hw, I40E_GLHMC_FCOEFOBJSZ);
209 obj->size = BIT_ULL(size_exp);
211 /* validate values requested by driver don't exceed HMC capacity */
212 if (fcoe_filt_num > obj->max_cnt) {
213 ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
214 DEBUGOUT3("i40e_init_lan_hmc: FCoE filter: asks for 0x%x but max allowed is 0x%x, returns error %d\n",
215 fcoe_filt_num, obj->max_cnt, ret_code);
219 /* aggregate values into the full LAN object for later */
220 full_obj->max_cnt += obj->max_cnt;
221 full_obj->cnt += obj->cnt;
223 hw->hmc.first_sd_index = 0;
224 hw->hmc.sd_table.ref_cnt = 0;
225 l2fpm_size = i40e_calculate_l2fpm_size(txq_num, rxq_num, fcoe_cntx_num,
227 if (NULL == hw->hmc.sd_table.sd_entry) {
228 hw->hmc.sd_table.sd_cnt = (u32)
229 (l2fpm_size + I40E_HMC_DIRECT_BP_SIZE - 1) /
230 I40E_HMC_DIRECT_BP_SIZE;
232 /* allocate the sd_entry members in the sd_table */
233 ret_code = i40e_allocate_virt_mem(hw, &hw->hmc.sd_table.addr,
234 (sizeof(struct i40e_hmc_sd_entry) *
235 hw->hmc.sd_table.sd_cnt));
238 hw->hmc.sd_table.sd_entry =
239 (struct i40e_hmc_sd_entry *)hw->hmc.sd_table.addr.va;
241 /* store in the LAN full object for later */
242 full_obj->size = l2fpm_size;
247 if (hw->hmc.hmc_obj_virt_mem.va)
248 i40e_free_virt_mem(hw, &hw->hmc.hmc_obj_virt_mem);
254 * i40e_remove_pd_page - Remove a page from the page descriptor table
255 * @hw: pointer to the HW structure
256 * @hmc_info: pointer to the HMC configuration information structure
257 * @idx: segment descriptor index to find the relevant page descriptor
260 * 1. Marks the entry in pd table (for paged address mode) invalid
261 * 2. write to register PMPDINV to invalidate the backing page in FV cache
262 * 3. Decrement the ref count for pd_entry
264 * 1. caller can deallocate the memory used by pd after this function
267 static enum i40e_status_code i40e_remove_pd_page(struct i40e_hw *hw,
268 struct i40e_hmc_info *hmc_info,
271 enum i40e_status_code ret_code = I40E_SUCCESS;
273 if (i40e_prep_remove_pd_page(hmc_info, idx) == I40E_SUCCESS)
274 ret_code = i40e_remove_pd_page_new(hw, hmc_info, idx, TRUE);
280 * i40e_remove_sd_bp - remove a backing page from a segment descriptor
281 * @hw: pointer to our HW structure
282 * @hmc_info: pointer to the HMC configuration information structure
283 * @idx: the page index
286 * 1. Marks the entry in sd table (for direct address mode) invalid
287 * 2. write to register PMSDCMD, PMSDDATALOW(PMSDDATALOW.PMSDVALID set
288 * to 0) and PMSDDATAHIGH to invalidate the sd page
289 * 3. Decrement the ref count for the sd_entry
291 * 1. caller can deallocate the memory used by backing storage after this
294 static enum i40e_status_code i40e_remove_sd_bp(struct i40e_hw *hw,
295 struct i40e_hmc_info *hmc_info,
298 enum i40e_status_code ret_code = I40E_SUCCESS;
300 if (i40e_prep_remove_sd_bp(hmc_info, idx) == I40E_SUCCESS)
301 ret_code = i40e_remove_sd_bp_new(hw, hmc_info, idx, TRUE);
307 * i40e_create_lan_hmc_object - allocate backing store for hmc objects
308 * @hw: pointer to the HW structure
309 * @info: pointer to i40e_hmc_create_obj_info struct
311 * This will allocate memory for PDs and backing pages and populate
312 * the sd and pd entries.
314 enum i40e_status_code i40e_create_lan_hmc_object(struct i40e_hw *hw,
315 struct i40e_hmc_lan_create_obj_info *info)
317 enum i40e_status_code ret_code = I40E_SUCCESS;
318 struct i40e_hmc_sd_entry *sd_entry;
319 u32 pd_idx1 = 0, pd_lmt1 = 0;
320 u32 pd_idx = 0, pd_lmt = 0;
321 bool pd_error = FALSE;
327 ret_code = I40E_ERR_BAD_PTR;
328 DEBUGOUT("i40e_create_lan_hmc_object: bad info ptr\n");
331 if (NULL == info->hmc_info) {
332 ret_code = I40E_ERR_BAD_PTR;
333 DEBUGOUT("i40e_create_lan_hmc_object: bad hmc_info ptr\n");
336 if (I40E_HMC_INFO_SIGNATURE != info->hmc_info->signature) {
337 ret_code = I40E_ERR_BAD_PTR;
338 DEBUGOUT("i40e_create_lan_hmc_object: bad signature\n");
342 if (info->start_idx >= info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
343 ret_code = I40E_ERR_INVALID_HMC_OBJ_INDEX;
344 DEBUGOUT1("i40e_create_lan_hmc_object: returns error %d\n",
348 if ((info->start_idx + info->count) >
349 info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
350 ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
351 DEBUGOUT1("i40e_create_lan_hmc_object: returns error %d\n",
356 /* find sd index and limit */
357 I40E_FIND_SD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,
358 info->start_idx, info->count,
360 if (sd_idx >= info->hmc_info->sd_table.sd_cnt ||
361 sd_lmt > info->hmc_info->sd_table.sd_cnt) {
362 ret_code = I40E_ERR_INVALID_SD_INDEX;
366 I40E_FIND_PD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,
367 info->start_idx, info->count, &pd_idx,
370 /* This is to cover for cases where you may not want to have an SD with
371 * the full 2M memory but something smaller. By not filling out any
372 * size, the function will default the SD size to be 2M.
374 if (info->direct_mode_sz == 0)
375 sd_size = I40E_HMC_DIRECT_BP_SIZE;
377 sd_size = info->direct_mode_sz;
379 /* check if all the sds are valid. If not, allocate a page and
382 for (j = sd_idx; j < sd_lmt; j++) {
383 /* update the sd table entry */
384 ret_code = i40e_add_sd_table_entry(hw, info->hmc_info, j,
387 if (I40E_SUCCESS != ret_code)
389 sd_entry = &info->hmc_info->sd_table.sd_entry[j];
390 if (I40E_SD_TYPE_PAGED == sd_entry->entry_type) {
391 /* check if all the pds in this sd are valid. If not,
392 * allocate a page and initialize it.
395 /* find pd_idx and pd_lmt in this sd */
396 pd_idx1 = max(pd_idx, (j * I40E_HMC_MAX_BP_COUNT));
397 pd_lmt1 = min(pd_lmt,
398 ((j + 1) * I40E_HMC_MAX_BP_COUNT));
399 for (i = pd_idx1; i < pd_lmt1; i++) {
400 /* update the pd table entry */
401 ret_code = i40e_add_pd_table_entry(hw,
404 if (I40E_SUCCESS != ret_code) {
410 /* remove the backing pages from pd_idx1 to i */
411 while (i && (i > pd_idx1)) {
412 i40e_remove_pd_bp(hw, info->hmc_info,
418 if (!sd_entry->valid) {
419 sd_entry->valid = TRUE;
420 switch (sd_entry->entry_type) {
421 case I40E_SD_TYPE_PAGED:
422 I40E_SET_PF_SD_ENTRY(hw,
423 sd_entry->u.pd_table.pd_page_addr.pa,
424 j, sd_entry->entry_type);
426 case I40E_SD_TYPE_DIRECT:
427 I40E_SET_PF_SD_ENTRY(hw, sd_entry->u.bp.addr.pa,
428 j, sd_entry->entry_type);
431 ret_code = I40E_ERR_INVALID_SD_TYPE;
439 /* cleanup for sd entries from j to sd_idx */
440 while (j && (j > sd_idx)) {
441 sd_entry = &info->hmc_info->sd_table.sd_entry[j - 1];
442 switch (sd_entry->entry_type) {
443 case I40E_SD_TYPE_PAGED:
444 pd_idx1 = max(pd_idx,
445 ((j - 1) * I40E_HMC_MAX_BP_COUNT));
446 pd_lmt1 = min(pd_lmt, (j * I40E_HMC_MAX_BP_COUNT));
447 for (i = pd_idx1; i < pd_lmt1; i++)
448 i40e_remove_pd_bp(hw, info->hmc_info, i);
449 i40e_remove_pd_page(hw, info->hmc_info, (j - 1));
451 case I40E_SD_TYPE_DIRECT:
452 i40e_remove_sd_bp(hw, info->hmc_info, (j - 1));
455 ret_code = I40E_ERR_INVALID_SD_TYPE;
465 * i40e_configure_lan_hmc - prepare the HMC backing store
466 * @hw: pointer to the hw structure
467 * @model: the model for the layout of the SD/PD tables
469 * - This function will be called once per physical function initialization.
470 * - This function will be called after i40e_init_lan_hmc() and before
471 * any LAN/FCoE HMC objects can be created.
473 enum i40e_status_code i40e_configure_lan_hmc(struct i40e_hw *hw,
474 enum i40e_hmc_model model)
476 struct i40e_hmc_lan_create_obj_info info;
477 u8 hmc_fn_id = hw->hmc.hmc_fn_id;
478 struct i40e_hmc_obj_info *obj;
479 enum i40e_status_code ret_code = I40E_SUCCESS;
481 /* Initialize part of the create object info struct */
482 info.hmc_info = &hw->hmc;
483 info.rsrc_type = I40E_HMC_LAN_FULL;
485 info.direct_mode_sz = hw->hmc.hmc_obj[I40E_HMC_LAN_FULL].size;
487 /* Build the SD entry for the LAN objects */
489 case I40E_HMC_MODEL_DIRECT_PREFERRED:
490 case I40E_HMC_MODEL_DIRECT_ONLY:
491 info.entry_type = I40E_SD_TYPE_DIRECT;
492 /* Make one big object, a single SD */
494 ret_code = i40e_create_lan_hmc_object(hw, &info);
495 if ((ret_code != I40E_SUCCESS) && (model == I40E_HMC_MODEL_DIRECT_PREFERRED))
497 else if (ret_code != I40E_SUCCESS)
498 goto configure_lan_hmc_out;
499 /* else clause falls through the break */
501 case I40E_HMC_MODEL_PAGED_ONLY:
503 info.entry_type = I40E_SD_TYPE_PAGED;
504 /* Make one big object in the PD table */
506 ret_code = i40e_create_lan_hmc_object(hw, &info);
507 if (ret_code != I40E_SUCCESS)
508 goto configure_lan_hmc_out;
511 /* unsupported type */
512 ret_code = I40E_ERR_INVALID_SD_TYPE;
513 DEBUGOUT1("i40e_configure_lan_hmc: Unknown SD type: %d\n",
515 goto configure_lan_hmc_out;
518 /* Configure and program the FPM registers so objects can be created */
521 obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_TX];
522 wr32(hw, I40E_GLHMC_LANTXBASE(hmc_fn_id),
523 (u32)((obj->base & I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK) / 512));
524 wr32(hw, I40E_GLHMC_LANTXCNT(hmc_fn_id), obj->cnt);
527 obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_RX];
528 wr32(hw, I40E_GLHMC_LANRXBASE(hmc_fn_id),
529 (u32)((obj->base & I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK) / 512));
530 wr32(hw, I40E_GLHMC_LANRXCNT(hmc_fn_id), obj->cnt);
533 obj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX];
534 wr32(hw, I40E_GLHMC_FCOEDDPBASE(hmc_fn_id),
535 (u32)((obj->base & I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK) / 512));
536 wr32(hw, I40E_GLHMC_FCOEDDPCNT(hmc_fn_id), obj->cnt);
539 obj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_FILT];
540 wr32(hw, I40E_GLHMC_FCOEFBASE(hmc_fn_id),
541 (u32)((obj->base & I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK) / 512));
542 wr32(hw, I40E_GLHMC_FCOEFCNT(hmc_fn_id), obj->cnt);
544 configure_lan_hmc_out:
549 * i40e_delete_lan_hmc_object - remove hmc objects
550 * @hw: pointer to the HW structure
551 * @info: pointer to i40e_hmc_delete_obj_info struct
553 * This will de-populate the SDs and PDs. It frees
554 * the memory for PDS and backing storage. After this function is returned,
555 * caller should deallocate memory allocated previously for
556 * book-keeping information about PDs and backing storage.
558 enum i40e_status_code i40e_delete_lan_hmc_object(struct i40e_hw *hw,
559 struct i40e_hmc_lan_delete_obj_info *info)
561 enum i40e_status_code ret_code = I40E_SUCCESS;
562 struct i40e_hmc_pd_table *pd_table;
563 u32 pd_idx, pd_lmt, rel_pd_idx;
568 ret_code = I40E_ERR_BAD_PTR;
569 DEBUGOUT("i40e_delete_hmc_object: bad info ptr\n");
572 if (NULL == info->hmc_info) {
573 ret_code = I40E_ERR_BAD_PTR;
574 DEBUGOUT("i40e_delete_hmc_object: bad info->hmc_info ptr\n");
577 if (I40E_HMC_INFO_SIGNATURE != info->hmc_info->signature) {
578 ret_code = I40E_ERR_BAD_PTR;
579 DEBUGOUT("i40e_delete_hmc_object: bad hmc_info->signature\n");
583 if (NULL == info->hmc_info->sd_table.sd_entry) {
584 ret_code = I40E_ERR_BAD_PTR;
585 DEBUGOUT("i40e_delete_hmc_object: bad sd_entry\n");
589 if (NULL == info->hmc_info->hmc_obj) {
590 ret_code = I40E_ERR_BAD_PTR;
591 DEBUGOUT("i40e_delete_hmc_object: bad hmc_info->hmc_obj\n");
594 if (info->start_idx >= info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
595 ret_code = I40E_ERR_INVALID_HMC_OBJ_INDEX;
596 DEBUGOUT1("i40e_delete_hmc_object: returns error %d\n",
601 if ((info->start_idx + info->count) >
602 info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
603 ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
604 DEBUGOUT1("i40e_delete_hmc_object: returns error %d\n",
609 I40E_FIND_PD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,
610 info->start_idx, info->count, &pd_idx,
613 for (j = pd_idx; j < pd_lmt; j++) {
614 sd_idx = j / I40E_HMC_PD_CNT_IN_SD;
616 if (I40E_SD_TYPE_PAGED !=
617 info->hmc_info->sd_table.sd_entry[sd_idx].entry_type)
620 rel_pd_idx = j % I40E_HMC_PD_CNT_IN_SD;
623 &info->hmc_info->sd_table.sd_entry[sd_idx].u.pd_table;
624 if (pd_table->pd_entry[rel_pd_idx].valid) {
625 ret_code = i40e_remove_pd_bp(hw, info->hmc_info, j);
626 if (I40E_SUCCESS != ret_code)
631 /* find sd index and limit */
632 I40E_FIND_SD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,
633 info->start_idx, info->count,
635 if (sd_idx >= info->hmc_info->sd_table.sd_cnt ||
636 sd_lmt > info->hmc_info->sd_table.sd_cnt) {
637 ret_code = I40E_ERR_INVALID_SD_INDEX;
641 for (i = sd_idx; i < sd_lmt; i++) {
642 if (!info->hmc_info->sd_table.sd_entry[i].valid)
644 switch (info->hmc_info->sd_table.sd_entry[i].entry_type) {
645 case I40E_SD_TYPE_DIRECT:
646 ret_code = i40e_remove_sd_bp(hw, info->hmc_info, i);
647 if (I40E_SUCCESS != ret_code)
650 case I40E_SD_TYPE_PAGED:
651 ret_code = i40e_remove_pd_page(hw, info->hmc_info, i);
652 if (I40E_SUCCESS != ret_code)
664 * i40e_shutdown_lan_hmc - Remove HMC backing store, free allocated memory
665 * @hw: pointer to the hw structure
667 * This must be called by drivers as they are shutting down and being
668 * removed from the OS.
670 enum i40e_status_code i40e_shutdown_lan_hmc(struct i40e_hw *hw)
672 struct i40e_hmc_lan_delete_obj_info info;
673 enum i40e_status_code ret_code;
675 info.hmc_info = &hw->hmc;
676 info.rsrc_type = I40E_HMC_LAN_FULL;
680 /* delete the object */
681 ret_code = i40e_delete_lan_hmc_object(hw, &info);
683 /* free the SD table entry for LAN */
684 i40e_free_virt_mem(hw, &hw->hmc.sd_table.addr);
685 hw->hmc.sd_table.sd_cnt = 0;
686 hw->hmc.sd_table.sd_entry = NULL;
688 /* free memory used for hmc_obj */
689 i40e_free_virt_mem(hw, &hw->hmc.hmc_obj_virt_mem);
690 hw->hmc.hmc_obj = NULL;
695 #define I40E_HMC_STORE(_struct, _ele) \
696 offsetof(struct _struct, _ele), \
697 FIELD_SIZEOF(struct _struct, _ele)
699 struct i40e_context_ele {
706 /* LAN Tx Queue Context */
707 static struct i40e_context_ele i40e_hmc_txq_ce_info[] = {
708 /* Field Width LSB */
709 {I40E_HMC_STORE(i40e_hmc_obj_txq, head), 13, 0 },
710 {I40E_HMC_STORE(i40e_hmc_obj_txq, new_context), 1, 30 },
711 {I40E_HMC_STORE(i40e_hmc_obj_txq, base), 57, 32 },
712 {I40E_HMC_STORE(i40e_hmc_obj_txq, fc_ena), 1, 89 },
713 {I40E_HMC_STORE(i40e_hmc_obj_txq, timesync_ena), 1, 90 },
714 {I40E_HMC_STORE(i40e_hmc_obj_txq, fd_ena), 1, 91 },
715 {I40E_HMC_STORE(i40e_hmc_obj_txq, alt_vlan_ena), 1, 92 },
716 {I40E_HMC_STORE(i40e_hmc_obj_txq, cpuid), 8, 96 },
718 {I40E_HMC_STORE(i40e_hmc_obj_txq, thead_wb), 13, 0 + 128 },
719 {I40E_HMC_STORE(i40e_hmc_obj_txq, head_wb_ena), 1, 32 + 128 },
720 {I40E_HMC_STORE(i40e_hmc_obj_txq, qlen), 13, 33 + 128 },
721 {I40E_HMC_STORE(i40e_hmc_obj_txq, tphrdesc_ena), 1, 46 + 128 },
722 {I40E_HMC_STORE(i40e_hmc_obj_txq, tphrpacket_ena), 1, 47 + 128 },
723 {I40E_HMC_STORE(i40e_hmc_obj_txq, tphwdesc_ena), 1, 48 + 128 },
724 {I40E_HMC_STORE(i40e_hmc_obj_txq, head_wb_addr), 64, 64 + 128 },
726 {I40E_HMC_STORE(i40e_hmc_obj_txq, crc), 32, 0 + (7 * 128) },
727 {I40E_HMC_STORE(i40e_hmc_obj_txq, rdylist), 10, 84 + (7 * 128) },
728 {I40E_HMC_STORE(i40e_hmc_obj_txq, rdylist_act), 1, 94 + (7 * 128) },
732 /* LAN Rx Queue Context */
733 static struct i40e_context_ele i40e_hmc_rxq_ce_info[] = {
734 /* Field Width LSB */
735 { I40E_HMC_STORE(i40e_hmc_obj_rxq, head), 13, 0 },
736 { I40E_HMC_STORE(i40e_hmc_obj_rxq, cpuid), 8, 13 },
737 { I40E_HMC_STORE(i40e_hmc_obj_rxq, base), 57, 32 },
738 { I40E_HMC_STORE(i40e_hmc_obj_rxq, qlen), 13, 89 },
739 { I40E_HMC_STORE(i40e_hmc_obj_rxq, dbuff), 7, 102 },
740 { I40E_HMC_STORE(i40e_hmc_obj_rxq, hbuff), 5, 109 },
741 { I40E_HMC_STORE(i40e_hmc_obj_rxq, dtype), 2, 114 },
742 { I40E_HMC_STORE(i40e_hmc_obj_rxq, dsize), 1, 116 },
743 { I40E_HMC_STORE(i40e_hmc_obj_rxq, crcstrip), 1, 117 },
744 { I40E_HMC_STORE(i40e_hmc_obj_rxq, fc_ena), 1, 118 },
745 { I40E_HMC_STORE(i40e_hmc_obj_rxq, l2tsel), 1, 119 },
746 { I40E_HMC_STORE(i40e_hmc_obj_rxq, hsplit_0), 4, 120 },
747 { I40E_HMC_STORE(i40e_hmc_obj_rxq, hsplit_1), 2, 124 },
748 { I40E_HMC_STORE(i40e_hmc_obj_rxq, showiv), 1, 127 },
749 { I40E_HMC_STORE(i40e_hmc_obj_rxq, rxmax), 14, 174 },
750 { I40E_HMC_STORE(i40e_hmc_obj_rxq, tphrdesc_ena), 1, 193 },
751 { I40E_HMC_STORE(i40e_hmc_obj_rxq, tphwdesc_ena), 1, 194 },
752 { I40E_HMC_STORE(i40e_hmc_obj_rxq, tphdata_ena), 1, 195 },
753 { I40E_HMC_STORE(i40e_hmc_obj_rxq, tphhead_ena), 1, 196 },
754 { I40E_HMC_STORE(i40e_hmc_obj_rxq, lrxqthresh), 3, 198 },
755 { I40E_HMC_STORE(i40e_hmc_obj_rxq, prefena), 1, 201 },
760 * i40e_write_byte - replace HMC context byte
761 * @hmc_bits: pointer to the HMC memory
762 * @ce_info: a description of the struct to be read from
763 * @src: the struct to be read from
765 static void i40e_write_byte(u8 *hmc_bits,
766 struct i40e_context_ele *ce_info,
769 u8 src_byte, dest_byte, mask;
773 /* copy from the next struct field */
774 from = src + ce_info->offset;
776 /* prepare the bits and mask */
777 shift_width = ce_info->lsb % 8;
778 mask = (u8)(BIT(ce_info->width) - 1);
783 /* shift to correct alignment */
784 mask <<= shift_width;
785 src_byte <<= shift_width;
787 /* get the current bits from the target bit string */
788 dest = hmc_bits + (ce_info->lsb / 8);
790 i40e_memcpy(&dest_byte, dest, sizeof(dest_byte), I40E_DMA_TO_NONDMA);
792 dest_byte &= ~mask; /* get the bits not changing */
793 dest_byte |= src_byte; /* add in the new bits */
795 /* put it all back */
796 i40e_memcpy(dest, &dest_byte, sizeof(dest_byte), I40E_NONDMA_TO_DMA);
800 * i40e_write_word - replace HMC context word
801 * @hmc_bits: pointer to the HMC memory
802 * @ce_info: a description of the struct to be read from
803 * @src: the struct to be read from
805 static void i40e_write_word(u8 *hmc_bits,
806 struct i40e_context_ele *ce_info,
814 /* copy from the next struct field */
815 from = src + ce_info->offset;
817 /* prepare the bits and mask */
818 shift_width = ce_info->lsb % 8;
819 mask = BIT(ce_info->width) - 1;
821 /* don't swizzle the bits until after the mask because the mask bits
822 * will be in a different bit position on big endian machines
824 src_word = *(u16 *)from;
827 /* shift to correct alignment */
828 mask <<= shift_width;
829 src_word <<= shift_width;
831 /* get the current bits from the target bit string */
832 dest = hmc_bits + (ce_info->lsb / 8);
834 i40e_memcpy(&dest_word, dest, sizeof(dest_word), I40E_DMA_TO_NONDMA);
836 dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
837 dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
839 /* put it all back */
840 i40e_memcpy(dest, &dest_word, sizeof(dest_word), I40E_NONDMA_TO_DMA);
844 * i40e_write_dword - replace HMC context dword
845 * @hmc_bits: pointer to the HMC memory
846 * @ce_info: a description of the struct to be read from
847 * @src: the struct to be read from
849 static void i40e_write_dword(u8 *hmc_bits,
850 struct i40e_context_ele *ce_info,
858 /* copy from the next struct field */
859 from = src + ce_info->offset;
861 /* prepare the bits and mask */
862 shift_width = ce_info->lsb % 8;
864 /* if the field width is exactly 32 on an x86 machine, then the shift
865 * operation will not work because the SHL instructions count is masked
866 * to 5 bits so the shift will do nothing
868 if (ce_info->width < 32)
869 mask = BIT(ce_info->width) - 1;
873 /* don't swizzle the bits until after the mask because the mask bits
874 * will be in a different bit position on big endian machines
876 src_dword = *(u32 *)from;
879 /* shift to correct alignment */
880 mask <<= shift_width;
881 src_dword <<= shift_width;
883 /* get the current bits from the target bit string */
884 dest = hmc_bits + (ce_info->lsb / 8);
886 i40e_memcpy(&dest_dword, dest, sizeof(dest_dword), I40E_DMA_TO_NONDMA);
888 dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */
889 dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */
891 /* put it all back */
892 i40e_memcpy(dest, &dest_dword, sizeof(dest_dword), I40E_NONDMA_TO_DMA);
896 * i40e_write_qword - replace HMC context qword
897 * @hmc_bits: pointer to the HMC memory
898 * @ce_info: a description of the struct to be read from
899 * @src: the struct to be read from
901 static void i40e_write_qword(u8 *hmc_bits,
902 struct i40e_context_ele *ce_info,
910 /* copy from the next struct field */
911 from = src + ce_info->offset;
913 /* prepare the bits and mask */
914 shift_width = ce_info->lsb % 8;
916 /* if the field width is exactly 64 on an x86 machine, then the shift
917 * operation will not work because the SHL instructions count is masked
918 * to 6 bits so the shift will do nothing
920 if (ce_info->width < 64)
921 mask = BIT_ULL(ce_info->width) - 1;
925 /* don't swizzle the bits until after the mask because the mask bits
926 * will be in a different bit position on big endian machines
928 src_qword = *(u64 *)from;
931 /* shift to correct alignment */
932 mask <<= shift_width;
933 src_qword <<= shift_width;
935 /* get the current bits from the target bit string */
936 dest = hmc_bits + (ce_info->lsb / 8);
938 i40e_memcpy(&dest_qword, dest, sizeof(dest_qword), I40E_DMA_TO_NONDMA);
940 dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */
941 dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */
943 /* put it all back */
944 i40e_memcpy(dest, &dest_qword, sizeof(dest_qword), I40E_NONDMA_TO_DMA);
948 * i40e_read_byte - read HMC context byte into struct
949 * @hmc_bits: pointer to the HMC memory
950 * @ce_info: a description of the struct to be filled
951 * @dest: the struct to be filled
953 static void i40e_read_byte(u8 *hmc_bits,
954 struct i40e_context_ele *ce_info,
961 /* prepare the bits and mask */
962 shift_width = ce_info->lsb % 8;
963 mask = (u8)(BIT(ce_info->width) - 1);
965 /* shift to correct alignment */
966 mask <<= shift_width;
968 /* get the current bits from the src bit string */
969 src = hmc_bits + (ce_info->lsb / 8);
971 i40e_memcpy(&dest_byte, src, sizeof(dest_byte), I40E_DMA_TO_NONDMA);
973 dest_byte &= ~(mask);
975 dest_byte >>= shift_width;
977 /* get the address from the struct field */
978 target = dest + ce_info->offset;
980 /* put it back in the struct */
981 i40e_memcpy(target, &dest_byte, sizeof(dest_byte), I40E_NONDMA_TO_DMA);
985 * i40e_read_word - read HMC context word into struct
986 * @hmc_bits: pointer to the HMC memory
987 * @ce_info: a description of the struct to be filled
988 * @dest: the struct to be filled
990 static void i40e_read_word(u8 *hmc_bits,
991 struct i40e_context_ele *ce_info,
999 /* prepare the bits and mask */
1000 shift_width = ce_info->lsb % 8;
1001 mask = BIT(ce_info->width) - 1;
1003 /* shift to correct alignment */
1004 mask <<= shift_width;
1006 /* get the current bits from the src bit string */
1007 src = hmc_bits + (ce_info->lsb / 8);
1009 i40e_memcpy(&src_word, src, sizeof(src_word), I40E_DMA_TO_NONDMA);
1011 /* the data in the memory is stored as little endian so mask it
1014 src_word &= ~(CPU_TO_LE16(mask));
1016 /* get the data back into host order before shifting */
1017 dest_word = LE16_TO_CPU(src_word);
1019 dest_word >>= shift_width;
1021 /* get the address from the struct field */
1022 target = dest + ce_info->offset;
1024 /* put it back in the struct */
1025 i40e_memcpy(target, &dest_word, sizeof(dest_word), I40E_NONDMA_TO_DMA);
1029 * i40e_read_dword - read HMC context dword into struct
1030 * @hmc_bits: pointer to the HMC memory
1031 * @ce_info: a description of the struct to be filled
1032 * @dest: the struct to be filled
1034 static void i40e_read_dword(u8 *hmc_bits,
1035 struct i40e_context_ele *ce_info,
1038 u32 dest_dword, mask;
1043 /* prepare the bits and mask */
1044 shift_width = ce_info->lsb % 8;
1046 /* if the field width is exactly 32 on an x86 machine, then the shift
1047 * operation will not work because the SHL instructions count is masked
1048 * to 5 bits so the shift will do nothing
1050 if (ce_info->width < 32)
1051 mask = BIT(ce_info->width) - 1;
1055 /* shift to correct alignment */
1056 mask <<= shift_width;
1058 /* get the current bits from the src bit string */
1059 src = hmc_bits + (ce_info->lsb / 8);
1061 i40e_memcpy(&src_dword, src, sizeof(src_dword), I40E_DMA_TO_NONDMA);
1063 /* the data in the memory is stored as little endian so mask it
1066 src_dword &= ~(CPU_TO_LE32(mask));
1068 /* get the data back into host order before shifting */
1069 dest_dword = LE32_TO_CPU(src_dword);
1071 dest_dword >>= shift_width;
1073 /* get the address from the struct field */
1074 target = dest + ce_info->offset;
1076 /* put it back in the struct */
1077 i40e_memcpy(target, &dest_dword, sizeof(dest_dword),
1078 I40E_NONDMA_TO_DMA);
1082 * i40e_read_qword - read HMC context qword into struct
1083 * @hmc_bits: pointer to the HMC memory
1084 * @ce_info: a description of the struct to be filled
1085 * @dest: the struct to be filled
1087 static void i40e_read_qword(u8 *hmc_bits,
1088 struct i40e_context_ele *ce_info,
1091 u64 dest_qword, mask;
1096 /* prepare the bits and mask */
1097 shift_width = ce_info->lsb % 8;
1099 /* if the field width is exactly 64 on an x86 machine, then the shift
1100 * operation will not work because the SHL instructions count is masked
1101 * to 6 bits so the shift will do nothing
1103 if (ce_info->width < 64)
1104 mask = BIT_ULL(ce_info->width) - 1;
1108 /* shift to correct alignment */
1109 mask <<= shift_width;
1111 /* get the current bits from the src bit string */
1112 src = hmc_bits + (ce_info->lsb / 8);
1114 i40e_memcpy(&src_qword, src, sizeof(src_qword), I40E_DMA_TO_NONDMA);
1116 /* the data in the memory is stored as little endian so mask it
1119 src_qword &= ~(CPU_TO_LE64(mask));
1121 /* get the data back into host order before shifting */
1122 dest_qword = LE64_TO_CPU(src_qword);
1124 dest_qword >>= shift_width;
1126 /* get the address from the struct field */
1127 target = dest + ce_info->offset;
1129 /* put it back in the struct */
1130 i40e_memcpy(target, &dest_qword, sizeof(dest_qword),
1131 I40E_NONDMA_TO_DMA);
1135 * i40e_get_hmc_context - extract HMC context bits
1136 * @context_bytes: pointer to the context bit array
1137 * @ce_info: a description of the struct to be filled
1138 * @dest: the struct to be filled
1140 static enum i40e_status_code i40e_get_hmc_context(u8 *context_bytes,
1141 struct i40e_context_ele *ce_info,
1146 for (f = 0; ce_info[f].width != 0; f++) {
1147 switch (ce_info[f].size_of) {
1149 i40e_read_byte(context_bytes, &ce_info[f], dest);
1152 i40e_read_word(context_bytes, &ce_info[f], dest);
1155 i40e_read_dword(context_bytes, &ce_info[f], dest);
1158 i40e_read_qword(context_bytes, &ce_info[f], dest);
1161 /* nothing to do, just keep going */
1166 return I40E_SUCCESS;
1170 * i40e_clear_hmc_context - zero out the HMC context bits
1171 * @hw: the hardware struct
1172 * @context_bytes: pointer to the context bit array (DMA memory)
1173 * @hmc_type: the type of HMC resource
1175 static enum i40e_status_code i40e_clear_hmc_context(struct i40e_hw *hw,
1177 enum i40e_hmc_lan_rsrc_type hmc_type)
1179 /* clean the bit array */
1180 i40e_memset(context_bytes, 0, (u32)hw->hmc.hmc_obj[hmc_type].size,
1183 return I40E_SUCCESS;
1187 * i40e_set_hmc_context - replace HMC context bits
1188 * @context_bytes: pointer to the context bit array
1189 * @ce_info: a description of the struct to be filled
1190 * @dest: the struct to be filled
1192 static enum i40e_status_code i40e_set_hmc_context(u8 *context_bytes,
1193 struct i40e_context_ele *ce_info,
1198 for (f = 0; ce_info[f].width != 0; f++) {
1200 /* we have to deal with each element of the HMC using the
1201 * correct size so that we are correct regardless of the
1202 * endianness of the machine
1204 switch (ce_info[f].size_of) {
1206 i40e_write_byte(context_bytes, &ce_info[f], dest);
1209 i40e_write_word(context_bytes, &ce_info[f], dest);
1212 i40e_write_dword(context_bytes, &ce_info[f], dest);
1215 i40e_write_qword(context_bytes, &ce_info[f], dest);
1220 return I40E_SUCCESS;
1224 * i40e_hmc_get_object_va - retrieves an object's virtual address
1225 * @hw: pointer to the hw structure
1226 * @object_base: pointer to u64 to get the va
1227 * @rsrc_type: the hmc resource type
1228 * @obj_idx: hmc object index
1230 * This function retrieves the object's virtual address from the object
1231 * base pointer. This function is used for LAN Queue contexts.
1234 enum i40e_status_code i40e_hmc_get_object_va(struct i40e_hw *hw,
1236 enum i40e_hmc_lan_rsrc_type rsrc_type,
1239 u32 obj_offset_in_sd, obj_offset_in_pd;
1240 struct i40e_hmc_info *hmc_info = &hw->hmc;
1241 struct i40e_hmc_sd_entry *sd_entry;
1242 struct i40e_hmc_pd_entry *pd_entry;
1243 u32 pd_idx, pd_lmt, rel_pd_idx;
1244 enum i40e_status_code ret_code = I40E_SUCCESS;
1245 u64 obj_offset_in_fpm;
1248 if (NULL == hmc_info->hmc_obj) {
1249 ret_code = I40E_ERR_BAD_PTR;
1250 DEBUGOUT("i40e_hmc_get_object_va: bad hmc_info->hmc_obj ptr\n");
1253 if (NULL == object_base) {
1254 ret_code = I40E_ERR_BAD_PTR;
1255 DEBUGOUT("i40e_hmc_get_object_va: bad object_base ptr\n");
1258 if (I40E_HMC_INFO_SIGNATURE != hmc_info->signature) {
1259 ret_code = I40E_ERR_BAD_PTR;
1260 DEBUGOUT("i40e_hmc_get_object_va: bad hmc_info->signature\n");
1263 if (obj_idx >= hmc_info->hmc_obj[rsrc_type].cnt) {
1264 DEBUGOUT1("i40e_hmc_get_object_va: returns error %d\n",
1266 ret_code = I40E_ERR_INVALID_HMC_OBJ_INDEX;
1269 /* find sd index and limit */
1270 I40E_FIND_SD_INDEX_LIMIT(hmc_info, rsrc_type, obj_idx, 1,
1273 sd_entry = &hmc_info->sd_table.sd_entry[sd_idx];
1274 obj_offset_in_fpm = hmc_info->hmc_obj[rsrc_type].base +
1275 hmc_info->hmc_obj[rsrc_type].size * obj_idx;
1277 if (I40E_SD_TYPE_PAGED == sd_entry->entry_type) {
1278 I40E_FIND_PD_INDEX_LIMIT(hmc_info, rsrc_type, obj_idx, 1,
1280 rel_pd_idx = pd_idx % I40E_HMC_PD_CNT_IN_SD;
1281 pd_entry = &sd_entry->u.pd_table.pd_entry[rel_pd_idx];
1282 obj_offset_in_pd = (u32)(obj_offset_in_fpm %
1283 I40E_HMC_PAGED_BP_SIZE);
1284 *object_base = (u8 *)pd_entry->bp.addr.va + obj_offset_in_pd;
1286 obj_offset_in_sd = (u32)(obj_offset_in_fpm %
1287 I40E_HMC_DIRECT_BP_SIZE);
1288 *object_base = (u8 *)sd_entry->u.bp.addr.va + obj_offset_in_sd;
1295 * i40e_get_lan_tx_queue_context - return the HMC context for the queue
1296 * @hw: the hardware struct
1297 * @queue: the queue we care about
1298 * @s: the struct to be filled
1300 enum i40e_status_code i40e_get_lan_tx_queue_context(struct i40e_hw *hw,
1302 struct i40e_hmc_obj_txq *s)
1304 enum i40e_status_code err;
1307 err = i40e_hmc_get_object_va(hw, &context_bytes, I40E_HMC_LAN_TX, queue);
1311 return i40e_get_hmc_context(context_bytes,
1312 i40e_hmc_txq_ce_info, (u8 *)s);
1316 * i40e_clear_lan_tx_queue_context - clear the HMC context for the queue
1317 * @hw: the hardware struct
1318 * @queue: the queue we care about
1320 enum i40e_status_code i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
1323 enum i40e_status_code err;
1326 err = i40e_hmc_get_object_va(hw, &context_bytes, I40E_HMC_LAN_TX, queue);
1330 return i40e_clear_hmc_context(hw, context_bytes, I40E_HMC_LAN_TX);
1334 * i40e_set_lan_tx_queue_context - set the HMC context for the queue
1335 * @hw: the hardware struct
1336 * @queue: the queue we care about
1337 * @s: the struct to be filled
1339 enum i40e_status_code i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
1341 struct i40e_hmc_obj_txq *s)
1343 enum i40e_status_code err;
1346 err = i40e_hmc_get_object_va(hw, &context_bytes, I40E_HMC_LAN_TX, queue);
1350 return i40e_set_hmc_context(context_bytes,
1351 i40e_hmc_txq_ce_info, (u8 *)s);
1355 * i40e_get_lan_rx_queue_context - return the HMC context for the queue
1356 * @hw: the hardware struct
1357 * @queue: the queue we care about
1358 * @s: the struct to be filled
1360 enum i40e_status_code i40e_get_lan_rx_queue_context(struct i40e_hw *hw,
1362 struct i40e_hmc_obj_rxq *s)
1364 enum i40e_status_code err;
1367 err = i40e_hmc_get_object_va(hw, &context_bytes, I40E_HMC_LAN_RX, queue);
1371 return i40e_get_hmc_context(context_bytes,
1372 i40e_hmc_rxq_ce_info, (u8 *)s);
1376 * i40e_clear_lan_rx_queue_context - clear the HMC context for the queue
1377 * @hw: the hardware struct
1378 * @queue: the queue we care about
1380 enum i40e_status_code i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
1383 enum i40e_status_code err;
1386 err = i40e_hmc_get_object_va(hw, &context_bytes, I40E_HMC_LAN_RX, queue);
1390 return i40e_clear_hmc_context(hw, context_bytes, I40E_HMC_LAN_RX);
1394 * i40e_set_lan_rx_queue_context - set the HMC context for the queue
1395 * @hw: the hardware struct
1396 * @queue: the queue we care about
1397 * @s: the struct to be filled
1399 enum i40e_status_code i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
1401 struct i40e_hmc_obj_rxq *s)
1403 enum i40e_status_code err;
1406 err = i40e_hmc_get_object_va(hw, &context_bytes, I40E_HMC_LAN_RX, queue);
1410 return i40e_set_hmc_context(context_bytes,
1411 i40e_hmc_rxq_ce_info, (u8 *)s);