1 /******************************************************************************
3 Copyright (c) 2013-2015, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
35 #include "i40e_prototype.h"
37 enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
39 enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
41 enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
42 u16 *words, u16 *data);
43 enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
44 u16 *words, u16 *data);
45 enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
46 u32 offset, u16 words, void *data,
50 * i40e_init_nvm_ops - Initialize NVM function pointers
51 * @hw: pointer to the HW structure
53 * Setup the function pointers and the NVM info structure. Should be called
54 * once per NVM initialization, e.g. inside the i40e_init_shared_code().
55 * Please notice that the NVM term is used here (& in all methods covered
56 * in this file) as an equivalent of the FLASH part mapped into the SR.
57 * We are accessing FLASH always thru the Shadow RAM.
59 enum i40e_status_code i40e_init_nvm(struct i40e_hw *hw)
61 struct i40e_nvm_info *nvm = &hw->nvm;
62 enum i40e_status_code ret_code = I40E_SUCCESS;
66 DEBUGFUNC("i40e_init_nvm");
68 /* The SR size is stored regardless of the nvm programming mode
69 * as the blank mode may be used in the factory line.
71 gens = rd32(hw, I40E_GLNVM_GENS);
72 sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
73 I40E_GLNVM_GENS_SR_SIZE_SHIFT);
74 /* Switching to words (sr_size contains power of 2KB) */
75 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB;
77 /* Check if we are in the normal or blank NVM programming mode */
78 fla = rd32(hw, I40E_GLNVM_FLA);
79 if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */
81 nvm->timeout = I40E_MAX_NVM_TIMEOUT;
82 nvm->blank_nvm_mode = FALSE;
83 } else { /* Blank programming mode */
84 nvm->blank_nvm_mode = TRUE;
85 ret_code = I40E_ERR_NVM_BLANK_MODE;
86 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n");
93 * i40e_acquire_nvm - Generic request for acquiring the NVM ownership
94 * @hw: pointer to the HW structure
95 * @access: NVM access type (read or write)
97 * This function will request NVM ownership for reading
98 * via the proper Admin Command.
100 enum i40e_status_code i40e_acquire_nvm(struct i40e_hw *hw,
101 enum i40e_aq_resource_access_type access)
103 enum i40e_status_code ret_code = I40E_SUCCESS;
107 DEBUGFUNC("i40e_acquire_nvm");
109 if (hw->nvm.blank_nvm_mode)
110 goto i40e_i40e_acquire_nvm_exit;
112 ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
113 0, &time_left, NULL);
114 /* Reading the Global Device Timer */
115 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
117 /* Store the timeout */
118 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime;
121 i40e_debug(hw, I40E_DEBUG_NVM,
122 "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n",
123 access, time_left, ret_code, hw->aq.asq_last_status);
125 if (ret_code && time_left) {
126 /* Poll until the current NVM owner timeouts */
127 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime;
128 while ((gtime < timeout) && time_left) {
130 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
131 ret_code = i40e_aq_request_resource(hw,
132 I40E_NVM_RESOURCE_ID,
133 access, 0, &time_left,
135 if (ret_code == I40E_SUCCESS) {
136 hw->nvm.hw_semaphore_timeout =
137 I40E_MS_TO_GTIME(time_left) + gtime;
141 if (ret_code != I40E_SUCCESS) {
142 hw->nvm.hw_semaphore_timeout = 0;
143 i40e_debug(hw, I40E_DEBUG_NVM,
144 "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n",
145 time_left, ret_code, hw->aq.asq_last_status);
149 i40e_i40e_acquire_nvm_exit:
154 * i40e_release_nvm - Generic request for releasing the NVM ownership
155 * @hw: pointer to the HW structure
157 * This function will release NVM resource via the proper Admin Command.
159 void i40e_release_nvm(struct i40e_hw *hw)
161 enum i40e_status_code ret_code = I40E_SUCCESS;
164 DEBUGFUNC("i40e_release_nvm");
166 if (hw->nvm.blank_nvm_mode)
169 ret_code = i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
171 /* there are some rare cases when trying to release the resource
172 * results in an admin Q timeout, so handle them correctly
174 while ((ret_code == I40E_ERR_ADMIN_QUEUE_TIMEOUT) &&
175 (total_delay < hw->aq.asq_cmd_timeout)) {
177 ret_code = i40e_aq_release_resource(hw,
178 I40E_NVM_RESOURCE_ID, 0, NULL);
184 * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
185 * @hw: pointer to the HW structure
187 * Polls the SRCTL Shadow RAM register done bit.
189 static enum i40e_status_code i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
191 enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
194 DEBUGFUNC("i40e_poll_sr_srctl_done_bit");
196 /* Poll the I40E_GLNVM_SRCTL until the done bit is set */
197 for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
198 srctl = rd32(hw, I40E_GLNVM_SRCTL);
199 if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
200 ret_code = I40E_SUCCESS;
205 if (ret_code == I40E_ERR_TIMEOUT)
206 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set");
211 * i40e_read_nvm_word - Reads Shadow RAM
212 * @hw: pointer to the HW structure
213 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
214 * @data: word read from the Shadow RAM
216 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
218 enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
222 if (hw->mac.type == I40E_MAC_X722)
223 return i40e_read_nvm_word_aq(hw, offset, data);
225 return i40e_read_nvm_word_srctl(hw, offset, data);
229 * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
230 * @hw: pointer to the HW structure
231 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
232 * @data: word read from the Shadow RAM
234 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
236 enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
239 enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
242 DEBUGFUNC("i40e_read_nvm_word_srctl");
244 if (offset >= hw->nvm.sr_size) {
245 i40e_debug(hw, I40E_DEBUG_NVM,
246 "NVM read error: Offset %d beyond Shadow RAM limit %d\n",
247 offset, hw->nvm.sr_size);
248 ret_code = I40E_ERR_PARAM;
252 /* Poll the done bit first */
253 ret_code = i40e_poll_sr_srctl_done_bit(hw);
254 if (ret_code == I40E_SUCCESS) {
255 /* Write the address and start reading */
256 sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
257 BIT(I40E_GLNVM_SRCTL_START_SHIFT);
258 wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
260 /* Poll I40E_GLNVM_SRCTL until the done bit is set */
261 ret_code = i40e_poll_sr_srctl_done_bit(hw);
262 if (ret_code == I40E_SUCCESS) {
263 sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
264 *data = (u16)((sr_reg &
265 I40E_GLNVM_SRDATA_RDDATA_MASK)
266 >> I40E_GLNVM_SRDATA_RDDATA_SHIFT);
269 if (ret_code != I40E_SUCCESS)
270 i40e_debug(hw, I40E_DEBUG_NVM,
271 "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
279 * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ
280 * @hw: pointer to the HW structure
281 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
282 * @data: word read from the Shadow RAM
284 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
286 enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
289 enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
291 DEBUGFUNC("i40e_read_nvm_word_aq");
293 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, TRUE);
294 *data = LE16_TO_CPU(*(__le16 *)data);
300 * i40e_read_nvm_buffer - Reads Shadow RAM buffer
301 * @hw: pointer to the HW structure
302 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
303 * @words: (in) number of words to read; (out) number of words actually read
304 * @data: words read from the Shadow RAM
306 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
307 * method. The buffer read is preceded by the NVM ownership take
308 * and followed by the release.
310 enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
311 u16 *words, u16 *data)
314 if (hw->mac.type == I40E_MAC_X722)
315 return i40e_read_nvm_buffer_aq(hw, offset, words, data);
317 return i40e_read_nvm_buffer_srctl(hw, offset, words, data);
321 * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
322 * @hw: pointer to the HW structure
323 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
324 * @words: (in) number of words to read; (out) number of words actually read
325 * @data: words read from the Shadow RAM
327 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
328 * method. The buffer read is preceded by the NVM ownership take
329 * and followed by the release.
331 enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
332 u16 *words, u16 *data)
334 enum i40e_status_code ret_code = I40E_SUCCESS;
337 DEBUGFUNC("i40e_read_nvm_buffer_srctl");
339 /* Loop thru the selected region */
340 for (word = 0; word < *words; word++) {
341 index = offset + word;
342 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]);
343 if (ret_code != I40E_SUCCESS)
347 /* Update the number of words read from the Shadow RAM */
354 * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ
355 * @hw: pointer to the HW structure
356 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
357 * @words: (in) number of words to read; (out) number of words actually read
358 * @data: words read from the Shadow RAM
360 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()
361 * method. The buffer read is preceded by the NVM ownership take
362 * and followed by the release.
364 enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
365 u16 *words, u16 *data)
367 enum i40e_status_code ret_code;
368 u16 read_size = *words;
369 bool last_cmd = FALSE;
373 DEBUGFUNC("i40e_read_nvm_buffer_aq");
376 /* Calculate number of bytes we should read in this step.
377 * FVL AQ do not allow to read more than one page at a time or
378 * to cross page boundaries.
380 if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)
381 read_size = min(*words,
382 (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS -
383 (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)));
385 read_size = min((*words - words_read),
386 I40E_SR_SECTOR_SIZE_IN_WORDS);
388 /* Check if this is last command, if so set proper flag */
389 if ((words_read + read_size) >= *words)
392 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,
393 data + words_read, last_cmd);
394 if (ret_code != I40E_SUCCESS)
395 goto read_nvm_buffer_aq_exit;
397 /* Increment counter for words already read and move offset to
400 words_read += read_size;
402 } while (words_read < *words);
404 for (i = 0; i < *words; i++)
405 data[i] = LE16_TO_CPU(((__le16 *)data)[i]);
407 read_nvm_buffer_aq_exit:
413 * i40e_read_nvm_aq - Read Shadow RAM.
414 * @hw: pointer to the HW structure.
415 * @module_pointer: module pointer location in words from the NVM beginning
416 * @offset: offset in words from module start
417 * @words: number of words to write
418 * @data: buffer with words to write to the Shadow RAM
419 * @last_command: tells the AdminQ that this is the last command
421 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
423 enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
424 u32 offset, u16 words, void *data,
427 enum i40e_status_code ret_code = I40E_ERR_NVM;
428 struct i40e_asq_cmd_details cmd_details;
430 DEBUGFUNC("i40e_read_nvm_aq");
432 memset(&cmd_details, 0, sizeof(cmd_details));
433 cmd_details.wb_desc = &hw->nvm_wb_desc;
435 /* Here we are checking the SR limit only for the flat memory model.
436 * We cannot do it for the module-based model, as we did not acquire
437 * the NVM resource yet (we cannot get the module pointer value).
438 * Firmware will check the module-based model.
440 if ((offset + words) > hw->nvm.sr_size)
441 i40e_debug(hw, I40E_DEBUG_NVM,
442 "NVM write error: offset %d beyond Shadow RAM limit %d\n",
443 (offset + words), hw->nvm.sr_size);
444 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
445 /* We can write only up to 4KB (one sector), in one AQ write */
446 i40e_debug(hw, I40E_DEBUG_NVM,
447 "NVM write fail error: tried to write %d words, limit is %d.\n",
448 words, I40E_SR_SECTOR_SIZE_IN_WORDS);
449 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
450 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
451 /* A single write cannot spread over two sectors */
452 i40e_debug(hw, I40E_DEBUG_NVM,
453 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
456 ret_code = i40e_aq_read_nvm(hw, module_pointer,
457 2 * offset, /*bytes*/
459 data, last_command, &cmd_details);
465 * i40e_write_nvm_aq - Writes Shadow RAM.
466 * @hw: pointer to the HW structure.
467 * @module_pointer: module pointer location in words from the NVM beginning
468 * @offset: offset in words from module start
469 * @words: number of words to write
470 * @data: buffer with words to write to the Shadow RAM
471 * @last_command: tells the AdminQ that this is the last command
473 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
475 enum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
476 u32 offset, u16 words, void *data,
479 enum i40e_status_code ret_code = I40E_ERR_NVM;
480 struct i40e_asq_cmd_details cmd_details;
482 DEBUGFUNC("i40e_write_nvm_aq");
484 memset(&cmd_details, 0, sizeof(cmd_details));
485 cmd_details.wb_desc = &hw->nvm_wb_desc;
487 /* Here we are checking the SR limit only for the flat memory model.
488 * We cannot do it for the module-based model, as we did not acquire
489 * the NVM resource yet (we cannot get the module pointer value).
490 * Firmware will check the module-based model.
492 if ((offset + words) > hw->nvm.sr_size)
493 DEBUGOUT("NVM write error: offset beyond Shadow RAM limit.\n");
494 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
495 /* We can write only up to 4KB (one sector), in one AQ write */
496 DEBUGOUT("NVM write fail error: cannot write more than 4KB in a single write.\n");
497 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
498 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
499 /* A single write cannot spread over two sectors */
500 DEBUGOUT("NVM write error: cannot spread over two sectors in a single write.\n");
502 ret_code = i40e_aq_update_nvm(hw, module_pointer,
503 2 * offset, /*bytes*/
505 data, last_command, &cmd_details);
511 * i40e_write_nvm_word - Writes Shadow RAM word
512 * @hw: pointer to the HW structure
513 * @offset: offset of the Shadow RAM word to write
514 * @data: word to write to the Shadow RAM
516 * Writes a 16 bit word to the SR using the i40e_write_nvm_aq() method.
517 * NVM ownership have to be acquired and released (on ARQ completion event
518 * reception) by caller. To commit SR to NVM update checksum function
521 enum i40e_status_code i40e_write_nvm_word(struct i40e_hw *hw, u32 offset,
524 DEBUGFUNC("i40e_write_nvm_word");
526 *((__le16 *)data) = CPU_TO_LE16(*((u16 *)data));
528 /* Value 0x00 below means that we treat SR as a flat mem */
529 return i40e_write_nvm_aq(hw, 0x00, offset, 1, data, FALSE);
533 * i40e_write_nvm_buffer - Writes Shadow RAM buffer
534 * @hw: pointer to the HW structure
535 * @module_pointer: module pointer location in words from the NVM beginning
536 * @offset: offset of the Shadow RAM buffer to write
537 * @words: number of words to write
538 * @data: words to write to the Shadow RAM
540 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
541 * NVM ownership must be acquired before calling this function and released
542 * on ARQ completion event reception by caller. To commit SR to NVM update
543 * checksum function should be called.
545 enum i40e_status_code i40e_write_nvm_buffer(struct i40e_hw *hw,
546 u8 module_pointer, u32 offset,
547 u16 words, void *data)
549 __le16 *le_word_ptr = (__le16 *)data;
550 u16 *word_ptr = (u16 *)data;
553 DEBUGFUNC("i40e_write_nvm_buffer");
555 for (i = 0; i < words; i++)
556 le_word_ptr[i] = CPU_TO_LE16(word_ptr[i]);
558 /* Here we will only write one buffer as the size of the modules
559 * mirrored in the Shadow RAM is always less than 4K.
561 return i40e_write_nvm_aq(hw, module_pointer, offset, words,
566 * i40e_calc_nvm_checksum - Calculates and returns the checksum
567 * @hw: pointer to hardware structure
568 * @checksum: pointer to the checksum
570 * This function calculates SW Checksum that covers the whole 64kB shadow RAM
571 * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
572 * is customer specific and unknown. Therefore, this function skips all maximum
573 * possible size of VPD (1kB).
575 enum i40e_status_code i40e_calc_nvm_checksum(struct i40e_hw *hw, u16 *checksum)
577 enum i40e_status_code ret_code = I40E_SUCCESS;
578 struct i40e_virt_mem vmem;
579 u16 pcie_alt_module = 0;
580 u16 checksum_local = 0;
585 DEBUGFUNC("i40e_calc_nvm_checksum");
587 ret_code = i40e_allocate_virt_mem(hw, &vmem,
588 I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16));
590 goto i40e_calc_nvm_checksum_exit;
591 data = (u16 *)vmem.va;
593 /* read pointer to VPD area */
594 ret_code = i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);
595 if (ret_code != I40E_SUCCESS) {
596 ret_code = I40E_ERR_NVM_CHECKSUM;
597 goto i40e_calc_nvm_checksum_exit;
600 /* read pointer to PCIe Alt Auto-load module */
601 ret_code = i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
603 if (ret_code != I40E_SUCCESS) {
604 ret_code = I40E_ERR_NVM_CHECKSUM;
605 goto i40e_calc_nvm_checksum_exit;
608 /* Calculate SW checksum that covers the whole 64kB shadow RAM
609 * except the VPD and PCIe ALT Auto-load modules
611 for (i = 0; i < hw->nvm.sr_size; i++) {
613 if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {
614 u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS;
616 ret_code = i40e_read_nvm_buffer(hw, i, &words, data);
617 if (ret_code != I40E_SUCCESS) {
618 ret_code = I40E_ERR_NVM_CHECKSUM;
619 goto i40e_calc_nvm_checksum_exit;
623 /* Skip Checksum word */
624 if (i == I40E_SR_SW_CHECKSUM_WORD)
626 /* Skip VPD module (convert byte size to word count) */
627 if ((i >= (u32)vpd_module) &&
628 (i < ((u32)vpd_module +
629 (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) {
632 /* Skip PCIe ALT module (convert byte size to word count) */
633 if ((i >= (u32)pcie_alt_module) &&
634 (i < ((u32)pcie_alt_module +
635 (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) {
639 checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS];
642 *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;
644 i40e_calc_nvm_checksum_exit:
645 i40e_free_virt_mem(hw, &vmem);
650 * i40e_update_nvm_checksum - Updates the NVM checksum
651 * @hw: pointer to hardware structure
653 * NVM ownership must be acquired before calling this function and released
654 * on ARQ completion event reception by caller.
655 * This function will commit SR to NVM.
657 enum i40e_status_code i40e_update_nvm_checksum(struct i40e_hw *hw)
659 enum i40e_status_code ret_code = I40E_SUCCESS;
663 DEBUGFUNC("i40e_update_nvm_checksum");
665 ret_code = i40e_calc_nvm_checksum(hw, &checksum);
666 le_sum = CPU_TO_LE16(checksum);
667 if (ret_code == I40E_SUCCESS)
668 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
675 * i40e_validate_nvm_checksum - Validate EEPROM checksum
676 * @hw: pointer to hardware structure
677 * @checksum: calculated checksum
679 * Performs checksum calculation and validates the NVM SW checksum. If the
680 * caller does not need checksum, the value can be NULL.
682 enum i40e_status_code i40e_validate_nvm_checksum(struct i40e_hw *hw,
685 enum i40e_status_code ret_code = I40E_SUCCESS;
687 u16 checksum_local = 0;
689 DEBUGFUNC("i40e_validate_nvm_checksum");
691 ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
692 if (ret_code != I40E_SUCCESS)
693 goto i40e_validate_nvm_checksum_exit;
695 /* Do not use i40e_read_nvm_word() because we do not want to take
696 * the synchronization semaphores twice here.
698 i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
700 /* Verify read checksum from EEPROM is the same as
701 * calculated checksum
703 if (checksum_local != checksum_sr)
704 ret_code = I40E_ERR_NVM_CHECKSUM;
706 /* If the user cares, return the calculated checksum */
708 *checksum = checksum_local;
710 i40e_validate_nvm_checksum_exit: