sys/dev/ixl/i40e_type.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2013-2018, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
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  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _I40E_TYPE_H_
  36 #define _I40E_TYPE_H_
  37
  38 #include "i40e_status.h"
  39 #include "i40e_osdep.h"
  40 #include "i40e_register.h"
  41 #include "i40e_adminq.h"
  42 #include "i40e_hmc.h"
  43 #include "i40e_lan_hmc.h"
  44 #include "i40e_devids.h"
  45
  46
  47 #define BIT(a) (1UL << (a))
  48 #define BIT_ULL(a) (1ULL << (a))
  49
  50 #ifndef I40E_MASK
  51 /* I40E_MASK is a macro used on 32 bit registers */
  52 #define I40E_MASK(mask, shift) (mask << shift)
  53 #endif
  54
  55 #define I40E_MAX_PF                     16
  56 #define I40E_MAX_PF_VSI                 64
  57 #define I40E_MAX_PF_QP                  128
  58 #define I40E_MAX_VSI_QP                 16
  59 #define I40E_MAX_VF_VSI                 3
  60 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  61 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  62
  63 /* something less than 1 minute */
  64 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  65
  66 /* Max default timeout in ms, */
  67 #define I40E_MAX_NVM_TIMEOUT            18000
  68
  69 /* Max timeout in ms for the phy to respond */
  70 #define I40E_MAX_PHY_TIMEOUT            500
  71
  72 /* Check whether address is multicast. */
  73 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  74
  75 /* Check whether an address is broadcast. */
  76 #define I40E_IS_BROADCAST(address)      \
  77         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  78         (((u8 *)(address))[1] == ((u8)0xff)))
  79
  80 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  81 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  82
  83 /* forward declaration */
  84 struct i40e_hw;
  85 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  86
  87 #define ETH_ALEN        6
  88 /* Data type manipulation macros. */
  89 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  90 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  91
  92 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
  93 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
  94
  95 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
  96 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
  97
  98 /* Number of Transmit Descriptors must be a multiple of 8. */
  99 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 100 /* Number of Receive Descriptors must be a multiple of 32 if
 101  * the number of descriptors is greater than 32.
 102  */
 103 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 104
 105 #define I40E_DESC_UNUSED(R)     \
 106         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 107         (R)->next_to_clean - (R)->next_to_use - 1)
 108
 109 /* bitfields for Tx queue mapping in QTX_CTL */
 110 #define I40E_QTX_CTL_VF_QUEUE   0x0
 111 #define I40E_QTX_CTL_VM_QUEUE   0x1
 112 #define I40E_QTX_CTL_PF_QUEUE   0x2
 113
 114 /* debug masks - set these bits in hw->debug_mask to control output */
 115 enum i40e_debug_mask {
 116         I40E_DEBUG_INIT                 = 0x00000001,
 117         I40E_DEBUG_RELEASE              = 0x00000002,
 118
 119         I40E_DEBUG_LINK                 = 0x00000010,
 120         I40E_DEBUG_PHY                  = 0x00000020,
 121         I40E_DEBUG_HMC                  = 0x00000040,
 122         I40E_DEBUG_NVM                  = 0x00000080,
 123         I40E_DEBUG_LAN                  = 0x00000100,
 124         I40E_DEBUG_FLOW                 = 0x00000200,
 125         I40E_DEBUG_DCB                  = 0x00000400,
 126         I40E_DEBUG_DIAG                 = 0x00000800,
 127         I40E_DEBUG_FD                   = 0x00001000,
 128
 129         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 130         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 131         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 132         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 133         I40E_DEBUG_AQ                   = 0x0F000000,
 134
 135         I40E_DEBUG_USER                 = 0xF0000000,
 136
 137         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 138 };
 139
 140 /* PCI Bus Info */
 141 #define I40E_PCI_LINK_STATUS            0xB2
 142 #define I40E_PCI_LINK_WIDTH             0x3F0
 143 #define I40E_PCI_LINK_WIDTH_1           0x10
 144 #define I40E_PCI_LINK_WIDTH_2           0x20
 145 #define I40E_PCI_LINK_WIDTH_4           0x40
 146 #define I40E_PCI_LINK_WIDTH_8           0x80
 147 #define I40E_PCI_LINK_SPEED             0xF
 148 #define I40E_PCI_LINK_SPEED_2500        0x1
 149 #define I40E_PCI_LINK_SPEED_5000        0x2
 150 #define I40E_PCI_LINK_SPEED_8000        0x3
 151
 152 #define I40E_MDIO_CLAUSE22_STCODE_MASK  I40E_MASK(1, \
 153                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 154 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_MASK(1, \
 155                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 156 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_MASK(2, \
 157                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 158
 159 #define I40E_MDIO_CLAUSE45_STCODE_MASK  I40E_MASK(0, \
 160                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 161 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_MASK(0, \
 162                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 163 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_MASK(1, \
 164                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 165 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    I40E_MASK(2, \
 166                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 167 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_MASK(3, \
 168                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 169
 170 #define I40E_PHY_COM_REG_PAGE                   0x1E
 171 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 172 #define I40E_PHY_LED_MANUAL_ON                  0x100
 173 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 174 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 175 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 176
 177 /* Memory types */
 178 enum i40e_memset_type {
 179         I40E_NONDMA_MEM = 0,
 180         I40E_DMA_MEM
 181 };
 182
 183 /* Memcpy types */
 184 enum i40e_memcpy_type {
 185         I40E_NONDMA_TO_NONDMA = 0,
 186         I40E_NONDMA_TO_DMA,
 187         I40E_DMA_TO_DMA,
 188         I40E_DMA_TO_NONDMA
 189 };
 190
 191
 192 /* These are structs for managing the hardware information and the operations.
 193  * The structures of function pointers are filled out at init time when we
 194  * know for sure exactly which hardware we're working with.  This gives us the
 195  * flexibility of using the same main driver code but adapting to slightly
 196  * different hardware needs as new parts are developed.  For this architecture,
 197  * the Firmware and AdminQ are intended to insulate the driver from most of the
 198  * future changes, but these structures will also do part of the job.
 199  */
 200 enum i40e_mac_type {
 201         I40E_MAC_UNKNOWN = 0,
 202         I40E_MAC_XL710,
 203         I40E_MAC_VF,
 204         I40E_MAC_X722,
 205         I40E_MAC_X722_VF,
 206         I40E_MAC_GENERIC,
 207 };
 208
 209 enum i40e_media_type {
 210         I40E_MEDIA_TYPE_UNKNOWN = 0,
 211         I40E_MEDIA_TYPE_FIBER,
 212         I40E_MEDIA_TYPE_BASET,
 213         I40E_MEDIA_TYPE_BACKPLANE,
 214         I40E_MEDIA_TYPE_CX4,
 215         I40E_MEDIA_TYPE_DA,
 216         I40E_MEDIA_TYPE_VIRTUAL
 217 };
 218
 219 enum i40e_fc_mode {
 220         I40E_FC_NONE = 0,
 221         I40E_FC_RX_PAUSE,
 222         I40E_FC_TX_PAUSE,
 223         I40E_FC_FULL,
 224         I40E_FC_PFC,
 225         I40E_FC_DEFAULT
 226 };
 227
 228 enum i40e_set_fc_aq_failures {
 229         I40E_SET_FC_AQ_FAIL_NONE = 0,
 230         I40E_SET_FC_AQ_FAIL_GET = 1,
 231         I40E_SET_FC_AQ_FAIL_SET = 2,
 232         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 233         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 234 };
 235
 236 enum i40e_vsi_type {
 237         I40E_VSI_MAIN   = 0,
 238         I40E_VSI_VMDQ1  = 1,
 239         I40E_VSI_VMDQ2  = 2,
 240         I40E_VSI_CTRL   = 3,
 241         I40E_VSI_FCOE   = 4,
 242         I40E_VSI_MIRROR = 5,
 243         I40E_VSI_SRIOV  = 6,
 244         I40E_VSI_FDIR   = 7,
 245         I40E_VSI_TYPE_UNKNOWN
 246 };
 247
 248 enum i40e_queue_type {
 249         I40E_QUEUE_TYPE_RX = 0,
 250         I40E_QUEUE_TYPE_TX,
 251         I40E_QUEUE_TYPE_PE_CEQ,
 252         I40E_QUEUE_TYPE_UNKNOWN
 253 };
 254
 255 struct i40e_link_status {
 256         enum i40e_aq_phy_type phy_type;
 257         enum i40e_aq_link_speed link_speed;
 258         u8 link_info;
 259         u8 an_info;
 260         u8 req_fec_info;
 261         u8 fec_info;
 262         u8 ext_info;
 263         u8 loopback;
 264         /* is Link Status Event notification to SW enabled */
 265         bool lse_enable;
 266         u16 max_frame_size;
 267         bool crc_enable;
 268         u8 pacing;
 269         u8 requested_speeds;
 270         u8 module_type[3];
 271         /* 1st byte: module identifier */
 272 #define I40E_MODULE_TYPE_SFP            0x03
 273 #define I40E_MODULE_TYPE_QSFP           0x0D
 274         /* 2nd byte: ethernet compliance codes for 10/40G */
 275 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 276 #define I40E_MODULE_TYPE_40G_LR4        0x02
 277 #define I40E_MODULE_TYPE_40G_SR4        0x04
 278 #define I40E_MODULE_TYPE_40G_CR4        0x08
 279 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 280 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 281 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 282 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 283         /* 3rd byte: ethernet compliance codes for 1G */
 284 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 285 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 286 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 287 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 288 };
 289
 290 struct i40e_phy_info {
 291         struct i40e_link_status link_info;
 292         struct i40e_link_status link_info_old;
 293         bool get_link_info;
 294         enum i40e_media_type media_type;
 295         /* all the phy types the NVM is capable of */
 296         u64 phy_types;
 297 };
 298
 299 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 300 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 301 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 302 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 303 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 304 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 305 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 306 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 307 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 308 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 309 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 310 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 311 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 312 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 313 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 314 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 315 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 316 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 317 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 318 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 319 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 320 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 321 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 322 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 323 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 324 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 325 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 326                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 327 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 328 /*
 329  * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
 330  * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
 331  * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
 332  * a shift is needed to adjust for this with values larger than 31. The
 333  * only affected values are I40E_PHY_TYPE_25GBASE_*.
 334  */
 335 #define I40E_PHY_TYPE_OFFSET 1
 336 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
 337                                              I40E_PHY_TYPE_OFFSET)
 338 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
 339                                              I40E_PHY_TYPE_OFFSET)
 340 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
 341                                              I40E_PHY_TYPE_OFFSET)
 342 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
 343                                              I40E_PHY_TYPE_OFFSET)
 344 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
 345                                              I40E_PHY_TYPE_OFFSET)
 346 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
 347                                              I40E_PHY_TYPE_OFFSET)
 348 #define I40E_HW_CAP_MAX_GPIO                    30
 349 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 350 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 351
 352 enum i40e_acpi_programming_method {
 353         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 354         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 355 };
 356
 357 #define I40E_WOL_SUPPORT_MASK                   0x1
 358 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       0x2
 359 #define I40E_PROXY_SUPPORT_MASK                 0x4
 360
 361 /* Capabilities of a PF or a VF or the whole device */
 362 struct i40e_hw_capabilities {
 363         u32  switch_mode;
 364 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 365 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 366 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 367
 368         /* Cloud filter modes:
 369          * Mode1: Filter on L4 port only
 370          * Mode2: Filter for non-tunneled traffic
 371          * Mode3: Filter for tunnel traffic
 372          */
 373 #define I40E_CLOUD_FILTER_MODE1 0x6
 374 #define I40E_CLOUD_FILTER_MODE2 0x7
 375 #define I40E_CLOUD_FILTER_MODE3 0x8
 376
 377         u32  management_mode;
 378         u32  mng_protocols_over_mctp;
 379 #define I40E_MNG_PROTOCOL_PLDM          0x2
 380 #define I40E_MNG_PROTOCOL_OEM_COMMANDS  0x4
 381 #define I40E_MNG_PROTOCOL_NCSI          0x8
 382         u32  npar_enable;
 383         u32  os2bmc;
 384         u32  valid_functions;
 385         bool sr_iov_1_1;
 386         bool vmdq;
 387         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 388         bool evb_802_1_qbh; /* Bridge Port Extension */
 389         bool dcb;
 390         bool fcoe;
 391         bool iscsi; /* Indicates iSCSI enabled */
 392         bool flex10_enable;
 393         bool flex10_capable;
 394         u32  flex10_mode;
 395 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 396 #define I40E_FLEX10_MODE_DCC            0x1
 397 #define I40E_FLEX10_MODE_DCI            0x2
 398
 399         u32 flex10_status;
 400 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 401 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 402
 403         bool sec_rev_disabled;
 404         bool update_disabled;
 405 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 406 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 407
 408         bool mgmt_cem;
 409         bool ieee_1588;
 410         bool iwarp;
 411         bool fd;
 412         u32 fd_filters_guaranteed;
 413         u32 fd_filters_best_effort;
 414         bool rss;
 415         u32 rss_table_size;
 416         u32 rss_table_entry_width;
 417         bool led[I40E_HW_CAP_MAX_GPIO];
 418         bool sdp[I40E_HW_CAP_MAX_GPIO];
 419         u32 nvm_image_type;
 420         u32 num_flow_director_filters;
 421         u32 num_vfs;
 422         u32 vf_base_id;
 423         u32 num_vsis;
 424         u32 num_rx_qp;
 425         u32 num_tx_qp;
 426         u32 base_queue;
 427         u32 num_msix_vectors;
 428         u32 num_msix_vectors_vf;
 429         u32 led_pin_num;
 430         u32 sdp_pin_num;
 431         u32 mdio_port_num;
 432         u32 mdio_port_mode;
 433         u8 rx_buf_chain_len;
 434         u32 enabled_tcmap;
 435         u32 maxtc;
 436         u64 wr_csr_prot;
 437         bool apm_wol_support;
 438         enum i40e_acpi_programming_method acpi_prog_method;
 439         bool proxy_support;
 440 };
 441
 442 struct i40e_mac_info {
 443         enum i40e_mac_type type;
 444         u8 addr[ETH_ALEN];
 445         u8 perm_addr[ETH_ALEN];
 446         u8 san_addr[ETH_ALEN];
 447         u8 port_addr[ETH_ALEN];
 448         u16 max_fcoeq;
 449 };
 450
 451 enum i40e_aq_resources_ids {
 452         I40E_NVM_RESOURCE_ID = 1
 453 };
 454
 455 enum i40e_aq_resource_access_type {
 456         I40E_RESOURCE_READ = 1,
 457         I40E_RESOURCE_WRITE
 458 };
 459
 460 struct i40e_nvm_info {
 461         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 462         u32 timeout;              /* [ms] */
 463         u16 sr_size;              /* Shadow RAM size in words */
 464         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 465         u16 version;              /* NVM package version */
 466         u32 eetrack;              /* NVM data version */
 467         u32 oem_ver;              /* OEM version info */
 468 };
 469
 470 /* definitions used in NVM update support */
 471
 472 enum i40e_nvmupd_cmd {
 473         I40E_NVMUPD_INVALID,
 474         I40E_NVMUPD_READ_CON,
 475         I40E_NVMUPD_READ_SNT,
 476         I40E_NVMUPD_READ_LCB,
 477         I40E_NVMUPD_READ_SA,
 478         I40E_NVMUPD_WRITE_ERA,
 479         I40E_NVMUPD_WRITE_CON,
 480         I40E_NVMUPD_WRITE_SNT,
 481         I40E_NVMUPD_WRITE_LCB,
 482         I40E_NVMUPD_WRITE_SA,
 483         I40E_NVMUPD_CSUM_CON,
 484         I40E_NVMUPD_CSUM_SA,
 485         I40E_NVMUPD_CSUM_LCB,
 486         I40E_NVMUPD_STATUS,
 487         I40E_NVMUPD_EXEC_AQ,
 488         I40E_NVMUPD_GET_AQ_RESULT,
 489         I40E_NVMUPD_GET_AQ_EVENT,
 490 };
 491
 492 enum i40e_nvmupd_state {
 493         I40E_NVMUPD_STATE_INIT,
 494         I40E_NVMUPD_STATE_READING,
 495         I40E_NVMUPD_STATE_WRITING,
 496         I40E_NVMUPD_STATE_INIT_WAIT,
 497         I40E_NVMUPD_STATE_WRITE_WAIT,
 498         I40E_NVMUPD_STATE_ERROR
 499 };
 500
 501 /* nvm_access definition and its masks/shifts need to be accessible to
 502  * application, core driver, and shared code.  Where is the right file?
 503  */
 504 #define I40E_NVM_READ   0xB
 505 #define I40E_NVM_WRITE  0xC
 506
 507 #define I40E_NVM_MOD_PNT_MASK 0xFF
 508
 509 #define I40E_NVM_TRANS_SHIFT                    8
 510 #define I40E_NVM_TRANS_MASK                     (0xf << I40E_NVM_TRANS_SHIFT)
 511 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT       12
 512 #define I40E_NVM_PRESERVATION_FLAGS_MASK \
 513                                 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
 514 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED    0x01
 515 #define I40E_NVM_PRESERVATION_FLAGS_ALL         0x02
 516 #define I40E_NVM_CON                            0x0
 517 #define I40E_NVM_SNT                            0x1
 518 #define I40E_NVM_LCB                            0x2
 519 #define I40E_NVM_SA                             (I40E_NVM_SNT | I40E_NVM_LCB)
 520 #define I40E_NVM_ERA                            0x4
 521 #define I40E_NVM_CSUM                           0x8
 522 #define I40E_NVM_AQE                            0xe
 523 #define I40E_NVM_EXEC                           0xf
 524
 525 #define I40E_NVM_ADAPT_SHIFT    16
 526 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 527
 528 #define I40E_NVMUPD_MAX_DATA    4096
 529 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 530
 531 struct i40e_nvm_access {
 532         u32 command;
 533         u32 config;
 534         u32 offset;     /* in bytes */
 535         u32 data_size;  /* in bytes */
 536         u8 data[1];
 537 };
 538
 539 /* (Q)SFP module access definitions */
 540 #define I40E_I2C_EEPROM_DEV_ADDR        0xA0
 541 #define I40E_I2C_EEPROM_DEV_ADDR2       0xA2
 542 #define I40E_MODULE_TYPE_ADDR           0x00
 543 #define I40E_MODULE_REVISION_ADDR       0x01
 544 #define I40E_MODULE_SFF_8472_COMP       0x5E
 545 #define I40E_MODULE_SFF_8472_SWAP       0x5C
 546 #define I40E_MODULE_SFF_ADDR_MODE       0x04
 547 #define I40E_MODULE_SFF_DIAG_CAPAB      0x40
 548 #define I40E_MODULE_TYPE_QSFP_PLUS      0x0D
 549 #define I40E_MODULE_TYPE_QSFP28         0x11
 550 #define I40E_MODULE_QSFP_MAX_LEN        640
 551
 552 /* PCI bus types */
 553 enum i40e_bus_type {
 554         i40e_bus_type_unknown = 0,
 555         i40e_bus_type_pci,
 556         i40e_bus_type_pcix,
 557         i40e_bus_type_pci_express,
 558         i40e_bus_type_reserved
 559 };
 560
 561 /* PCI bus speeds */
 562 enum i40e_bus_speed {
 563         i40e_bus_speed_unknown  = 0,
 564         i40e_bus_speed_33       = 33,
 565         i40e_bus_speed_66       = 66,
 566         i40e_bus_speed_100      = 100,
 567         i40e_bus_speed_120      = 120,
 568         i40e_bus_speed_133      = 133,
 569         i40e_bus_speed_2500     = 2500,
 570         i40e_bus_speed_5000     = 5000,
 571         i40e_bus_speed_8000     = 8000,
 572         i40e_bus_speed_reserved
 573 };
 574
 575 /* PCI bus widths */
 576 enum i40e_bus_width {
 577         i40e_bus_width_unknown  = 0,
 578         i40e_bus_width_pcie_x1  = 1,
 579         i40e_bus_width_pcie_x2  = 2,
 580         i40e_bus_width_pcie_x4  = 4,
 581         i40e_bus_width_pcie_x8  = 8,
 582         i40e_bus_width_32       = 32,
 583         i40e_bus_width_64       = 64,
 584         i40e_bus_width_reserved
 585 };
 586
 587 /* Bus parameters */
 588 struct i40e_bus_info {
 589         enum i40e_bus_speed speed;
 590         enum i40e_bus_width width;
 591         enum i40e_bus_type type;
 592
 593         u16 func;
 594         u16 device;
 595         u16 lan_id;
 596         u16 bus_id;
 597 };
 598
 599 /* Flow control (FC) parameters */
 600 struct i40e_fc_info {
 601         enum i40e_fc_mode current_mode; /* FC mode in effect */
 602         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 603 };
 604
 605 #define I40E_MAX_TRAFFIC_CLASS          8
 606 #define I40E_MAX_USER_PRIORITY          8
 607 #define I40E_DCBX_MAX_APPS              32
 608 #define I40E_LLDPDU_SIZE                1500
 609 #define I40E_TLV_STATUS_OPER            0x1
 610 #define I40E_TLV_STATUS_SYNC            0x2
 611 #define I40E_TLV_STATUS_ERR             0x4
 612 #define I40E_CEE_OPER_MAX_APPS          3
 613 #define I40E_APP_PROTOID_FCOE           0x8906
 614 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 615 #define I40E_APP_PROTOID_FIP            0x8914
 616 #define I40E_APP_SEL_ETHTYPE            0x1
 617 #define I40E_APP_SEL_TCPIP              0x2
 618 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 619 #define I40E_CEE_APP_SEL_TCPIP          0x1
 620
 621 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 622 struct i40e_dcb_ets_config {
 623         u8 willing;
 624         u8 cbs;
 625         u8 maxtcs;
 626         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 627         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 628         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 629 };
 630
 631 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 632 struct i40e_dcb_pfc_config {
 633         u8 willing;
 634         u8 mbc;
 635         u8 pfccap;
 636         u8 pfcenable;
 637 };
 638
 639 /* CEE or IEEE 802.1Qaz Application Priority data */
 640 struct i40e_dcb_app_priority_table {
 641         u8  priority;
 642         u8  selector;
 643         u16 protocolid;
 644 };
 645
 646 struct i40e_dcbx_config {
 647         u8  dcbx_mode;
 648 #define I40E_DCBX_MODE_CEE      0x1
 649 #define I40E_DCBX_MODE_IEEE     0x2
 650         u8  app_mode;
 651 #define I40E_DCBX_APPS_NON_WILLING      0x1
 652         u32 numapps;
 653         u32 tlv_status; /* CEE mode TLV status */
 654         struct i40e_dcb_ets_config etscfg;
 655         struct i40e_dcb_ets_config etsrec;
 656         struct i40e_dcb_pfc_config pfc;
 657         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 658 };
 659
 660 /* Port hardware description */
 661 struct i40e_hw {
 662         u8 *hw_addr;
 663         void *back;
 664
 665         /* subsystem structs */
 666         struct i40e_phy_info phy;
 667         struct i40e_mac_info mac;
 668         struct i40e_bus_info bus;
 669         struct i40e_nvm_info nvm;
 670         struct i40e_fc_info fc;
 671
 672         /* pci info */
 673         u16 device_id;
 674         u16 vendor_id;
 675         u16 subsystem_device_id;
 676         u16 subsystem_vendor_id;
 677         u8 revision_id;
 678         u8 port;
 679         bool adapter_stopped;
 680
 681         /* capabilities for entire device and PCI func */
 682         struct i40e_hw_capabilities dev_caps;
 683         struct i40e_hw_capabilities func_caps;
 684
 685         /* Flow Director shared filter space */
 686         u16 fdir_shared_filter_count;
 687
 688         /* device profile info */
 689         u8  pf_id;
 690         u16 main_vsi_seid;
 691
 692         /* for multi-function MACs */
 693         u16 partition_id;
 694         u16 num_partitions;
 695         u16 num_ports;
 696
 697         /* Closest numa node to the device */
 698         u16 numa_node;
 699
 700         /* Admin Queue info */
 701         struct i40e_adminq_info aq;
 702
 703         /* state of nvm update process */
 704         enum i40e_nvmupd_state nvmupd_state;
 705         struct i40e_aq_desc nvm_wb_desc;
 706         struct i40e_aq_desc nvm_aq_event_desc;
 707         struct i40e_virt_mem nvm_buff;
 708         bool nvm_release_on_done;
 709         u16 nvm_wait_opcode;
 710
 711         /* HMC info */
 712         struct i40e_hmc_info hmc; /* HMC info struct */
 713
 714         /* LLDP/DCBX Status */
 715         u16 dcbx_status;
 716
 717         /* DCBX info */
 718         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 719         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 720         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 721
 722         /* WoL and proxy support */
 723         u16 num_wol_proxy_filters;
 724         u16 wol_proxy_vsi_seid;
 725
 726 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 727 #define I40E_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)
 728 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
 729 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
 730         u64 flags;
 731
 732         /* Used in set switch config AQ command */
 733         u16 switch_tag;
 734         u16 first_tag;
 735         u16 second_tag;
 736
 737         /* debug mask */
 738         u32 debug_mask;
 739         char err_str[16];
 740 };
 741
 742 static INLINE bool i40e_is_vf(struct i40e_hw *hw)
 743 {
 744         return (hw->mac.type == I40E_MAC_VF ||
 745                 hw->mac.type == I40E_MAC_X722_VF);
 746 }
 747
 748 struct i40e_driver_version {
 749         u8 major_version;
 750         u8 minor_version;
 751         u8 build_version;
 752         u8 subbuild_version;
 753         u8 driver_string[32];
 754 };
 755
 756 /* RX Descriptors */
 757 union i40e_16byte_rx_desc {
 758         struct {
 759                 __le64 pkt_addr; /* Packet buffer address */
 760                 __le64 hdr_addr; /* Header buffer address */
 761         } read;
 762         struct {
 763                 struct {
 764                         struct {
 765                                 union {
 766                                         __le16 mirroring_status;
 767                                         __le16 fcoe_ctx_id;
 768                                 } mirr_fcoe;
 769                                 __le16 l2tag1;
 770                         } lo_dword;
 771                         union {
 772                                 __le32 rss; /* RSS Hash */
 773                                 __le32 fd_id; /* Flow director filter id */
 774                                 __le32 fcoe_param; /* FCoE DDP Context id */
 775                         } hi_dword;
 776                 } qword0;
 777                 struct {
 778                         /* ext status/error/pktype/length */
 779                         __le64 status_error_len;
 780                 } qword1;
 781         } wb;  /* writeback */
 782 };
 783
 784 union i40e_32byte_rx_desc {
 785         struct {
 786                 __le64  pkt_addr; /* Packet buffer address */
 787                 __le64  hdr_addr; /* Header buffer address */
 788                         /* bit 0 of hdr_buffer_addr is DD bit */
 789                 __le64  rsvd1;
 790                 __le64  rsvd2;
 791         } read;
 792         struct {
 793                 struct {
 794                         struct {
 795                                 union {
 796                                         __le16 mirroring_status;
 797                                         __le16 fcoe_ctx_id;
 798                                 } mirr_fcoe;
 799                                 __le16 l2tag1;
 800                         } lo_dword;
 801                         union {
 802                                 __le32 rss; /* RSS Hash */
 803                                 __le32 fcoe_param; /* FCoE DDP Context id */
 804                                 /* Flow director filter id in case of
 805                                  * Programming status desc WB
 806                                  */
 807                                 __le32 fd_id;
 808                         } hi_dword;
 809                 } qword0;
 810                 struct {
 811                         /* status/error/pktype/length */
 812                         __le64 status_error_len;
 813                 } qword1;
 814                 struct {
 815                         __le16 ext_status; /* extended status */
 816                         __le16 rsvd;
 817                         __le16 l2tag2_1;
 818                         __le16 l2tag2_2;
 819                 } qword2;
 820                 struct {
 821                         union {
 822                                 __le32 flex_bytes_lo;
 823                                 __le32 pe_status;
 824                         } lo_dword;
 825                         union {
 826                                 __le32 flex_bytes_hi;
 827                                 __le32 fd_id;
 828                         } hi_dword;
 829                 } qword3;
 830         } wb;  /* writeback */
 831 };
 832
 833 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 834 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 835                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 836 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 837 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 838                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 839
 840 enum i40e_rx_desc_status_bits {
 841         /* Note: These are predefined bit offsets */
 842         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 843         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 844         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 845         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 846         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 847         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 848         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 849         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 850
 851         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 852         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 853         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 854         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 855         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 856         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 857         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 858         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 859 };
 860
 861 #define I40E_RXD_QW1_STATUS_SHIFT       0
 862 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 863                                          I40E_RXD_QW1_STATUS_SHIFT)
 864
 865 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 866 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 867                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 868
 869 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 870 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 871
 872 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 873 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 874                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 875
 876 enum i40e_rx_desc_fltstat_values {
 877         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 878         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 879         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 880         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 881 };
 882
 883 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 884 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 885 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 886 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 887
 888 #define I40E_RXD_QW1_ERROR_SHIFT        19
 889 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 890
 891 enum i40e_rx_desc_error_bits {
 892         /* Note: These are predefined bit offsets */
 893         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 894         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 895         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 896         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 897         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 898         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 899         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 900         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 901         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 902 };
 903
 904 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 905         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 906         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 907         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 908         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 909         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 910 };
 911
 912 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 913 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 914
 915 /* Packet type non-ip values */
 916 enum i40e_rx_l2_ptype {
 917         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 918         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 919         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 920         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 921         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 922         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 923         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 924         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 925         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 926         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 927         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 928         I40E_RX_PTYPE_L2_ARP                            = 11,
 929         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 930         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 931         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 932         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 933         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 934         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 935         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 936         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 937         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 938         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 939         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 940         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 941         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 942         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 943 };
 944
 945 struct i40e_rx_ptype_decoded {
 946         u32 ptype:8;
 947         u32 known:1;
 948         u32 outer_ip:1;
 949         u32 outer_ip_ver:1;
 950         u32 outer_frag:1;
 951         u32 tunnel_type:3;
 952         u32 tunnel_end_prot:2;
 953         u32 tunnel_end_frag:1;
 954         u32 inner_prot:4;
 955         u32 payload_layer:3;
 956 };
 957
 958 enum i40e_rx_ptype_outer_ip {
 959         I40E_RX_PTYPE_OUTER_L2  = 0,
 960         I40E_RX_PTYPE_OUTER_IP  = 1
 961 };
 962
 963 enum i40e_rx_ptype_outer_ip_ver {
 964         I40E_RX_PTYPE_OUTER_NONE        = 0,
 965         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 966         I40E_RX_PTYPE_OUTER_IPV6        = 1
 967 };
 968
 969 enum i40e_rx_ptype_outer_fragmented {
 970         I40E_RX_PTYPE_NOT_FRAG  = 0,
 971         I40E_RX_PTYPE_FRAG      = 1
 972 };
 973
 974 enum i40e_rx_ptype_tunnel_type {
 975         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 976         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 977         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 978         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 979         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 980 };
 981
 982 enum i40e_rx_ptype_tunnel_end_prot {
 983         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 984         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 985         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 986 };
 987
 988 enum i40e_rx_ptype_inner_prot {
 989         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 990         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 991         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 992         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 993         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 994         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 995 };
 996
 997 enum i40e_rx_ptype_payload_layer {
 998         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 999         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
1000         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
1001         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
1002 };
1003
1004 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
1005 #define I40E_RX_PTYPE_SHIFT             56
1006
1007 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
1008 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
1009                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
1010
1011 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
1012 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
1013                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
1014
1015 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
1016 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
1017
1018 #define I40E_RXD_QW1_NEXTP_SHIFT        38
1019 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
1020
1021 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
1022 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
1023                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
1024
1025 enum i40e_rx_desc_ext_status_bits {
1026         /* Note: These are predefined bit offsets */
1027         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
1028         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
1029         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
1030         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
1031         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
1032         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1033         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
1034 };
1035
1036 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
1037 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1038
1039 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
1040 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1041
1042 enum i40e_rx_desc_pe_status_bits {
1043         /* Note: These are predefined bit offsets */
1044         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1045         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1046         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1047         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1048         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1049         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1050         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1051         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1052         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1053 };
1054
1055 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1056 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1057
1058 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1059 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1060                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1061
1062 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1063 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1064                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1065
1066 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1067 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1068                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1069
1070 enum i40e_rx_prog_status_desc_status_bits {
1071         /* Note: These are predefined bit offsets */
1072         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1073         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1074 };
1075
1076 enum i40e_rx_prog_status_desc_prog_id_masks {
1077         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1078         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1079         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1080 };
1081
1082 enum i40e_rx_prog_status_desc_error_bits {
1083         /* Note: These are predefined bit offsets */
1084         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1085         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1086         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1087         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1088 };
1089
1090 #define I40E_TWO_BIT_MASK       0x3
1091 #define I40E_THREE_BIT_MASK     0x7
1092 #define I40E_FOUR_BIT_MASK      0xF
1093 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1094
1095 /* TX Descriptor */
1096 struct i40e_tx_desc {
1097         __le64 buffer_addr; /* Address of descriptor's data buf */
1098         __le64 cmd_type_offset_bsz;
1099 };
1100
1101 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1102 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1103
1104 enum i40e_tx_desc_dtype_value {
1105         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1106         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1107         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1108         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1109         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1110         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1111         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1112         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1113         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1114         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1115 };
1116
1117 #define I40E_TXD_QW1_CMD_SHIFT  4
1118 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1119
1120 enum i40e_tx_desc_cmd_bits {
1121         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1122         I40E_TX_DESC_CMD_RS                     = 0x0002,
1123         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1124         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1125         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1126         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1127         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1128         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1129         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1130         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1131         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1132         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1133         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1134         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1135         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1136         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1137         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1138         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1139 };
1140
1141 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1142 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1143                                          I40E_TXD_QW1_OFFSET_SHIFT)
1144
1145 enum i40e_tx_desc_length_fields {
1146         /* Note: These are predefined bit offsets */
1147         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1148         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1149         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1150 };
1151
1152 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1153 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1154 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1155 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1156
1157 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1158 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1159                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1160
1161 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1162 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1163
1164 /* Context descriptors */
1165 struct i40e_tx_context_desc {
1166         __le32 tunneling_params;
1167         __le16 l2tag2;
1168         __le16 rsvd;
1169         __le64 type_cmd_tso_mss;
1170 };
1171
1172 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1173 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1174
1175 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1176 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1177
1178 enum i40e_tx_ctx_desc_cmd_bits {
1179         I40E_TX_CTX_DESC_TSO            = 0x01,
1180         I40E_TX_CTX_DESC_TSYN           = 0x02,
1181         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1182         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1183         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1184         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1185         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1186         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1187         I40E_TX_CTX_DESC_SWPE           = 0x40
1188 };
1189
1190 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1191 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1192                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1193
1194 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1195 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1196                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1197
1198 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1199 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1200
1201 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1202 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1203                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1204
1205 enum i40e_tx_ctx_desc_eipt_offload {
1206         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1207         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1208         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1209         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1210 };
1211
1212 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1213 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1214                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1215
1216 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1217 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1218
1219 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1220 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1221
1222 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1223 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1224
1225 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1226
1227 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1228 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1229                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1230
1231 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1232 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1233                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1234
1235 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1236 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1237 struct i40e_nop_desc {
1238         __le64 rsvd;
1239         __le64 dtype_cmd;
1240 };
1241
1242 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1243 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1244
1245 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1246 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1247
1248 enum i40e_tx_nop_desc_cmd_bits {
1249         /* Note: These are predefined bit offsets */
1250         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1251         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1252         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1253 };
1254
1255 struct i40e_filter_program_desc {
1256         __le32 qindex_flex_ptype_vsi;
1257         __le32 rsvd;
1258         __le32 dtype_cmd_cntindex;
1259         __le32 fd_id;
1260 };
1261 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1262 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1263                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1264 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1265 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1266                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1267 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1268 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1269                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1270
1271 /* Packet Classifier Types for filters */
1272 enum i40e_filter_pctype {
1273         /* Note: Values 0-28 are reserved for future use.
1274          * Value 29, 30, 32 are not supported on XL710 and X710.
1275          */
1276         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1277         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1278         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1279         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1280         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1281         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1282         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1283         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1284         /* Note: Values 37-38 are reserved for future use.
1285          * Value 39, 40, 42 are not supported on XL710 and X710.
1286          */
1287         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1288         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1289         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1290         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1291         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1292         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1293         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1294         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1295         /* Note: Value 47 is reserved for future use */
1296         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1297         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1298         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1299         /* Note: Values 51-62 are reserved for future use */
1300         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1301 };
1302
1303 enum i40e_filter_program_desc_dest {
1304         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1305         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1306         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1307 };
1308
1309 enum i40e_filter_program_desc_fd_status {
1310         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1311         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1312         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1313         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1314 };
1315
1316 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1317 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1318                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1319
1320 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1321 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1322
1323 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1324 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1325                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1326
1327 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1328 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1329
1330 enum i40e_filter_program_desc_pcmd {
1331         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1332         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1333 };
1334
1335 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1336 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1337
1338 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1339 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1340
1341 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1342                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1343 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1344                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1345
1346 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1347                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1348 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1349
1350 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1351 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1352                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1353
1354 enum i40e_filter_type {
1355         I40E_FLOW_DIRECTOR_FLTR = 0,
1356         I40E_PE_QUAD_HASH_FLTR = 1,
1357         I40E_ETHERTYPE_FLTR,
1358         I40E_FCOE_CTX_FLTR,
1359         I40E_MAC_VLAN_FLTR,
1360         I40E_HASH_FLTR
1361 };
1362
1363 struct i40e_vsi_context {
1364         u16 seid;
1365         u16 uplink_seid;
1366         u16 vsi_number;
1367         u16 vsis_allocated;
1368         u16 vsis_unallocated;
1369         u16 flags;
1370         u8 pf_num;
1371         u8 vf_num;
1372         u8 connection_type;
1373         struct i40e_aqc_vsi_properties_data info;
1374 };
1375
1376 struct i40e_veb_context {
1377         u16 seid;
1378         u16 uplink_seid;
1379         u16 veb_number;
1380         u16 vebs_allocated;
1381         u16 vebs_unallocated;
1382         u16 flags;
1383         struct i40e_aqc_get_veb_parameters_completion info;
1384 };
1385
1386 /* Statistics collected by each port, VSI, VEB, and S-channel */
1387 struct i40e_eth_stats {
1388         u64 rx_bytes;                   /* gorc */
1389         u64 rx_unicast;                 /* uprc */
1390         u64 rx_multicast;               /* mprc */
1391         u64 rx_broadcast;               /* bprc */
1392         u64 rx_discards;                /* rdpc */
1393         u64 rx_unknown_protocol;        /* rupp */
1394         u64 tx_bytes;                   /* gotc */
1395         u64 tx_unicast;                 /* uptc */
1396         u64 tx_multicast;               /* mptc */
1397         u64 tx_broadcast;               /* bptc */
1398         u64 tx_discards;                /* tdpc */
1399         u64 tx_errors;                  /* tepc */
1400 };
1401
1402 /* Statistics collected per VEB per TC */
1403 struct i40e_veb_tc_stats {
1404         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1405         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1406         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1407         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1408 };
1409
1410 /* Statistics collected by the MAC */
1411 struct i40e_hw_port_stats {
1412         /* eth stats collected by the port */
1413         struct i40e_eth_stats eth;
1414
1415         /* additional port specific stats */
1416         u64 tx_dropped_link_down;       /* tdold */
1417         u64 crc_errors;                 /* crcerrs */
1418         u64 illegal_bytes;              /* illerrc */
1419         u64 error_bytes;                /* errbc */
1420         u64 mac_local_faults;           /* mlfc */
1421         u64 mac_remote_faults;          /* mrfc */
1422         u64 rx_length_errors;           /* rlec */
1423         u64 link_xon_rx;                /* lxonrxc */
1424         u64 link_xoff_rx;               /* lxoffrxc */
1425         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1426         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1427         u64 link_xon_tx;                /* lxontxc */
1428         u64 link_xoff_tx;               /* lxofftxc */
1429         u64 priority_xon_tx[8];         /* pxontxc[8] */
1430         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1431         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1432         u64 rx_size_64;                 /* prc64 */
1433         u64 rx_size_127;                /* prc127 */
1434         u64 rx_size_255;                /* prc255 */
1435         u64 rx_size_511;                /* prc511 */
1436         u64 rx_size_1023;               /* prc1023 */
1437         u64 rx_size_1522;               /* prc1522 */
1438         u64 rx_size_big;                /* prc9522 */
1439         u64 rx_undersize;               /* ruc */
1440         u64 rx_fragments;               /* rfc */
1441         u64 rx_oversize;                /* roc */
1442         u64 rx_jabber;                  /* rjc */
1443         u64 tx_size_64;                 /* ptc64 */
1444         u64 tx_size_127;                /* ptc127 */
1445         u64 tx_size_255;                /* ptc255 */
1446         u64 tx_size_511;                /* ptc511 */
1447         u64 tx_size_1023;               /* ptc1023 */
1448         u64 tx_size_1522;               /* ptc1522 */
1449         u64 tx_size_big;                /* ptc9522 */
1450         u64 mac_short_packet_dropped;   /* mspdc */
1451         u64 checksum_error;             /* xec */
1452         /* flow director stats */
1453         u64 fd_atr_match;
1454         u64 fd_sb_match;
1455         u64 fd_atr_tunnel_match;
1456         u32 fd_atr_status;
1457         u32 fd_sb_status;
1458         /* EEE LPI */
1459         u32 tx_lpi_status;
1460         u32 rx_lpi_status;
1461         u64 tx_lpi_count;               /* etlpic */
1462         u64 rx_lpi_count;               /* erlpic */
1463 };
1464
1465 /* Checksum and Shadow RAM pointers */
1466 #define I40E_SR_NVM_CONTROL_WORD                0x00
1467 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1468 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1469 #define I40E_SR_OPTION_ROM_PTR                  0x05
1470 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1471 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1472 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1473 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1474 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1475 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1476 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1477 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1478 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1479 #define I40E_EMP_MODULE_PTR                     0x0F
1480 #define I40E_SR_EMP_MODULE_PTR                  0x48
1481 #define I40E_SR_PBA_FLAGS                       0x15
1482 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1483 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1484 #define I40E_NVM_OEM_VER_OFF                    0x83
1485 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1486 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1487 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1488 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1489 #define I40E_SR_NVM_MAP_VERSION                 0x29
1490 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1491 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1492 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1493 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1494 #define I40E_SR_VPD_PTR                         0x2F
1495 #define I40E_SR_PXE_SETUP_PTR                   0x30
1496 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1497 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1498 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1499 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1500 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1501 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1502 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1503 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1504 #define I40E_SR_PHY_ACTIVITY_LIST_PTR           0x3D
1505 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1506 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1507 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1508 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1509 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1510 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1511 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1512 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1513 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1514 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1515
1516 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1517 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1518 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1519 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1520 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1521 #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID   BIT(5)
1522 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE          BIT(12)
1523 #define I40E_PTR_TYPE                           BIT(15)
1524 #define I40E_SR_OCP_CFG_WORD0                   0x2B
1525 #define I40E_SR_OCP_ENABLED                     BIT(15)
1526
1527 /* Shadow RAM related */
1528 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1529 #define I40E_SR_BUF_ALIGNMENT           4096
1530 #define I40E_SR_WORDS_IN_1KB            512
1531 /* Checksum should be calculated such that after adding all the words,
1532  * including the checksum word itself, the sum should be 0xBABA.
1533  */
1534 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1535
1536 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1537
1538 enum i40e_switch_element_types {
1539         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1540         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1541         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1542         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1543         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1544         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1545         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1546         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1547         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1548 };
1549
1550 /* Supported EtherType filters */
1551 enum i40e_ether_type_index {
1552         I40E_ETHER_TYPE_1588            = 0,
1553         I40E_ETHER_TYPE_FIP             = 1,
1554         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1555         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1556         I40E_ETHER_TYPE_LLDP            = 4,
1557         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1558         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1559         I40E_ETHER_TYPE_QCN_CNM         = 7,
1560         I40E_ETHER_TYPE_8021X           = 8,
1561         I40E_ETHER_TYPE_ARP             = 9,
1562         I40E_ETHER_TYPE_RSV1            = 10,
1563         I40E_ETHER_TYPE_RSV2            = 11,
1564 };
1565
1566 /* Filter context base size is 1K */
1567 #define I40E_HASH_FILTER_BASE_SIZE      1024
1568 /* Supported Hash filter values */
1569 enum i40e_hash_filter_size {
1570         I40E_HASH_FILTER_SIZE_1K        = 0,
1571         I40E_HASH_FILTER_SIZE_2K        = 1,
1572         I40E_HASH_FILTER_SIZE_4K        = 2,
1573         I40E_HASH_FILTER_SIZE_8K        = 3,
1574         I40E_HASH_FILTER_SIZE_16K       = 4,
1575         I40E_HASH_FILTER_SIZE_32K       = 5,
1576         I40E_HASH_FILTER_SIZE_64K       = 6,
1577         I40E_HASH_FILTER_SIZE_128K      = 7,
1578         I40E_HASH_FILTER_SIZE_256K      = 8,
1579         I40E_HASH_FILTER_SIZE_512K      = 9,
1580         I40E_HASH_FILTER_SIZE_1M        = 10,
1581 };
1582
1583 /* DMA context base size is 0.5K */
1584 #define I40E_DMA_CNTX_BASE_SIZE         512
1585 /* Supported DMA context values */
1586 enum i40e_dma_cntx_size {
1587         I40E_DMA_CNTX_SIZE_512          = 0,
1588         I40E_DMA_CNTX_SIZE_1K           = 1,
1589         I40E_DMA_CNTX_SIZE_2K           = 2,
1590         I40E_DMA_CNTX_SIZE_4K           = 3,
1591         I40E_DMA_CNTX_SIZE_8K           = 4,
1592         I40E_DMA_CNTX_SIZE_16K          = 5,
1593         I40E_DMA_CNTX_SIZE_32K          = 6,
1594         I40E_DMA_CNTX_SIZE_64K          = 7,
1595         I40E_DMA_CNTX_SIZE_128K         = 8,
1596         I40E_DMA_CNTX_SIZE_256K         = 9,
1597 };
1598
1599 /* Supported Hash look up table (LUT) sizes */
1600 enum i40e_hash_lut_size {
1601         I40E_HASH_LUT_SIZE_128          = 0,
1602         I40E_HASH_LUT_SIZE_512          = 1,
1603 };
1604
1605 /* Structure to hold a per PF filter control settings */
1606 struct i40e_filter_control_settings {
1607         /* number of PE Quad Hash filter buckets */
1608         enum i40e_hash_filter_size pe_filt_num;
1609         /* number of PE Quad Hash contexts */
1610         enum i40e_dma_cntx_size pe_cntx_num;
1611         /* number of FCoE filter buckets */
1612         enum i40e_hash_filter_size fcoe_filt_num;
1613         /* number of FCoE DDP contexts */
1614         enum i40e_dma_cntx_size fcoe_cntx_num;
1615         /* size of the Hash LUT */
1616         enum i40e_hash_lut_size hash_lut_size;
1617         /* enable FDIR filters for PF and its VFs */
1618         bool enable_fdir;
1619         /* enable Ethertype filters for PF and its VFs */
1620         bool enable_ethtype;
1621         /* enable MAC/VLAN filters for PF and its VFs */
1622         bool enable_macvlan;
1623 };
1624
1625 /* Structure to hold device level control filter counts */
1626 struct i40e_control_filter_stats {
1627         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1628         u16 etype_used;       /* Used perfect EtherType filters */
1629         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1630         u16 etype_free;       /* Un-used perfect EtherType filters */
1631 };
1632
1633 enum i40e_reset_type {
1634         I40E_RESET_POR          = 0,
1635         I40E_RESET_CORER        = 1,
1636         I40E_RESET_GLOBR        = 2,
1637         I40E_RESET_EMPR         = 3,
1638 };
1639
1640 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1641 #define I40E_NVM_LLDP_CFG_PTR   0x06
1642 #define I40E_SR_LLDP_CFG_PTR    0x31
1643 struct i40e_lldp_variables {
1644         u16 length;
1645         u16 adminstatus;
1646         u16 msgfasttx;
1647         u16 msgtxinterval;
1648         u16 txparams;
1649         u16 timers;
1650         u16 crc8;
1651 };
1652
1653 /* Offsets into Alternate Ram */
1654 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1655 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1656 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1657 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1658 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1659 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1660
1661 /* Alternate Ram Bandwidth Masks */
1662 #define I40E_ALT_BW_VALUE_MASK          0xFF
1663 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1664 #define I40E_ALT_BW_VALID_MASK          0x80000000
1665
1666 /* RSS Hash Table Size */
1667 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1668
1669 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1670 #define I40E_L3_SRC_SHIFT               47
1671 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1672 #define I40E_L3_V6_SRC_SHIFT            43
1673 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1674 #define I40E_L3_DST_SHIFT               35
1675 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1676 #define I40E_L3_V6_DST_SHIFT            35
1677 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1678 #define I40E_L4_SRC_SHIFT               34
1679 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1680 #define I40E_L4_DST_SHIFT               33
1681 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1682 #define I40E_VERIFY_TAG_SHIFT           31
1683 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1684
1685 #define I40E_FLEX_50_SHIFT              13
1686 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1687 #define I40E_FLEX_51_SHIFT              12
1688 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1689 #define I40E_FLEX_52_SHIFT              11
1690 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1691 #define I40E_FLEX_53_SHIFT              10
1692 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1693 #define I40E_FLEX_54_SHIFT              9
1694 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1695 #define I40E_FLEX_55_SHIFT              8
1696 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1697 #define I40E_FLEX_56_SHIFT              7
1698 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1699 #define I40E_FLEX_57_SHIFT              6
1700 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1701 #endif /* _I40E_TYPE_H_ */