sys/dev/ixl/i40e_type.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2013-2015, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
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  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _I40E_TYPE_H_
  36 #define _I40E_TYPE_H_
  37
  38 #include "i40e_status.h"
  39 #include "i40e_osdep.h"
  40 #include "i40e_register.h"
  41 #include "i40e_adminq.h"
  42 #include "i40e_hmc.h"
  43 #include "i40e_lan_hmc.h"
  44 #include "i40e_devids.h"
  45
  46
  47 #define BIT(a) (1UL << (a))
  48 #define BIT_ULL(a) (1ULL << (a))
  49
  50 #ifndef I40E_MASK
  51 /* I40E_MASK is a macro used on 32 bit registers */
  52 #define I40E_MASK(mask, shift) (mask << shift)
  53 #endif
  54
  55 #define I40E_MAX_PF                     16
  56 #define I40E_MAX_PF_VSI                 64
  57 #define I40E_MAX_PF_QP                  128
  58 #define I40E_MAX_VSI_QP                 16
  59 #define I40E_MAX_VF_VSI                 3
  60 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  61 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  62
  63 /* something less than 1 minute */
  64 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  65
  66 /* Max default timeout in ms, */
  67 #define I40E_MAX_NVM_TIMEOUT            18000
  68
  69 /* Check whether address is multicast. */
  70 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  71
  72 /* Check whether an address is broadcast. */
  73 #define I40E_IS_BROADCAST(address)      \
  74         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  75         (((u8 *)(address))[1] == ((u8)0xff)))
  76
  77 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  78 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  79
  80 /* forward declaration */
  81 struct i40e_hw;
  82 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  83
  84 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  85 /* Data type manipulation macros. */
  86 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  87 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  88
  89 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
  90 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
  91
  92 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
  93 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
  94
  95 /* Number of Transmit Descriptors must be a multiple of 8. */
  96 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
  97 /* Number of Receive Descriptors must be a multiple of 32 if
  98  * the number of descriptors is greater than 32.
  99  */
 100 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 101
 102 #define I40E_DESC_UNUSED(R)     \
 103         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 104         (R)->next_to_clean - (R)->next_to_use - 1)
 105
 106 /* bitfields for Tx queue mapping in QTX_CTL */
 107 #define I40E_QTX_CTL_VF_QUEUE   0x0
 108 #define I40E_QTX_CTL_VM_QUEUE   0x1
 109 #define I40E_QTX_CTL_PF_QUEUE   0x2
 110
 111 /* debug masks - set these bits in hw->debug_mask to control output */
 112 enum i40e_debug_mask {
 113         I40E_DEBUG_INIT                 = 0x00000001,
 114         I40E_DEBUG_RELEASE              = 0x00000002,
 115
 116         I40E_DEBUG_LINK                 = 0x00000010,
 117         I40E_DEBUG_PHY                  = 0x00000020,
 118         I40E_DEBUG_HMC                  = 0x00000040,
 119         I40E_DEBUG_NVM                  = 0x00000080,
 120         I40E_DEBUG_LAN                  = 0x00000100,
 121         I40E_DEBUG_FLOW                 = 0x00000200,
 122         I40E_DEBUG_DCB                  = 0x00000400,
 123         I40E_DEBUG_DIAG                 = 0x00000800,
 124         I40E_DEBUG_FD                   = 0x00001000,
 125
 126         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 127         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 128         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 129         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 130         I40E_DEBUG_AQ                   = 0x0F000000,
 131
 132         I40E_DEBUG_USER                 = 0xF0000000,
 133
 134         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 135 };
 136
 137 /* PCI Bus Info */
 138 #define I40E_PCI_LINK_STATUS            0xB2
 139 #define I40E_PCI_LINK_WIDTH             0x3F0
 140 #define I40E_PCI_LINK_WIDTH_1           0x10
 141 #define I40E_PCI_LINK_WIDTH_2           0x20
 142 #define I40E_PCI_LINK_WIDTH_4           0x40
 143 #define I40E_PCI_LINK_WIDTH_8           0x80
 144 #define I40E_PCI_LINK_SPEED             0xF
 145 #define I40E_PCI_LINK_SPEED_2500        0x1
 146 #define I40E_PCI_LINK_SPEED_5000        0x2
 147 #define I40E_PCI_LINK_SPEED_8000        0x3
 148
 149 #define I40E_MDIO_CLAUSE22_STCODE_MASK  I40E_MASK(1, \
 150                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 151 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_MASK(1, \
 152                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 153 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_MASK(2, \
 154                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 155
 156 #define I40E_MDIO_CLAUSE45_STCODE_MASK  I40E_MASK(0, \
 157                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 158 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_MASK(0, \
 159                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 160 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_MASK(1, \
 161                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 162 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    I40E_MASK(2, \
 163                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 164 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_MASK(3, \
 165                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 166
 167 #define I40E_PHY_COM_REG_PAGE                   0x1E
 168 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 169 #define I40E_PHY_LED_MANUAL_ON                  0x100
 170 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 171 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 172 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 173
 174 /* Memory types */
 175 enum i40e_memset_type {
 176         I40E_NONDMA_MEM = 0,
 177         I40E_DMA_MEM
 178 };
 179
 180 /* Memcpy types */
 181 enum i40e_memcpy_type {
 182         I40E_NONDMA_TO_NONDMA = 0,
 183         I40E_NONDMA_TO_DMA,
 184         I40E_DMA_TO_DMA,
 185         I40E_DMA_TO_NONDMA
 186 };
 187
 188 #define I40E_FW_API_VERSION_MINOR_X722  0x0005
 189 #define I40E_FW_API_VERSION_MINOR_X710  0x0005
 190
 191
 192 /* These are structs for managing the hardware information and the operations.
 193  * The structures of function pointers are filled out at init time when we
 194  * know for sure exactly which hardware we're working with.  This gives us the
 195  * flexibility of using the same main driver code but adapting to slightly
 196  * different hardware needs as new parts are developed.  For this architecture,
 197  * the Firmware and AdminQ are intended to insulate the driver from most of the
 198  * future changes, but these structures will also do part of the job.
 199  */
 200 enum i40e_mac_type {
 201         I40E_MAC_UNKNOWN = 0,
 202         I40E_MAC_XL710,
 203         I40E_MAC_VF,
 204         I40E_MAC_X722,
 205         I40E_MAC_X722_VF,
 206         I40E_MAC_GENERIC,
 207 };
 208
 209 enum i40e_media_type {
 210         I40E_MEDIA_TYPE_UNKNOWN = 0,
 211         I40E_MEDIA_TYPE_FIBER,
 212         I40E_MEDIA_TYPE_BASET,
 213         I40E_MEDIA_TYPE_BACKPLANE,
 214         I40E_MEDIA_TYPE_CX4,
 215         I40E_MEDIA_TYPE_DA,
 216         I40E_MEDIA_TYPE_VIRTUAL
 217 };
 218
 219 enum i40e_fc_mode {
 220         I40E_FC_NONE = 0,
 221         I40E_FC_RX_PAUSE,
 222         I40E_FC_TX_PAUSE,
 223         I40E_FC_FULL,
 224         I40E_FC_PFC,
 225         I40E_FC_DEFAULT
 226 };
 227
 228 enum i40e_set_fc_aq_failures {
 229         I40E_SET_FC_AQ_FAIL_NONE = 0,
 230         I40E_SET_FC_AQ_FAIL_GET = 1,
 231         I40E_SET_FC_AQ_FAIL_SET = 2,
 232         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 233         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 234 };
 235
 236 enum i40e_vsi_type {
 237         I40E_VSI_MAIN   = 0,
 238         I40E_VSI_VMDQ1  = 1,
 239         I40E_VSI_VMDQ2  = 2,
 240         I40E_VSI_CTRL   = 3,
 241         I40E_VSI_FCOE   = 4,
 242         I40E_VSI_MIRROR = 5,
 243         I40E_VSI_SRIOV  = 6,
 244         I40E_VSI_FDIR   = 7,
 245         I40E_VSI_TYPE_UNKNOWN
 246 };
 247
 248 enum i40e_queue_type {
 249         I40E_QUEUE_TYPE_RX = 0,
 250         I40E_QUEUE_TYPE_TX,
 251         I40E_QUEUE_TYPE_PE_CEQ,
 252         I40E_QUEUE_TYPE_UNKNOWN
 253 };
 254
 255 struct i40e_link_status {
 256         enum i40e_aq_phy_type phy_type;
 257         enum i40e_aq_link_speed link_speed;
 258         u8 link_info;
 259         u8 an_info;
 260         u8 fec_info;
 261         u8 ext_info;
 262         u8 loopback;
 263         /* is Link Status Event notification to SW enabled */
 264         bool lse_enable;
 265         u16 max_frame_size;
 266         bool crc_enable;
 267         u8 pacing;
 268         u8 requested_speeds;
 269         u8 module_type[3];
 270         /* 1st byte: module identifier */
 271 #define I40E_MODULE_TYPE_SFP            0x03
 272 #define I40E_MODULE_TYPE_QSFP           0x0D
 273         /* 2nd byte: ethernet compliance codes for 10/40G */
 274 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 275 #define I40E_MODULE_TYPE_40G_LR4        0x02
 276 #define I40E_MODULE_TYPE_40G_SR4        0x04
 277 #define I40E_MODULE_TYPE_40G_CR4        0x08
 278 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 279 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 280 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 281 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 282         /* 3rd byte: ethernet compliance codes for 1G */
 283 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 284 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 285 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 286 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 287 };
 288
 289 struct i40e_phy_info {
 290         struct i40e_link_status link_info;
 291         struct i40e_link_status link_info_old;
 292         bool get_link_info;
 293         enum i40e_media_type media_type;
 294         /* all the phy types the NVM is capable of */
 295         u64 phy_types;
 296 };
 297
 298 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 299 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 300 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 301 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 302 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 303 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 304 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 305 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 306 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 307 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 308 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 309 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 310 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 311 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 312 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 313 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 314 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 315 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 316 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 317 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 318 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 319 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 320 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 321 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 322 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 323 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 324 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 325                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 326 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 327 /*
 328  * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
 329  * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
 330  * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
 331  * a shift is needed to adjust for this with values larger than 31. The
 332  * only affected values are I40E_PHY_TYPE_25GBASE_*.
 333  */
 334 #define I40E_PHY_TYPE_OFFSET 1
 335 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
 336                                              I40E_PHY_TYPE_OFFSET)
 337 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
 338                                              I40E_PHY_TYPE_OFFSET)
 339 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
 340                                              I40E_PHY_TYPE_OFFSET)
 341 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
 342                                              I40E_PHY_TYPE_OFFSET)
 343 #define I40E_HW_CAP_MAX_GPIO                    30
 344 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 345 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 346
 347 enum i40e_acpi_programming_method {
 348         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 349         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 350 };
 351
 352 #define I40E_WOL_SUPPORT_MASK                   0x1
 353 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       0x2
 354 #define I40E_PROXY_SUPPORT_MASK                 0x4
 355
 356 /* Capabilities of a PF or a VF or the whole device */
 357 struct i40e_hw_capabilities {
 358         u32  switch_mode;
 359 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 360 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 361 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 362
 363         u32  management_mode;
 364         u32  mng_protocols_over_mctp;
 365 #define I40E_MNG_PROTOCOL_PLDM          0x2
 366 #define I40E_MNG_PROTOCOL_OEM_COMMANDS  0x4
 367 #define I40E_MNG_PROTOCOL_NCSI          0x8
 368         u32  npar_enable;
 369         u32  os2bmc;
 370         u32  valid_functions;
 371         bool sr_iov_1_1;
 372         bool vmdq;
 373         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 374         bool evb_802_1_qbh; /* Bridge Port Extension */
 375         bool dcb;
 376         bool fcoe;
 377         bool iscsi; /* Indicates iSCSI enabled */
 378         bool flex10_enable;
 379         bool flex10_capable;
 380         u32  flex10_mode;
 381 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 382 #define I40E_FLEX10_MODE_DCC            0x1
 383 #define I40E_FLEX10_MODE_DCI            0x2
 384
 385         u32 flex10_status;
 386 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 387 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 388
 389         bool sec_rev_disabled;
 390         bool update_disabled;
 391 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 392 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 393
 394         bool mgmt_cem;
 395         bool ieee_1588;
 396         bool iwarp;
 397         bool fd;
 398         u32 fd_filters_guaranteed;
 399         u32 fd_filters_best_effort;
 400         bool rss;
 401         u32 rss_table_size;
 402         u32 rss_table_entry_width;
 403         bool led[I40E_HW_CAP_MAX_GPIO];
 404         bool sdp[I40E_HW_CAP_MAX_GPIO];
 405         u32 nvm_image_type;
 406         u32 num_flow_director_filters;
 407         u32 num_vfs;
 408         u32 vf_base_id;
 409         u32 num_vsis;
 410         u32 num_rx_qp;
 411         u32 num_tx_qp;
 412         u32 base_queue;
 413         u32 num_msix_vectors;
 414         u32 num_msix_vectors_vf;
 415         u32 led_pin_num;
 416         u32 sdp_pin_num;
 417         u32 mdio_port_num;
 418         u32 mdio_port_mode;
 419         u8 rx_buf_chain_len;
 420         u32 enabled_tcmap;
 421         u32 maxtc;
 422         u64 wr_csr_prot;
 423         bool apm_wol_support;
 424         enum i40e_acpi_programming_method acpi_prog_method;
 425         bool proxy_support;
 426 };
 427
 428 struct i40e_mac_info {
 429         enum i40e_mac_type type;
 430         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 431         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 432         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 433         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 434         u16 max_fcoeq;
 435 };
 436
 437 enum i40e_aq_resources_ids {
 438         I40E_NVM_RESOURCE_ID = 1
 439 };
 440
 441 enum i40e_aq_resource_access_type {
 442         I40E_RESOURCE_READ = 1,
 443         I40E_RESOURCE_WRITE
 444 };
 445
 446 struct i40e_nvm_info {
 447         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 448         u32 timeout;              /* [ms] */
 449         u16 sr_size;              /* Shadow RAM size in words */
 450         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 451         u16 version;              /* NVM package version */
 452         u32 eetrack;              /* NVM data version */
 453         u32 oem_ver;              /* OEM version info */
 454 };
 455
 456 /* definitions used in NVM update support */
 457
 458 enum i40e_nvmupd_cmd {
 459         I40E_NVMUPD_INVALID,
 460         I40E_NVMUPD_READ_CON,
 461         I40E_NVMUPD_READ_SNT,
 462         I40E_NVMUPD_READ_LCB,
 463         I40E_NVMUPD_READ_SA,
 464         I40E_NVMUPD_WRITE_ERA,
 465         I40E_NVMUPD_WRITE_CON,
 466         I40E_NVMUPD_WRITE_SNT,
 467         I40E_NVMUPD_WRITE_LCB,
 468         I40E_NVMUPD_WRITE_SA,
 469         I40E_NVMUPD_CSUM_CON,
 470         I40E_NVMUPD_CSUM_SA,
 471         I40E_NVMUPD_CSUM_LCB,
 472         I40E_NVMUPD_STATUS,
 473         I40E_NVMUPD_EXEC_AQ,
 474         I40E_NVMUPD_GET_AQ_RESULT,
 475 };
 476
 477 enum i40e_nvmupd_state {
 478         I40E_NVMUPD_STATE_INIT,
 479         I40E_NVMUPD_STATE_READING,
 480         I40E_NVMUPD_STATE_WRITING,
 481         I40E_NVMUPD_STATE_INIT_WAIT,
 482         I40E_NVMUPD_STATE_WRITE_WAIT,
 483         I40E_NVMUPD_STATE_ERROR
 484 };
 485
 486 /* nvm_access definition and its masks/shifts need to be accessible to
 487  * application, core driver, and shared code.  Where is the right file?
 488  */
 489 #define I40E_NVM_READ   0xB
 490 #define I40E_NVM_WRITE  0xC
 491
 492 #define I40E_NVM_MOD_PNT_MASK 0xFF
 493
 494 #define I40E_NVM_TRANS_SHIFT    8
 495 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 496 #define I40E_NVM_CON            0x0
 497 #define I40E_NVM_SNT            0x1
 498 #define I40E_NVM_LCB            0x2
 499 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 500 #define I40E_NVM_ERA            0x4
 501 #define I40E_NVM_CSUM           0x8
 502 #define I40E_NVM_EXEC           0xf
 503
 504 #define I40E_NVM_ADAPT_SHIFT    16
 505 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 506
 507 #define I40E_NVMUPD_MAX_DATA    4096
 508 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 509
 510 struct i40e_nvm_access {
 511         u32 command;
 512         u32 config;
 513         u32 offset;     /* in bytes */
 514         u32 data_size;  /* in bytes */
 515         u8 data[1];
 516 };
 517
 518 /* PCI bus types */
 519 enum i40e_bus_type {
 520         i40e_bus_type_unknown = 0,
 521         i40e_bus_type_pci,
 522         i40e_bus_type_pcix,
 523         i40e_bus_type_pci_express,
 524         i40e_bus_type_reserved
 525 };
 526
 527 /* PCI bus speeds */
 528 enum i40e_bus_speed {
 529         i40e_bus_speed_unknown  = 0,
 530         i40e_bus_speed_33       = 33,
 531         i40e_bus_speed_66       = 66,
 532         i40e_bus_speed_100      = 100,
 533         i40e_bus_speed_120      = 120,
 534         i40e_bus_speed_133      = 133,
 535         i40e_bus_speed_2500     = 2500,
 536         i40e_bus_speed_5000     = 5000,
 537         i40e_bus_speed_8000     = 8000,
 538         i40e_bus_speed_reserved
 539 };
 540
 541 /* PCI bus widths */
 542 enum i40e_bus_width {
 543         i40e_bus_width_unknown  = 0,
 544         i40e_bus_width_pcie_x1  = 1,
 545         i40e_bus_width_pcie_x2  = 2,
 546         i40e_bus_width_pcie_x4  = 4,
 547         i40e_bus_width_pcie_x8  = 8,
 548         i40e_bus_width_32       = 32,
 549         i40e_bus_width_64       = 64,
 550         i40e_bus_width_reserved
 551 };
 552
 553 /* Bus parameters */
 554 struct i40e_bus_info {
 555         enum i40e_bus_speed speed;
 556         enum i40e_bus_width width;
 557         enum i40e_bus_type type;
 558
 559         u16 func;
 560         u16 device;
 561         u16 lan_id;
 562         u16 bus_id;
 563 };
 564
 565 /* Flow control (FC) parameters */
 566 struct i40e_fc_info {
 567         enum i40e_fc_mode current_mode; /* FC mode in effect */
 568         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 569 };
 570
 571 #define I40E_MAX_TRAFFIC_CLASS          8
 572 #define I40E_MAX_USER_PRIORITY          8
 573 #define I40E_DCBX_MAX_APPS              32
 574 #define I40E_LLDPDU_SIZE                1500
 575 #define I40E_TLV_STATUS_OPER            0x1
 576 #define I40E_TLV_STATUS_SYNC            0x2
 577 #define I40E_TLV_STATUS_ERR             0x4
 578 #define I40E_CEE_OPER_MAX_APPS          3
 579 #define I40E_APP_PROTOID_FCOE           0x8906
 580 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 581 #define I40E_APP_PROTOID_FIP            0x8914
 582 #define I40E_APP_SEL_ETHTYPE            0x1
 583 #define I40E_APP_SEL_TCPIP              0x2
 584 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 585 #define I40E_CEE_APP_SEL_TCPIP          0x1
 586
 587 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 588 struct i40e_dcb_ets_config {
 589         u8 willing;
 590         u8 cbs;
 591         u8 maxtcs;
 592         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 593         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 594         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 595 };
 596
 597 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 598 struct i40e_dcb_pfc_config {
 599         u8 willing;
 600         u8 mbc;
 601         u8 pfccap;
 602         u8 pfcenable;
 603 };
 604
 605 /* CEE or IEEE 802.1Qaz Application Priority data */
 606 struct i40e_dcb_app_priority_table {
 607         u8  priority;
 608         u8  selector;
 609         u16 protocolid;
 610 };
 611
 612 struct i40e_dcbx_config {
 613         u8  dcbx_mode;
 614 #define I40E_DCBX_MODE_CEE      0x1
 615 #define I40E_DCBX_MODE_IEEE     0x2
 616         u8  app_mode;
 617 #define I40E_DCBX_APPS_NON_WILLING      0x1
 618         u32 numapps;
 619         u32 tlv_status; /* CEE mode TLV status */
 620         struct i40e_dcb_ets_config etscfg;
 621         struct i40e_dcb_ets_config etsrec;
 622         struct i40e_dcb_pfc_config pfc;
 623         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 624 };
 625
 626 /* Port hardware description */
 627 struct i40e_hw {
 628         u8 *hw_addr;
 629         void *back;
 630
 631         /* subsystem structs */
 632         struct i40e_phy_info phy;
 633         struct i40e_mac_info mac;
 634         struct i40e_bus_info bus;
 635         struct i40e_nvm_info nvm;
 636         struct i40e_fc_info fc;
 637
 638         /* pci info */
 639         u16 device_id;
 640         u16 vendor_id;
 641         u16 subsystem_device_id;
 642         u16 subsystem_vendor_id;
 643         u8 revision_id;
 644         u8 port;
 645         bool adapter_stopped;
 646
 647         /* capabilities for entire device and PCI func */
 648         struct i40e_hw_capabilities dev_caps;
 649         struct i40e_hw_capabilities func_caps;
 650
 651         /* Flow Director shared filter space */
 652         u16 fdir_shared_filter_count;
 653
 654         /* device profile info */
 655         u8  pf_id;
 656         u16 main_vsi_seid;
 657
 658         /* for multi-function MACs */
 659         u16 partition_id;
 660         u16 num_partitions;
 661         u16 num_ports;
 662
 663         /* Closest numa node to the device */
 664         u16 numa_node;
 665
 666         /* Admin Queue info */
 667         struct i40e_adminq_info aq;
 668
 669         /* state of nvm update process */
 670         enum i40e_nvmupd_state nvmupd_state;
 671         struct i40e_aq_desc nvm_wb_desc;
 672         struct i40e_virt_mem nvm_buff;
 673         bool nvm_release_on_done;
 674         u16 nvm_wait_opcode;
 675
 676         /* HMC info */
 677         struct i40e_hmc_info hmc; /* HMC info struct */
 678
 679         /* LLDP/DCBX Status */
 680         u16 dcbx_status;
 681
 682         /* DCBX info */
 683         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 684         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 685         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 686
 687         /* WoL and proxy support */
 688         u16 num_wol_proxy_filters;
 689         u16 wol_proxy_vsi_seid;
 690
 691 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 692         u64 flags;
 693
 694         /* debug mask */
 695         u32 debug_mask;
 696         char err_str[16];
 697 };
 698
 699 static INLINE bool i40e_is_vf(struct i40e_hw *hw)
 700 {
 701         return (hw->mac.type == I40E_MAC_VF ||
 702                 hw->mac.type == I40E_MAC_X722_VF);
 703 }
 704
 705 struct i40e_driver_version {
 706         u8 major_version;
 707         u8 minor_version;
 708         u8 build_version;
 709         u8 subbuild_version;
 710         u8 driver_string[32];
 711 };
 712
 713 /* RX Descriptors */
 714 union i40e_16byte_rx_desc {
 715         struct {
 716                 __le64 pkt_addr; /* Packet buffer address */
 717                 __le64 hdr_addr; /* Header buffer address */
 718         } read;
 719         struct {
 720                 struct {
 721                         struct {
 722                                 union {
 723                                         __le16 mirroring_status;
 724                                         __le16 fcoe_ctx_id;
 725                                 } mirr_fcoe;
 726                                 __le16 l2tag1;
 727                         } lo_dword;
 728                         union {
 729                                 __le32 rss; /* RSS Hash */
 730                                 __le32 fd_id; /* Flow director filter id */
 731                                 __le32 fcoe_param; /* FCoE DDP Context id */
 732                         } hi_dword;
 733                 } qword0;
 734                 struct {
 735                         /* ext status/error/pktype/length */
 736                         __le64 status_error_len;
 737                 } qword1;
 738         } wb;  /* writeback */
 739 };
 740
 741 union i40e_32byte_rx_desc {
 742         struct {
 743                 __le64  pkt_addr; /* Packet buffer address */
 744                 __le64  hdr_addr; /* Header buffer address */
 745                         /* bit 0 of hdr_buffer_addr is DD bit */
 746                 __le64  rsvd1;
 747                 __le64  rsvd2;
 748         } read;
 749         struct {
 750                 struct {
 751                         struct {
 752                                 union {
 753                                         __le16 mirroring_status;
 754                                         __le16 fcoe_ctx_id;
 755                                 } mirr_fcoe;
 756                                 __le16 l2tag1;
 757                         } lo_dword;
 758                         union {
 759                                 __le32 rss; /* RSS Hash */
 760                                 __le32 fcoe_param; /* FCoE DDP Context id */
 761                                 /* Flow director filter id in case of
 762                                  * Programming status desc WB
 763                                  */
 764                                 __le32 fd_id;
 765                         } hi_dword;
 766                 } qword0;
 767                 struct {
 768                         /* status/error/pktype/length */
 769                         __le64 status_error_len;
 770                 } qword1;
 771                 struct {
 772                         __le16 ext_status; /* extended status */
 773                         __le16 rsvd;
 774                         __le16 l2tag2_1;
 775                         __le16 l2tag2_2;
 776                 } qword2;
 777                 struct {
 778                         union {
 779                                 __le32 flex_bytes_lo;
 780                                 __le32 pe_status;
 781                         } lo_dword;
 782                         union {
 783                                 __le32 flex_bytes_hi;
 784                                 __le32 fd_id;
 785                         } hi_dword;
 786                 } qword3;
 787         } wb;  /* writeback */
 788 };
 789
 790 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 791 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 792                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 793 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 794 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 795                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 796
 797 enum i40e_rx_desc_status_bits {
 798         /* Note: These are predefined bit offsets */
 799         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 800         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 801         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 802         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 803         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 804         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 805         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 806         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 807
 808         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 809         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 810         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 811         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 812         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 813         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 814         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 815         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 816 };
 817
 818 #define I40E_RXD_QW1_STATUS_SHIFT       0
 819 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 820                                          I40E_RXD_QW1_STATUS_SHIFT)
 821
 822 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 823 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 824                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 825
 826 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 827 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 828
 829 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 830 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 831                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 832
 833 enum i40e_rx_desc_fltstat_values {
 834         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 835         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 836         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 837         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 838 };
 839
 840 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 841 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 842 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 843 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 844
 845 #define I40E_RXD_QW1_ERROR_SHIFT        19
 846 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 847
 848 enum i40e_rx_desc_error_bits {
 849         /* Note: These are predefined bit offsets */
 850         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 851         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 852         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 853         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 854         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 855         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 856         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 857         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 858         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 859 };
 860
 861 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 862         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 863         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 864         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 865         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 866         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 867 };
 868
 869 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 870 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 871
 872 /* Packet type non-ip values */
 873 enum i40e_rx_l2_ptype {
 874         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 875         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 876         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 877         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 878         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 879         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 880         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 881         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 882         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 883         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 884         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 885         I40E_RX_PTYPE_L2_ARP                            = 11,
 886         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 887         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 888         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 889         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 890         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 891         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 892         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 893         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 894         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 895         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 896         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 897         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 898         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 899         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 900 };
 901
 902 struct i40e_rx_ptype_decoded {
 903         u32 ptype:8;
 904         u32 known:1;
 905         u32 outer_ip:1;
 906         u32 outer_ip_ver:1;
 907         u32 outer_frag:1;
 908         u32 tunnel_type:3;
 909         u32 tunnel_end_prot:2;
 910         u32 tunnel_end_frag:1;
 911         u32 inner_prot:4;
 912         u32 payload_layer:3;
 913 };
 914
 915 enum i40e_rx_ptype_outer_ip {
 916         I40E_RX_PTYPE_OUTER_L2  = 0,
 917         I40E_RX_PTYPE_OUTER_IP  = 1
 918 };
 919
 920 enum i40e_rx_ptype_outer_ip_ver {
 921         I40E_RX_PTYPE_OUTER_NONE        = 0,
 922         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 923         I40E_RX_PTYPE_OUTER_IPV6        = 1
 924 };
 925
 926 enum i40e_rx_ptype_outer_fragmented {
 927         I40E_RX_PTYPE_NOT_FRAG  = 0,
 928         I40E_RX_PTYPE_FRAG      = 1
 929 };
 930
 931 enum i40e_rx_ptype_tunnel_type {
 932         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 933         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 934         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 935         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 936         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 937 };
 938
 939 enum i40e_rx_ptype_tunnel_end_prot {
 940         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 941         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 942         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 943 };
 944
 945 enum i40e_rx_ptype_inner_prot {
 946         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 947         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 948         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 949         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 950         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 951         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 952 };
 953
 954 enum i40e_rx_ptype_payload_layer {
 955         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 956         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 957         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 958         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 959 };
 960
 961 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 962 #define I40E_RX_PTYPE_SHIFT             56
 963
 964 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 965 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 966                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 967
 968 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 969 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 970                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 971
 972 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 973 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 974
 975 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 976 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 977
 978 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 979 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 980                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 981
 982 enum i40e_rx_desc_ext_status_bits {
 983         /* Note: These are predefined bit offsets */
 984         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 985         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 986         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 987         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 988         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 989         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 990         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 991 };
 992
 993 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
 994 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
 995
 996 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
 997 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
 998
 999 enum i40e_rx_desc_pe_status_bits {
1000         /* Note: These are predefined bit offsets */
1001         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1002         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1003         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1004         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1005         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1006         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1007         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1008         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1009         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1010 };
1011
1012 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1013 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1014
1015 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1016 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1017                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1018
1019 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1020 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1021                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1022
1023 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1024 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1025                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1026
1027 enum i40e_rx_prog_status_desc_status_bits {
1028         /* Note: These are predefined bit offsets */
1029         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1030         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1031 };
1032
1033 enum i40e_rx_prog_status_desc_prog_id_masks {
1034         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1035         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1036         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1037 };
1038
1039 enum i40e_rx_prog_status_desc_error_bits {
1040         /* Note: These are predefined bit offsets */
1041         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1042         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1043         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1044         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1045 };
1046
1047 #define I40E_TWO_BIT_MASK       0x3
1048 #define I40E_THREE_BIT_MASK     0x7
1049 #define I40E_FOUR_BIT_MASK      0xF
1050 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1051
1052 /* TX Descriptor */
1053 struct i40e_tx_desc {
1054         __le64 buffer_addr; /* Address of descriptor's data buf */
1055         __le64 cmd_type_offset_bsz;
1056 };
1057
1058 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1059 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1060
1061 enum i40e_tx_desc_dtype_value {
1062         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1063         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1064         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1065         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1066         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1067         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1068         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1069         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1070         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1071         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1072 };
1073
1074 #define I40E_TXD_QW1_CMD_SHIFT  4
1075 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1076
1077 enum i40e_tx_desc_cmd_bits {
1078         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1079         I40E_TX_DESC_CMD_RS                     = 0x0002,
1080         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1081         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1082         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1083         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1084         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1085         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1086         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1087         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1088         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1089         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1090         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1091         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1092         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1093         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1094         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1095         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1096 };
1097
1098 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1099 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1100                                          I40E_TXD_QW1_OFFSET_SHIFT)
1101
1102 enum i40e_tx_desc_length_fields {
1103         /* Note: These are predefined bit offsets */
1104         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1105         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1106         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1107 };
1108
1109 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1110 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1111 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1112 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1113
1114 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1115 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1116                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1117
1118 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1119 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1120
1121 /* Context descriptors */
1122 struct i40e_tx_context_desc {
1123         __le32 tunneling_params;
1124         __le16 l2tag2;
1125         __le16 rsvd;
1126         __le64 type_cmd_tso_mss;
1127 };
1128
1129 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1130 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1131
1132 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1133 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1134
1135 enum i40e_tx_ctx_desc_cmd_bits {
1136         I40E_TX_CTX_DESC_TSO            = 0x01,
1137         I40E_TX_CTX_DESC_TSYN           = 0x02,
1138         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1139         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1140         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1141         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1142         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1143         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1144         I40E_TX_CTX_DESC_SWPE           = 0x40
1145 };
1146
1147 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1148 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1149                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1150
1151 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1152 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1153                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1154
1155 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1156 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1157
1158 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1159 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1160                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1161
1162 enum i40e_tx_ctx_desc_eipt_offload {
1163         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1164         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1165         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1166         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1167 };
1168
1169 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1170 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1171                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1172
1173 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1174 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1175
1176 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1177 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1178
1179 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1180 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1181
1182 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1183
1184 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1185 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1186                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1187
1188 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1189 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1190                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1191
1192 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1193 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1194 struct i40e_nop_desc {
1195         __le64 rsvd;
1196         __le64 dtype_cmd;
1197 };
1198
1199 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1200 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1201
1202 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1203 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1204
1205 enum i40e_tx_nop_desc_cmd_bits {
1206         /* Note: These are predefined bit offsets */
1207         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1208         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1209         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1210 };
1211
1212 struct i40e_filter_program_desc {
1213         __le32 qindex_flex_ptype_vsi;
1214         __le32 rsvd;
1215         __le32 dtype_cmd_cntindex;
1216         __le32 fd_id;
1217 };
1218 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1219 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1220                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1221 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1222 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1223                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1224 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1225 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1226                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1227
1228 /* Packet Classifier Types for filters */
1229 enum i40e_filter_pctype {
1230         /* Note: Values 0-28 are reserved for future use.
1231          * Value 29, 30, 32 are not supported on XL710 and X710.
1232          */
1233         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1234         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1235         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1236         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1237         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1238         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1239         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1240         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1241         /* Note: Values 37-38 are reserved for future use.
1242          * Value 39, 40, 42 are not supported on XL710 and X710.
1243          */
1244         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1245         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1246         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1247         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1248         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1249         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1250         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1251         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1252         /* Note: Value 47 is reserved for future use */
1253         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1254         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1255         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1256         /* Note: Values 51-62 are reserved for future use */
1257         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1258 };
1259
1260 enum i40e_filter_program_desc_dest {
1261         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1262         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1263         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1264 };
1265
1266 enum i40e_filter_program_desc_fd_status {
1267         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1268         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1269         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1270         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1271 };
1272
1273 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1274 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1275                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1276
1277 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1278 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1279
1280 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1281 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1282                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1283
1284 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1285 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1286
1287 enum i40e_filter_program_desc_pcmd {
1288         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1289         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1290 };
1291
1292 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1293 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1294
1295 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1296 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1297
1298 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1299                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1300 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1301                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1302
1303 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1304                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1305 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1306
1307 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1308 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1309                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1310
1311 enum i40e_filter_type {
1312         I40E_FLOW_DIRECTOR_FLTR = 0,
1313         I40E_PE_QUAD_HASH_FLTR = 1,
1314         I40E_ETHERTYPE_FLTR,
1315         I40E_FCOE_CTX_FLTR,
1316         I40E_MAC_VLAN_FLTR,
1317         I40E_HASH_FLTR
1318 };
1319
1320 struct i40e_vsi_context {
1321         u16 seid;
1322         u16 uplink_seid;
1323         u16 vsi_number;
1324         u16 vsis_allocated;
1325         u16 vsis_unallocated;
1326         u16 flags;
1327         u8 pf_num;
1328         u8 vf_num;
1329         u8 connection_type;
1330         struct i40e_aqc_vsi_properties_data info;
1331 };
1332
1333 struct i40e_veb_context {
1334         u16 seid;
1335         u16 uplink_seid;
1336         u16 veb_number;
1337         u16 vebs_allocated;
1338         u16 vebs_unallocated;
1339         u16 flags;
1340         struct i40e_aqc_get_veb_parameters_completion info;
1341 };
1342
1343 /* Statistics collected by each port, VSI, VEB, and S-channel */
1344 struct i40e_eth_stats {
1345         u64 rx_bytes;                   /* gorc */
1346         u64 rx_unicast;                 /* uprc */
1347         u64 rx_multicast;               /* mprc */
1348         u64 rx_broadcast;               /* bprc */
1349         u64 rx_discards;                /* rdpc */
1350         u64 rx_unknown_protocol;        /* rupp */
1351         u64 tx_bytes;                   /* gotc */
1352         u64 tx_unicast;                 /* uptc */
1353         u64 tx_multicast;               /* mptc */
1354         u64 tx_broadcast;               /* bptc */
1355         u64 tx_discards;                /* tdpc */
1356         u64 tx_errors;                  /* tepc */
1357 };
1358
1359 /* Statistics collected per VEB per TC */
1360 struct i40e_veb_tc_stats {
1361         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1362         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1363         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1364         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1365 };
1366
1367 /* Statistics collected by the MAC */
1368 struct i40e_hw_port_stats {
1369         /* eth stats collected by the port */
1370         struct i40e_eth_stats eth;
1371
1372         /* additional port specific stats */
1373         u64 tx_dropped_link_down;       /* tdold */
1374         u64 crc_errors;                 /* crcerrs */
1375         u64 illegal_bytes;              /* illerrc */
1376         u64 error_bytes;                /* errbc */
1377         u64 mac_local_faults;           /* mlfc */
1378         u64 mac_remote_faults;          /* mrfc */
1379         u64 rx_length_errors;           /* rlec */
1380         u64 link_xon_rx;                /* lxonrxc */
1381         u64 link_xoff_rx;               /* lxoffrxc */
1382         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1383         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1384         u64 link_xon_tx;                /* lxontxc */
1385         u64 link_xoff_tx;               /* lxofftxc */
1386         u64 priority_xon_tx[8];         /* pxontxc[8] */
1387         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1388         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1389         u64 rx_size_64;                 /* prc64 */
1390         u64 rx_size_127;                /* prc127 */
1391         u64 rx_size_255;                /* prc255 */
1392         u64 rx_size_511;                /* prc511 */
1393         u64 rx_size_1023;               /* prc1023 */
1394         u64 rx_size_1522;               /* prc1522 */
1395         u64 rx_size_big;                /* prc9522 */
1396         u64 rx_undersize;               /* ruc */
1397         u64 rx_fragments;               /* rfc */
1398         u64 rx_oversize;                /* roc */
1399         u64 rx_jabber;                  /* rjc */
1400         u64 tx_size_64;                 /* ptc64 */
1401         u64 tx_size_127;                /* ptc127 */
1402         u64 tx_size_255;                /* ptc255 */
1403         u64 tx_size_511;                /* ptc511 */
1404         u64 tx_size_1023;               /* ptc1023 */
1405         u64 tx_size_1522;               /* ptc1522 */
1406         u64 tx_size_big;                /* ptc9522 */
1407         u64 mac_short_packet_dropped;   /* mspdc */
1408         u64 checksum_error;             /* xec */
1409         /* flow director stats */
1410         u64 fd_atr_match;
1411         u64 fd_sb_match;
1412         u64 fd_atr_tunnel_match;
1413         u32 fd_atr_status;
1414         u32 fd_sb_status;
1415         /* EEE LPI */
1416         u32 tx_lpi_status;
1417         u32 rx_lpi_status;
1418         u64 tx_lpi_count;               /* etlpic */
1419         u64 rx_lpi_count;               /* erlpic */
1420 };
1421
1422 /* Checksum and Shadow RAM pointers */
1423 #define I40E_SR_NVM_CONTROL_WORD                0x00
1424 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1425 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1426 #define I40E_SR_OPTION_ROM_PTR                  0x05
1427 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1428 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1429 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1430 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1431 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1432 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1433 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1434 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1435 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1436 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1437 #define I40E_SR_PBA_FLAGS                       0x15
1438 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1439 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1440 #define I40E_NVM_OEM_VER_OFF                    0x83
1441 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1442 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1443 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1444 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1445 #define I40E_SR_NVM_MAP_VERSION                 0x29
1446 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1447 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1448 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1449 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1450 #define I40E_SR_VPD_PTR                         0x2F
1451 #define I40E_SR_PXE_SETUP_PTR                   0x30
1452 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1453 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1454 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1455 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1456 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1457 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1458 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1459 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1460 #define I40E_SR_PHY_ACTIVITY_LIST_PTR           0x3D
1461 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1462 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1463 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1464 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1465 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1466 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1467 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1468 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1469 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1470 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1471
1472 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1473 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1474 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1475 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1476 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1477
1478 /* Shadow RAM related */
1479 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1480 #define I40E_SR_BUF_ALIGNMENT           4096
1481 #define I40E_SR_WORDS_IN_1KB            512
1482 /* Checksum should be calculated such that after adding all the words,
1483  * including the checksum word itself, the sum should be 0xBABA.
1484  */
1485 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1486
1487 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1488
1489 enum i40e_switch_element_types {
1490         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1491         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1492         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1493         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1494         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1495         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1496         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1497         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1498         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1499 };
1500
1501 /* Supported EtherType filters */
1502 enum i40e_ether_type_index {
1503         I40E_ETHER_TYPE_1588            = 0,
1504         I40E_ETHER_TYPE_FIP             = 1,
1505         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1506         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1507         I40E_ETHER_TYPE_LLDP            = 4,
1508         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1509         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1510         I40E_ETHER_TYPE_QCN_CNM         = 7,
1511         I40E_ETHER_TYPE_8021X           = 8,
1512         I40E_ETHER_TYPE_ARP             = 9,
1513         I40E_ETHER_TYPE_RSV1            = 10,
1514         I40E_ETHER_TYPE_RSV2            = 11,
1515 };
1516
1517 /* Filter context base size is 1K */
1518 #define I40E_HASH_FILTER_BASE_SIZE      1024
1519 /* Supported Hash filter values */
1520 enum i40e_hash_filter_size {
1521         I40E_HASH_FILTER_SIZE_1K        = 0,
1522         I40E_HASH_FILTER_SIZE_2K        = 1,
1523         I40E_HASH_FILTER_SIZE_4K        = 2,
1524         I40E_HASH_FILTER_SIZE_8K        = 3,
1525         I40E_HASH_FILTER_SIZE_16K       = 4,
1526         I40E_HASH_FILTER_SIZE_32K       = 5,
1527         I40E_HASH_FILTER_SIZE_64K       = 6,
1528         I40E_HASH_FILTER_SIZE_128K      = 7,
1529         I40E_HASH_FILTER_SIZE_256K      = 8,
1530         I40E_HASH_FILTER_SIZE_512K      = 9,
1531         I40E_HASH_FILTER_SIZE_1M        = 10,
1532 };
1533
1534 /* DMA context base size is 0.5K */
1535 #define I40E_DMA_CNTX_BASE_SIZE         512
1536 /* Supported DMA context values */
1537 enum i40e_dma_cntx_size {
1538         I40E_DMA_CNTX_SIZE_512          = 0,
1539         I40E_DMA_CNTX_SIZE_1K           = 1,
1540         I40E_DMA_CNTX_SIZE_2K           = 2,
1541         I40E_DMA_CNTX_SIZE_4K           = 3,
1542         I40E_DMA_CNTX_SIZE_8K           = 4,
1543         I40E_DMA_CNTX_SIZE_16K          = 5,
1544         I40E_DMA_CNTX_SIZE_32K          = 6,
1545         I40E_DMA_CNTX_SIZE_64K          = 7,
1546         I40E_DMA_CNTX_SIZE_128K         = 8,
1547         I40E_DMA_CNTX_SIZE_256K         = 9,
1548 };
1549
1550 /* Supported Hash look up table (LUT) sizes */
1551 enum i40e_hash_lut_size {
1552         I40E_HASH_LUT_SIZE_128          = 0,
1553         I40E_HASH_LUT_SIZE_512          = 1,
1554 };
1555
1556 /* Structure to hold a per PF filter control settings */
1557 struct i40e_filter_control_settings {
1558         /* number of PE Quad Hash filter buckets */
1559         enum i40e_hash_filter_size pe_filt_num;
1560         /* number of PE Quad Hash contexts */
1561         enum i40e_dma_cntx_size pe_cntx_num;
1562         /* number of FCoE filter buckets */
1563         enum i40e_hash_filter_size fcoe_filt_num;
1564         /* number of FCoE DDP contexts */
1565         enum i40e_dma_cntx_size fcoe_cntx_num;
1566         /* size of the Hash LUT */
1567         enum i40e_hash_lut_size hash_lut_size;
1568         /* enable FDIR filters for PF and its VFs */
1569         bool enable_fdir;
1570         /* enable Ethertype filters for PF and its VFs */
1571         bool enable_ethtype;
1572         /* enable MAC/VLAN filters for PF and its VFs */
1573         bool enable_macvlan;
1574 };
1575
1576 /* Structure to hold device level control filter counts */
1577 struct i40e_control_filter_stats {
1578         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1579         u16 etype_used;       /* Used perfect EtherType filters */
1580         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1581         u16 etype_free;       /* Un-used perfect EtherType filters */
1582 };
1583
1584 enum i40e_reset_type {
1585         I40E_RESET_POR          = 0,
1586         I40E_RESET_CORER        = 1,
1587         I40E_RESET_GLOBR        = 2,
1588         I40E_RESET_EMPR         = 3,
1589 };
1590
1591 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1592 #define I40E_NVM_LLDP_CFG_PTR           0xD
1593 struct i40e_lldp_variables {
1594         u16 length;
1595         u16 adminstatus;
1596         u16 msgfasttx;
1597         u16 msgtxinterval;
1598         u16 txparams;
1599         u16 timers;
1600         u16 crc8;
1601 };
1602
1603 /* Offsets into Alternate Ram */
1604 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1605 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1606 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1607 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1608 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1609 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1610
1611 /* Alternate Ram Bandwidth Masks */
1612 #define I40E_ALT_BW_VALUE_MASK          0xFF
1613 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1614 #define I40E_ALT_BW_VALID_MASK          0x80000000
1615
1616 /* RSS Hash Table Size */
1617 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1618
1619 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1620 #define I40E_L3_SRC_SHIFT               47
1621 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1622 #define I40E_L3_V6_SRC_SHIFT            43
1623 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1624 #define I40E_L3_DST_SHIFT               35
1625 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1626 #define I40E_L3_V6_DST_SHIFT            35
1627 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1628 #define I40E_L4_SRC_SHIFT               34
1629 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1630 #define I40E_L4_DST_SHIFT               33
1631 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1632 #define I40E_VERIFY_TAG_SHIFT           31
1633 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1634
1635 #define I40E_FLEX_50_SHIFT              13
1636 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1637 #define I40E_FLEX_51_SHIFT              12
1638 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1639 #define I40E_FLEX_52_SHIFT              11
1640 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1641 #define I40E_FLEX_53_SHIFT              10
1642 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1643 #define I40E_FLEX_54_SHIFT              9
1644 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1645 #define I40E_FLEX_55_SHIFT              8
1646 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1647 #define I40E_FLEX_56_SHIFT              7
1648 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1649 #define I40E_FLEX_57_SHIFT              6
1650 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1651 #endif /* _I40E_TYPE_H_ */