sys/dev/ixl/i40e_type.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2013-2018, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
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  10       this list of conditions and the following disclaimer.
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  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _I40E_TYPE_H_
  36 #define _I40E_TYPE_H_
  37
  38 #include "i40e_status.h"
  39 #include "i40e_osdep.h"
  40 #include "i40e_register.h"
  41 #include "i40e_adminq.h"
  42 #include "i40e_hmc.h"
  43 #include "i40e_lan_hmc.h"
  44 #include "i40e_devids.h"
  45
  46
  47 #define BIT(a) (1UL << (a))
  48 #define BIT_ULL(a) (1ULL << (a))
  49
  50 #ifndef I40E_MASK
  51 /* I40E_MASK is a macro used on 32 bit registers */
  52 #define I40E_MASK(mask, shift) (mask << shift)
  53 #endif
  54
  55 #define I40E_MAX_PF                     16
  56 #define I40E_MAX_PF_VSI                 64
  57 #define I40E_MAX_PF_QP                  128
  58 #define I40E_MAX_VSI_QP                 16
  59 #define I40E_MAX_VF_VSI                 4
  60 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  61 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  62
  63 /* something less than 1 minute */
  64 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  65
  66 /* Max default timeout in ms, */
  67 #define I40E_MAX_NVM_TIMEOUT            18000
  68
  69 /* Max timeout in ms for the phy to respond */
  70 #define I40E_MAX_PHY_TIMEOUT            500
  71
  72 /* Check whether address is multicast. */
  73 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  74
  75 /* Check whether an address is broadcast. */
  76 #define I40E_IS_BROADCAST(address)      \
  77         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  78         (((u8 *)(address))[1] == ((u8)0xff)))
  79
  80 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  81 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  82
  83 /* forward declaration */
  84 struct i40e_hw;
  85 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  86
  87 #define ETH_ALEN        6
  88 /* Data type manipulation macros. */
  89 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  90 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  91
  92 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
  93 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
  94
  95 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
  96 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
  97
  98 /* Number of Transmit Descriptors must be a multiple of 32. */
  99 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 32
 100 /* Number of Receive Descriptors must be a multiple of 32 if
 101  * the number of descriptors is greater than 32.
 102  */
 103 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 104
 105 #define I40E_DESC_UNUSED(R)     \
 106         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 107         (R)->next_to_clean - (R)->next_to_use - 1)
 108
 109 /* bitfields for Tx queue mapping in QTX_CTL */
 110 #define I40E_QTX_CTL_VF_QUEUE   0x0
 111 #define I40E_QTX_CTL_VM_QUEUE   0x1
 112 #define I40E_QTX_CTL_PF_QUEUE   0x2
 113
 114 /* debug masks - set these bits in hw->debug_mask to control output */
 115 enum i40e_debug_mask {
 116         I40E_DEBUG_INIT                 = 0x00000001,
 117         I40E_DEBUG_RELEASE              = 0x00000002,
 118
 119         I40E_DEBUG_LINK                 = 0x00000010,
 120         I40E_DEBUG_PHY                  = 0x00000020,
 121         I40E_DEBUG_HMC                  = 0x00000040,
 122         I40E_DEBUG_NVM                  = 0x00000080,
 123         I40E_DEBUG_LAN                  = 0x00000100,
 124         I40E_DEBUG_FLOW                 = 0x00000200,
 125         I40E_DEBUG_DCB                  = 0x00000400,
 126         I40E_DEBUG_DIAG                 = 0x00000800,
 127         I40E_DEBUG_FD                   = 0x00001000,
 128
 129         I40E_DEBUG_IWARP                = 0x00F00000,
 130
 131         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 132         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 133         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 134         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 135         I40E_DEBUG_AQ                   = 0x0F000000,
 136
 137         I40E_DEBUG_USER                 = 0xF0000000,
 138
 139         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 140 };
 141
 142 /* PCI Bus Info */
 143 #define I40E_PCI_LINK_STATUS            0xB2
 144 #define I40E_PCI_LINK_WIDTH             0x3F0
 145 #define I40E_PCI_LINK_WIDTH_1           0x10
 146 #define I40E_PCI_LINK_WIDTH_2           0x20
 147 #define I40E_PCI_LINK_WIDTH_4           0x40
 148 #define I40E_PCI_LINK_WIDTH_8           0x80
 149 #define I40E_PCI_LINK_SPEED             0xF
 150 #define I40E_PCI_LINK_SPEED_2500        0x1
 151 #define I40E_PCI_LINK_SPEED_5000        0x2
 152 #define I40E_PCI_LINK_SPEED_8000        0x3
 153
 154 #define I40E_MDIO_CLAUSE22_STCODE_MASK  I40E_MASK(1, \
 155                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 156 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_MASK(1, \
 157                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 158 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_MASK(2, \
 159                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 160
 161 #define I40E_MDIO_CLAUSE45_STCODE_MASK  I40E_MASK(0, \
 162                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 163 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_MASK(0, \
 164                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 165 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_MASK(1, \
 166                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 167 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    I40E_MASK(2, \
 168                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 169 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_MASK(3, \
 170                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 171
 172 #define I40E_PHY_COM_REG_PAGE                   0x1E
 173 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 174 #define I40E_PHY_LED_MANUAL_ON                  0x100
 175 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 176 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 177 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 178
 179 /* Memory types */
 180 enum i40e_memset_type {
 181         I40E_NONDMA_MEM = 0,
 182         I40E_DMA_MEM
 183 };
 184
 185 /* Memcpy types */
 186 enum i40e_memcpy_type {
 187         I40E_NONDMA_TO_NONDMA = 0,
 188         I40E_NONDMA_TO_DMA,
 189         I40E_DMA_TO_DMA,
 190         I40E_DMA_TO_NONDMA
 191 };
 192
 193 /* These are structs for managing the hardware information and the operations.
 194  * The structures of function pointers are filled out at init time when we
 195  * know for sure exactly which hardware we're working with.  This gives us the
 196  * flexibility of using the same main driver code but adapting to slightly
 197  * different hardware needs as new parts are developed.  For this architecture,
 198  * the Firmware and AdminQ are intended to insulate the driver from most of the
 199  * future changes, but these structures will also do part of the job.
 200  */
 201 enum i40e_mac_type {
 202         I40E_MAC_UNKNOWN = 0,
 203         I40E_MAC_XL710,
 204         I40E_MAC_VF,
 205         I40E_MAC_X722,
 206         I40E_MAC_X722_VF,
 207         I40E_MAC_GENERIC,
 208 };
 209
 210 enum i40e_media_type {
 211         I40E_MEDIA_TYPE_UNKNOWN = 0,
 212         I40E_MEDIA_TYPE_FIBER,
 213         I40E_MEDIA_TYPE_BASET,
 214         I40E_MEDIA_TYPE_BACKPLANE,
 215         I40E_MEDIA_TYPE_CX4,
 216         I40E_MEDIA_TYPE_DA,
 217         I40E_MEDIA_TYPE_VIRTUAL
 218 };
 219
 220 enum i40e_fc_mode {
 221         I40E_FC_NONE = 0,
 222         I40E_FC_RX_PAUSE,
 223         I40E_FC_TX_PAUSE,
 224         I40E_FC_FULL,
 225         I40E_FC_PFC,
 226         I40E_FC_DEFAULT
 227 };
 228
 229 enum i40e_set_fc_aq_failures {
 230         I40E_SET_FC_AQ_FAIL_NONE = 0,
 231         I40E_SET_FC_AQ_FAIL_GET = 1,
 232         I40E_SET_FC_AQ_FAIL_SET = 2,
 233         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 234         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 235 };
 236
 237 enum i40e_vsi_type {
 238         I40E_VSI_MAIN   = 0,
 239         I40E_VSI_VMDQ1  = 1,
 240         I40E_VSI_VMDQ2  = 2,
 241         I40E_VSI_CTRL   = 3,
 242         I40E_VSI_FCOE   = 4,
 243         I40E_VSI_MIRROR = 5,
 244         I40E_VSI_SRIOV  = 6,
 245         I40E_VSI_FDIR   = 7,
 246         I40E_VSI_IWARP  = 8,
 247         I40E_VSI_TYPE_UNKNOWN
 248 };
 249
 250 enum i40e_queue_type {
 251         I40E_QUEUE_TYPE_RX = 0,
 252         I40E_QUEUE_TYPE_TX,
 253         I40E_QUEUE_TYPE_PE_CEQ,
 254         I40E_QUEUE_TYPE_UNKNOWN
 255 };
 256
 257 struct i40e_link_status {
 258         enum i40e_aq_phy_type phy_type;
 259         enum i40e_aq_link_speed link_speed;
 260         u8 link_info;
 261         u8 an_info;
 262         u8 req_fec_info;
 263         u8 fec_info;
 264         u8 ext_info;
 265         u8 loopback;
 266         /* is Link Status Event notification to SW enabled */
 267         bool lse_enable;
 268         u16 max_frame_size;
 269         bool crc_enable;
 270         u8 pacing;
 271         u8 requested_speeds;
 272         u8 module_type[3];
 273         /* 1st byte: module identifier */
 274 #define I40E_MODULE_TYPE_SFP            0x03
 275 #define I40E_MODULE_TYPE_QSFP           0x0D
 276         /* 2nd byte: ethernet compliance codes for 10/40G */
 277 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 278 #define I40E_MODULE_TYPE_40G_LR4        0x02
 279 #define I40E_MODULE_TYPE_40G_SR4        0x04
 280 #define I40E_MODULE_TYPE_40G_CR4        0x08
 281 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 282 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 283 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 284 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 285         /* 3rd byte: ethernet compliance codes for 1G */
 286 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 287 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 288 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 289 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 290 };
 291
 292 struct i40e_phy_info {
 293         struct i40e_link_status link_info;
 294         struct i40e_link_status link_info_old;
 295         bool get_link_info;
 296         enum i40e_media_type media_type;
 297         /* all the phy types the NVM is capable of */
 298         u64 phy_types;
 299 };
 300
 301 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 302 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 303 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 304 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 305 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 306 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 307 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 308 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 309 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 310 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 311 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 312 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 313 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 314 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 315 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 316 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 317 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 318 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 319 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 320 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 321 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 322 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 323 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 324 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 325 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 326 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 327 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 328                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 329 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 330 /*
 331  * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
 332  * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
 333  * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
 334  * a shift is needed to adjust for this with values larger than 31. The
 335  * only affected values are I40E_PHY_TYPE_25GBASE_*.
 336  */
 337 #define I40E_PHY_TYPE_OFFSET 1
 338 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
 339                                              I40E_PHY_TYPE_OFFSET)
 340 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
 341                                              I40E_PHY_TYPE_OFFSET)
 342 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
 343                                              I40E_PHY_TYPE_OFFSET)
 344 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
 345                                              I40E_PHY_TYPE_OFFSET)
 346 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
 347                                              I40E_PHY_TYPE_OFFSET)
 348 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
 349                                              I40E_PHY_TYPE_OFFSET)
 350 /* Offset for 2.5G/5G PHY Types value to bit number conversion */
 351 #define I40E_PHY_TYPE_OFFSET2 (-10)
 352 #define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \
 353                                              I40E_PHY_TYPE_OFFSET2)
 354 #define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \
 355                                              I40E_PHY_TYPE_OFFSET2)
 356 #define I40E_HW_CAP_MAX_GPIO                    30
 357 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 358 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 359
 360 enum i40e_acpi_programming_method {
 361         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 362         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 363 };
 364
 365 #define I40E_WOL_SUPPORT_MASK                   0x1
 366 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       0x2
 367 #define I40E_PROXY_SUPPORT_MASK                 0x4
 368
 369 /* Capabilities of a PF or a VF or the whole device */
 370 struct i40e_hw_capabilities {
 371         u32  switch_mode;
 372 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 373 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 374 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 375
 376         /* Cloud filter modes:
 377          * Mode1: Filter on L4 port only
 378          * Mode2: Filter for non-tunneled traffic
 379          * Mode3: Filter for tunnel traffic
 380          */
 381 #define I40E_CLOUD_FILTER_MODE1 0x6
 382 #define I40E_CLOUD_FILTER_MODE2 0x7
 383 #define I40E_CLOUD_FILTER_MODE3 0x8
 384 #define I40E_SWITCH_MODE_MASK   0xF
 385
 386         u32  management_mode;
 387         u32  mng_protocols_over_mctp;
 388 #define I40E_MNG_PROTOCOL_PLDM          0x2
 389 #define I40E_MNG_PROTOCOL_OEM_COMMANDS  0x4
 390 #define I40E_MNG_PROTOCOL_NCSI          0x8
 391         u32  npar_enable;
 392         u32  os2bmc;
 393         u32  valid_functions;
 394         bool sr_iov_1_1;
 395         bool vmdq;
 396         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 397         bool evb_802_1_qbh; /* Bridge Port Extension */
 398         bool dcb;
 399         bool fcoe;
 400         bool iscsi; /* Indicates iSCSI enabled */
 401         bool flex10_enable;
 402         bool flex10_capable;
 403         u32  flex10_mode;
 404 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 405 #define I40E_FLEX10_MODE_DCC            0x1
 406 #define I40E_FLEX10_MODE_DCI            0x2
 407
 408         u32 flex10_status;
 409 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 410 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 411
 412         bool sec_rev_disabled;
 413         bool update_disabled;
 414 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 415 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 416
 417         bool mgmt_cem;
 418         bool ieee_1588;
 419         bool iwarp;
 420         bool fd;
 421         u32 fd_filters_guaranteed;
 422         u32 fd_filters_best_effort;
 423         bool rss;
 424         u32 rss_table_size;
 425         u32 rss_table_entry_width;
 426         bool led[I40E_HW_CAP_MAX_GPIO];
 427         bool sdp[I40E_HW_CAP_MAX_GPIO];
 428         u32 nvm_image_type;
 429         u32 num_flow_director_filters;
 430         u32 num_vfs;
 431         u32 vf_base_id;
 432         u32 num_vsis;
 433         u32 num_rx_qp;
 434         u32 num_tx_qp;
 435         u32 base_queue;
 436         u32 num_msix_vectors;
 437         u32 num_msix_vectors_vf;
 438         u32 led_pin_num;
 439         u32 sdp_pin_num;
 440         u32 mdio_port_num;
 441         u32 mdio_port_mode;
 442         u8 rx_buf_chain_len;
 443         u32 enabled_tcmap;
 444         u32 maxtc;
 445         u64 wr_csr_prot;
 446         bool apm_wol_support;
 447         enum i40e_acpi_programming_method acpi_prog_method;
 448         bool proxy_support;
 449 };
 450
 451 struct i40e_mac_info {
 452         enum i40e_mac_type type;
 453         u8 addr[ETH_ALEN];
 454         u8 perm_addr[ETH_ALEN];
 455         u8 san_addr[ETH_ALEN];
 456         u8 port_addr[ETH_ALEN];
 457         u16 max_fcoeq;
 458 };
 459
 460 enum i40e_aq_resources_ids {
 461         I40E_NVM_RESOURCE_ID = 1
 462 };
 463
 464 enum i40e_aq_resource_access_type {
 465         I40E_RESOURCE_READ = 1,
 466         I40E_RESOURCE_WRITE
 467 };
 468
 469 struct i40e_nvm_info {
 470         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 471         u32 timeout;              /* [ms] */
 472         u16 sr_size;              /* Shadow RAM size in words */
 473         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 474         u16 version;              /* NVM package version */
 475         u32 eetrack;              /* NVM data version */
 476         u32 oem_ver;              /* OEM version info */
 477 };
 478
 479 /* definitions used in NVM update support */
 480
 481 enum i40e_nvmupd_cmd {
 482         I40E_NVMUPD_INVALID,
 483         I40E_NVMUPD_READ_CON,
 484         I40E_NVMUPD_READ_SNT,
 485         I40E_NVMUPD_READ_LCB,
 486         I40E_NVMUPD_READ_SA,
 487         I40E_NVMUPD_WRITE_ERA,
 488         I40E_NVMUPD_WRITE_CON,
 489         I40E_NVMUPD_WRITE_SNT,
 490         I40E_NVMUPD_WRITE_LCB,
 491         I40E_NVMUPD_WRITE_SA,
 492         I40E_NVMUPD_CSUM_CON,
 493         I40E_NVMUPD_CSUM_SA,
 494         I40E_NVMUPD_CSUM_LCB,
 495         I40E_NVMUPD_STATUS,
 496         I40E_NVMUPD_EXEC_AQ,
 497         I40E_NVMUPD_GET_AQ_RESULT,
 498         I40E_NVMUPD_GET_AQ_EVENT,
 499         I40E_NVMUPD_FEATURES,
 500 };
 501
 502 enum i40e_nvmupd_state {
 503         I40E_NVMUPD_STATE_INIT,
 504         I40E_NVMUPD_STATE_READING,
 505         I40E_NVMUPD_STATE_WRITING,
 506         I40E_NVMUPD_STATE_INIT_WAIT,
 507         I40E_NVMUPD_STATE_WRITE_WAIT,
 508         I40E_NVMUPD_STATE_ERROR
 509 };
 510
 511 /* nvm_access definition and its masks/shifts need to be accessible to
 512  * application, core driver, and shared code.  Where is the right file?
 513  */
 514 #define I40E_NVM_READ   0xB
 515 #define I40E_NVM_WRITE  0xC
 516
 517 #define I40E_NVM_MOD_PNT_MASK 0xFF
 518
 519 #define I40E_NVM_TRANS_SHIFT                    8
 520 #define I40E_NVM_TRANS_MASK                     (0xf << I40E_NVM_TRANS_SHIFT)
 521 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT       12
 522 #define I40E_NVM_PRESERVATION_FLAGS_MASK \
 523                                 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
 524 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED    0x01
 525 #define I40E_NVM_PRESERVATION_FLAGS_ALL         0x02
 526 #define I40E_NVM_CON                            0x0
 527 #define I40E_NVM_SNT                            0x1
 528 #define I40E_NVM_LCB                            0x2
 529 #define I40E_NVM_SA                             (I40E_NVM_SNT | I40E_NVM_LCB)
 530 #define I40E_NVM_ERA                            0x4
 531 #define I40E_NVM_CSUM                           0x8
 532 #define I40E_NVM_AQE                            0xe
 533 #define I40E_NVM_EXEC                           0xf
 534
 535 #define I40E_NVM_EXEC_GET_AQ_RESULT             0x0
 536 #define I40E_NVM_EXEC_FEATURES                  0xe
 537 #define I40E_NVM_EXEC_STATUS                    0xf
 538
 539 #define I40E_NVM_ADAPT_SHIFT    16
 540 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 541
 542 #define I40E_NVMUPD_MAX_DATA    4096
 543 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 544
 545 struct i40e_nvm_access {
 546         u32 command;
 547         u32 config;
 548         u32 offset;     /* in bytes */
 549         u32 data_size;  /* in bytes */
 550         u8 data[1];
 551 };
 552
 553 /* NVMUpdate features API */
 554 #define I40E_NVMUPD_FEATURES_API_VER_MAJOR              0
 555 #define I40E_NVMUPD_FEATURES_API_VER_MINOR              14
 556 #define I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN     12
 557
 558 #define I40E_NVMUPD_FEATURE_FLAT_NVM_SUPPORT            BIT(0)
 559
 560 struct i40e_nvmupd_features {
 561         u8 major;
 562         u8 minor;
 563         u16 size;
 564         u8 features[I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN];
 565 };
 566
 567 /* (Q)SFP module access definitions */
 568 #define I40E_I2C_EEPROM_DEV_ADDR        0xA0
 569 #define I40E_I2C_EEPROM_DEV_ADDR2       0xA2
 570 #define I40E_MODULE_TYPE_ADDR           0x00
 571 #define I40E_MODULE_REVISION_ADDR       0x01
 572 #define I40E_MODULE_SFF_8472_COMP       0x5E
 573 #define I40E_MODULE_SFF_8472_SWAP       0x5C
 574 #define I40E_MODULE_SFF_ADDR_MODE       0x04
 575 #define I40E_MODULE_SFF_DIAG_CAPAB      0x40
 576 #define I40E_MODULE_TYPE_QSFP_PLUS      0x0D
 577 #define I40E_MODULE_TYPE_QSFP28         0x11
 578 #define I40E_MODULE_QSFP_MAX_LEN        640
 579
 580 /* PCI bus types */
 581 enum i40e_bus_type {
 582         i40e_bus_type_unknown = 0,
 583         i40e_bus_type_pci,
 584         i40e_bus_type_pcix,
 585         i40e_bus_type_pci_express,
 586         i40e_bus_type_reserved
 587 };
 588
 589 /* PCI bus speeds */
 590 enum i40e_bus_speed {
 591         i40e_bus_speed_unknown  = 0,
 592         i40e_bus_speed_33       = 33,
 593         i40e_bus_speed_66       = 66,
 594         i40e_bus_speed_100      = 100,
 595         i40e_bus_speed_120      = 120,
 596         i40e_bus_speed_133      = 133,
 597         i40e_bus_speed_2500     = 2500,
 598         i40e_bus_speed_5000     = 5000,
 599         i40e_bus_speed_8000     = 8000,
 600         i40e_bus_speed_reserved
 601 };
 602
 603 /* PCI bus widths */
 604 enum i40e_bus_width {
 605         i40e_bus_width_unknown  = 0,
 606         i40e_bus_width_pcie_x1  = 1,
 607         i40e_bus_width_pcie_x2  = 2,
 608         i40e_bus_width_pcie_x4  = 4,
 609         i40e_bus_width_pcie_x8  = 8,
 610         i40e_bus_width_32       = 32,
 611         i40e_bus_width_64       = 64,
 612         i40e_bus_width_reserved
 613 };
 614
 615 /* Bus parameters */
 616 struct i40e_bus_info {
 617         enum i40e_bus_speed speed;
 618         enum i40e_bus_width width;
 619         enum i40e_bus_type type;
 620
 621         u16 func;
 622         u16 device;
 623         u16 lan_id;
 624         u16 bus_id;
 625 };
 626
 627 /* Flow control (FC) parameters */
 628 struct i40e_fc_info {
 629         enum i40e_fc_mode current_mode; /* FC mode in effect */
 630         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 631 };
 632
 633 #define I40E_MAX_TRAFFIC_CLASS          8
 634 #define I40E_MAX_USER_PRIORITY          8
 635 #define I40E_DCBX_MAX_APPS              32
 636 #define I40E_LLDPDU_SIZE                1500
 637 #define I40E_TLV_STATUS_OPER            0x1
 638 #define I40E_TLV_STATUS_SYNC            0x2
 639 #define I40E_TLV_STATUS_ERR             0x4
 640 #define I40E_CEE_OPER_MAX_APPS          3
 641 #define I40E_APP_PROTOID_FCOE           0x8906
 642 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 643 #define I40E_APP_PROTOID_FIP            0x8914
 644 #define I40E_APP_SEL_ETHTYPE            0x1
 645 #define I40E_APP_SEL_TCPIP              0x2
 646 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 647 #define I40E_CEE_APP_SEL_TCPIP          0x1
 648
 649 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 650 struct i40e_dcb_ets_config {
 651         u8 willing;
 652         u8 cbs;
 653         u8 maxtcs;
 654         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 655         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 656         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 657 };
 658
 659 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 660 struct i40e_dcb_pfc_config {
 661         u8 willing;
 662         u8 mbc;
 663         u8 pfccap;
 664         u8 pfcenable;
 665 };
 666
 667 /* CEE or IEEE 802.1Qaz Application Priority data */
 668 struct i40e_dcb_app_priority_table {
 669         u8  priority;
 670         u8  selector;
 671         u16 protocolid;
 672 };
 673
 674 struct i40e_dcbx_config {
 675         u8  dcbx_mode;
 676 #define I40E_DCBX_MODE_CEE      0x1
 677 #define I40E_DCBX_MODE_IEEE     0x2
 678         u8  app_mode;
 679 #define I40E_DCBX_APPS_NON_WILLING      0x1
 680         u32 numapps;
 681         u32 tlv_status; /* CEE mode TLV status */
 682         struct i40e_dcb_ets_config etscfg;
 683         struct i40e_dcb_ets_config etsrec;
 684         struct i40e_dcb_pfc_config pfc;
 685         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 686 };
 687
 688 /* Port hardware description */
 689 struct i40e_hw {
 690         u8 *hw_addr;
 691         void *back;
 692
 693         /* subsystem structs */
 694         struct i40e_phy_info phy;
 695         struct i40e_mac_info mac;
 696         struct i40e_bus_info bus;
 697         struct i40e_nvm_info nvm;
 698         struct i40e_fc_info fc;
 699
 700         /* pci info */
 701         u16 device_id;
 702         u16 vendor_id;
 703         u16 subsystem_device_id;
 704         u16 subsystem_vendor_id;
 705         u8 revision_id;
 706         u8 port;
 707         bool adapter_stopped;
 708
 709         /* capabilities for entire device and PCI func */
 710         struct i40e_hw_capabilities dev_caps;
 711         struct i40e_hw_capabilities func_caps;
 712
 713         /* Flow Director shared filter space */
 714         u16 fdir_shared_filter_count;
 715
 716         /* device profile info */
 717         u8  pf_id;
 718         u16 main_vsi_seid;
 719
 720         /* for multi-function MACs */
 721         u16 partition_id;
 722         u16 num_partitions;
 723         u16 num_ports;
 724
 725         /* Closest numa node to the device */
 726         u16 numa_node;
 727
 728         /* Admin Queue info */
 729         struct i40e_adminq_info aq;
 730
 731         /* state of nvm update process */
 732         enum i40e_nvmupd_state nvmupd_state;
 733         struct i40e_aq_desc nvm_wb_desc;
 734         struct i40e_aq_desc nvm_aq_event_desc;
 735         struct i40e_virt_mem nvm_buff;
 736         bool nvm_release_on_done;
 737         u16 nvm_wait_opcode;
 738
 739         /* HMC info */
 740         struct i40e_hmc_info hmc; /* HMC info struct */
 741
 742         /* LLDP/DCBX Status */
 743         u16 dcbx_status;
 744
 745         /* DCBX info */
 746         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 747         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 748         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 749
 750         /* WoL and proxy support */
 751         u16 num_wol_proxy_filters;
 752         u16 wol_proxy_vsi_seid;
 753
 754 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 755 #define I40E_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)
 756 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
 757 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
 758 #define I40E_HW_FLAG_FW_LLDP_STOPPABLE      BIT_ULL(4)
 759 #define I40E_HW_FLAG_FW_LLDP_PERSISTENT     BIT_ULL(5)
 760 #define I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED BIT_ULL(6)
 761 #define I40E_HW_FLAG_DROP_MODE              BIT_ULL(7)
 762 #define I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE BIT_ULL(8)
 763         u64 flags;
 764
 765         /* Used in set switch config AQ command */
 766         u16 switch_tag;
 767         u16 first_tag;
 768         u16 second_tag;
 769
 770         /* NVMUpdate features */
 771         struct i40e_nvmupd_features nvmupd_features;
 772
 773         /* debug mask */
 774         u32 debug_mask;
 775         char err_str[16];
 776 };
 777
 778 static INLINE bool i40e_is_vf(struct i40e_hw *hw)
 779 {
 780         return (hw->mac.type == I40E_MAC_VF ||
 781                 hw->mac.type == I40E_MAC_X722_VF);
 782 }
 783
 784 struct i40e_driver_version {
 785         u8 major_version;
 786         u8 minor_version;
 787         u8 build_version;
 788         u8 subbuild_version;
 789         u8 driver_string[32];
 790 };
 791
 792 /* RX Descriptors */
 793 union i40e_16byte_rx_desc {
 794         struct {
 795                 __le64 pkt_addr; /* Packet buffer address */
 796                 __le64 hdr_addr; /* Header buffer address */
 797         } read;
 798         struct {
 799                 struct {
 800                         struct {
 801                                 union {
 802                                         __le16 mirroring_status;
 803                                         __le16 fcoe_ctx_id;
 804                                 } mirr_fcoe;
 805                                 __le16 l2tag1;
 806                         } lo_dword;
 807                         union {
 808                                 __le32 rss; /* RSS Hash */
 809                                 __le32 fd_id; /* Flow director filter id */
 810                                 __le32 fcoe_param; /* FCoE DDP Context id */
 811                         } hi_dword;
 812                 } qword0;
 813                 struct {
 814                         /* ext status/error/pktype/length */
 815                         __le64 status_error_len;
 816                 } qword1;
 817         } wb;  /* writeback */
 818 };
 819
 820 union i40e_32byte_rx_desc {
 821         struct {
 822                 __le64  pkt_addr; /* Packet buffer address */
 823                 __le64  hdr_addr; /* Header buffer address */
 824                         /* bit 0 of hdr_buffer_addr is DD bit */
 825                 __le64  rsvd1;
 826                 __le64  rsvd2;
 827         } read;
 828         struct {
 829                 struct {
 830                         struct {
 831                                 union {
 832                                         __le16 mirroring_status;
 833                                         __le16 fcoe_ctx_id;
 834                                 } mirr_fcoe;
 835                                 __le16 l2tag1;
 836                         } lo_dword;
 837                         union {
 838                                 __le32 rss; /* RSS Hash */
 839                                 __le32 fcoe_param; /* FCoE DDP Context id */
 840                                 /* Flow director filter id in case of
 841                                  * Programming status desc WB
 842                                  */
 843                                 __le32 fd_id;
 844                         } hi_dword;
 845                 } qword0;
 846                 struct {
 847                         /* status/error/pktype/length */
 848                         __le64 status_error_len;
 849                 } qword1;
 850                 struct {
 851                         __le16 ext_status; /* extended status */
 852                         __le16 rsvd;
 853                         __le16 l2tag2_1;
 854                         __le16 l2tag2_2;
 855                 } qword2;
 856                 struct {
 857                         union {
 858                                 __le32 flex_bytes_lo;
 859                                 __le32 pe_status;
 860                         } lo_dword;
 861                         union {
 862                                 __le32 flex_bytes_hi;
 863                                 __le32 fd_id;
 864                         } hi_dword;
 865                 } qword3;
 866         } wb;  /* writeback */
 867 };
 868
 869 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 870 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 871                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 872 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 873 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 874                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 875
 876 enum i40e_rx_desc_status_bits {
 877         /* Note: These are predefined bit offsets */
 878         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 879         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 880         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 881         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 882         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 883         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 884         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 885         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 886
 887         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 888         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 889         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 890         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 891         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 892         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 893         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 894         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 895 };
 896
 897 #define I40E_RXD_QW1_STATUS_SHIFT       0
 898 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 899                                          I40E_RXD_QW1_STATUS_SHIFT)
 900
 901 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 902 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 903                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 904
 905 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 906 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 907
 908 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 909 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 910                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 911
 912 enum i40e_rx_desc_fltstat_values {
 913         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 914         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 915         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 916         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 917 };
 918
 919 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 920 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 921 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 922 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 923
 924 #define I40E_RXD_QW1_ERROR_SHIFT        19
 925 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 926
 927 enum i40e_rx_desc_error_bits {
 928         /* Note: These are predefined bit offsets */
 929         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 930         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 931         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 932         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 933         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 934         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 935         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 936         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 937         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 938 };
 939
 940 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 941         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 942         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 943         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 944         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 945         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 946 };
 947
 948 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 949 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 950
 951 /* Packet type non-ip values */
 952 enum i40e_rx_l2_ptype {
 953         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 954         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 955         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 956         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 957         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 958         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 959         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 960         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 961         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 962         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 963         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 964         I40E_RX_PTYPE_L2_ARP                            = 11,
 965         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 966         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 967         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 968         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 969         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 970         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 971         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 972         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 973         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 974         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 975         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 976         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 977         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 978         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 979 };
 980
 981 struct i40e_rx_ptype_decoded {
 982         u32 ptype:8;
 983         u32 known:1;
 984         u32 outer_ip:1;
 985         u32 outer_ip_ver:1;
 986         u32 outer_frag:1;
 987         u32 tunnel_type:3;
 988         u32 tunnel_end_prot:2;
 989         u32 tunnel_end_frag:1;
 990         u32 inner_prot:4;
 991         u32 payload_layer:3;
 992 };
 993
 994 enum i40e_rx_ptype_outer_ip {
 995         I40E_RX_PTYPE_OUTER_L2  = 0,
 996         I40E_RX_PTYPE_OUTER_IP  = 1
 997 };
 998
 999 enum i40e_rx_ptype_outer_ip_ver {
1000         I40E_RX_PTYPE_OUTER_NONE        = 0,
1001         I40E_RX_PTYPE_OUTER_IPV4        = 0,
1002         I40E_RX_PTYPE_OUTER_IPV6        = 1
1003 };
1004
1005 enum i40e_rx_ptype_outer_fragmented {
1006         I40E_RX_PTYPE_NOT_FRAG  = 0,
1007         I40E_RX_PTYPE_FRAG      = 1
1008 };
1009
1010 enum i40e_rx_ptype_tunnel_type {
1011         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
1012         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
1013         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
1014         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
1015         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
1016 };
1017
1018 enum i40e_rx_ptype_tunnel_end_prot {
1019         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
1020         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
1021         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
1022 };
1023
1024 enum i40e_rx_ptype_inner_prot {
1025         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
1026         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
1027         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
1028         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
1029         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
1030         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
1031 };
1032
1033 enum i40e_rx_ptype_payload_layer {
1034         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
1035         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
1036         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
1037         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
1038 };
1039
1040 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
1041 #define I40E_RX_PTYPE_SHIFT             56
1042
1043 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
1044 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
1045                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
1046
1047 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
1048 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
1049                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
1050
1051 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
1052 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
1053
1054 #define I40E_RXD_QW1_NEXTP_SHIFT        38
1055 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
1056
1057 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
1058 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
1059                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
1060
1061 enum i40e_rx_desc_ext_status_bits {
1062         /* Note: These are predefined bit offsets */
1063         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
1064         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
1065         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
1066         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
1067         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
1068         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1069         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
1070 };
1071
1072 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
1073 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1074
1075 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
1076 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1077
1078 enum i40e_rx_desc_pe_status_bits {
1079         /* Note: These are predefined bit offsets */
1080         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1081         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1082         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1083         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1084         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1085         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1086         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1087         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1088         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1089 };
1090
1091 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1092 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1093
1094 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1095 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1096                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1097
1098 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1099 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1100                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1101
1102 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1103 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1104                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1105
1106 enum i40e_rx_prog_status_desc_status_bits {
1107         /* Note: These are predefined bit offsets */
1108         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1109         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1110 };
1111
1112 enum i40e_rx_prog_status_desc_prog_id_masks {
1113         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1114         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1115         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1116 };
1117
1118 enum i40e_rx_prog_status_desc_error_bits {
1119         /* Note: These are predefined bit offsets */
1120         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1121         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1122         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1123         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1124 };
1125
1126 #define I40E_TWO_BIT_MASK       0x3
1127 #define I40E_THREE_BIT_MASK     0x7
1128 #define I40E_FOUR_BIT_MASK      0xF
1129 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1130
1131 /* TX Descriptor */
1132 struct i40e_tx_desc {
1133         __le64 buffer_addr; /* Address of descriptor's data buf */
1134         __le64 cmd_type_offset_bsz;
1135 };
1136
1137 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1138 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1139
1140 enum i40e_tx_desc_dtype_value {
1141         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1142         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1143         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1144         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1145         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1146         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1147         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1148         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1149         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1150         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1151 };
1152
1153 #define I40E_TXD_QW1_CMD_SHIFT  4
1154 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1155
1156 enum i40e_tx_desc_cmd_bits {
1157         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1158         I40E_TX_DESC_CMD_RS                     = 0x0002,
1159         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1160         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1161         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1162         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1163         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1164         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1165         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1166         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1167         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1168         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1169         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1170         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1171         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1172         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1173         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1174         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1175 };
1176
1177 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1178 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1179                                          I40E_TXD_QW1_OFFSET_SHIFT)
1180
1181 enum i40e_tx_desc_length_fields {
1182         /* Note: These are predefined bit offsets */
1183         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1184         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1185         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1186 };
1187
1188 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1189 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1190 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1191 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1192
1193 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1194 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1195                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1196
1197 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1198 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1199
1200 /* Context descriptors */
1201 struct i40e_tx_context_desc {
1202         __le32 tunneling_params;
1203         __le16 l2tag2;
1204         __le16 rsvd;
1205         __le64 type_cmd_tso_mss;
1206 };
1207
1208 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1209 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1210
1211 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1212 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1213
1214 enum i40e_tx_ctx_desc_cmd_bits {
1215         I40E_TX_CTX_DESC_TSO            = 0x01,
1216         I40E_TX_CTX_DESC_TSYN           = 0x02,
1217         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1218         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1219         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1220         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1221         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1222         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1223         I40E_TX_CTX_DESC_SWPE           = 0x40
1224 };
1225
1226 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1227 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1228                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1229
1230 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1231 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1232                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1233
1234 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1235 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1236
1237 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1238 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1239                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1240
1241 enum i40e_tx_ctx_desc_eipt_offload {
1242         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1243         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1244         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1245         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1246 };
1247
1248 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1249 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1250                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1251
1252 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1253 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1254
1255 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1256 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1257
1258 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1259 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1260
1261 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1262
1263 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1264 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1265                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1266
1267 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1268 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1269                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1270
1271 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1272 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1273 struct i40e_nop_desc {
1274         __le64 rsvd;
1275         __le64 dtype_cmd;
1276 };
1277
1278 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1279 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1280
1281 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1282 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1283
1284 enum i40e_tx_nop_desc_cmd_bits {
1285         /* Note: These are predefined bit offsets */
1286         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1287         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1288         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1289 };
1290
1291 struct i40e_filter_program_desc {
1292         __le32 qindex_flex_ptype_vsi;
1293         __le32 rsvd;
1294         __le32 dtype_cmd_cntindex;
1295         __le32 fd_id;
1296 };
1297 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1298 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1299                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1300 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1301 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1302                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1303 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1304 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1305                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1306
1307 /* Packet Classifier Types for filters */
1308 enum i40e_filter_pctype {
1309         /* Note: Values 0-28 are reserved for future use.
1310          * Value 29, 30, 32 are not supported on XL710 and X710.
1311          */
1312         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1313         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1314         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1315         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1316         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1317         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1318         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1319         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1320         /* Note: Values 37-38 are reserved for future use.
1321          * Value 39, 40, 42 are not supported on XL710 and X710.
1322          */
1323         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1324         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1325         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1326         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1327         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1328         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1329         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1330         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1331         /* Note: Value 47 is reserved for future use */
1332         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1333         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1334         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1335         /* Note: Values 51-62 are reserved for future use */
1336         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1337 };
1338
1339 enum i40e_filter_program_desc_dest {
1340         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1341         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1342         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1343 };
1344
1345 enum i40e_filter_program_desc_fd_status {
1346         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1347         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1348         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1349         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1350 };
1351
1352 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1353 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1354                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1355
1356 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1357 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1358
1359 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1360 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1361                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1362
1363 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1364 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1365
1366 enum i40e_filter_program_desc_pcmd {
1367         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1368         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1369 };
1370
1371 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1372 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1373
1374 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1375 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1376
1377 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1378                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1379 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1380                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1381
1382 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1383                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1384 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1385
1386 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1387 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1388                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1389
1390 enum i40e_filter_type {
1391         I40E_FLOW_DIRECTOR_FLTR = 0,
1392         I40E_PE_QUAD_HASH_FLTR = 1,
1393         I40E_ETHERTYPE_FLTR,
1394         I40E_FCOE_CTX_FLTR,
1395         I40E_MAC_VLAN_FLTR,
1396         I40E_HASH_FLTR
1397 };
1398
1399 struct i40e_vsi_context {
1400         u16 seid;
1401         u16 uplink_seid;
1402         u16 vsi_number;
1403         u16 vsis_allocated;
1404         u16 vsis_unallocated;
1405         u16 flags;
1406         u8 pf_num;
1407         u8 vf_num;
1408         u8 connection_type;
1409         struct i40e_aqc_vsi_properties_data info;
1410 };
1411
1412 struct i40e_veb_context {
1413         u16 seid;
1414         u16 uplink_seid;
1415         u16 veb_number;
1416         u16 vebs_allocated;
1417         u16 vebs_unallocated;
1418         u16 flags;
1419         struct i40e_aqc_get_veb_parameters_completion info;
1420 };
1421
1422 /* Statistics collected by each port, VSI, VEB, and S-channel */
1423 struct i40e_eth_stats {
1424         u64 rx_bytes;                   /* gorc */
1425         u64 rx_unicast;                 /* uprc */
1426         u64 rx_multicast;               /* mprc */
1427         u64 rx_broadcast;               /* bprc */
1428         u64 rx_discards;                /* rdpc */
1429         u64 rx_unknown_protocol;        /* rupp */
1430         u64 tx_bytes;                   /* gotc */
1431         u64 tx_unicast;                 /* uptc */
1432         u64 tx_multicast;               /* mptc */
1433         u64 tx_broadcast;               /* bptc */
1434         u64 tx_discards;                /* tdpc */
1435         u64 tx_errors;                  /* tepc */
1436 };
1437
1438 /* Statistics collected per VEB per TC */
1439 struct i40e_veb_tc_stats {
1440         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1441         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1442         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1443         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1444 };
1445
1446 /* Statistics collected by the MAC */
1447 struct i40e_hw_port_stats {
1448         /* eth stats collected by the port */
1449         struct i40e_eth_stats eth;
1450
1451         /* additional port specific stats */
1452         u64 tx_dropped_link_down;       /* tdold */
1453         u64 crc_errors;                 /* crcerrs */
1454         u64 illegal_bytes;              /* illerrc */
1455         u64 error_bytes;                /* errbc */
1456         u64 mac_local_faults;           /* mlfc */
1457         u64 mac_remote_faults;          /* mrfc */
1458         u64 rx_length_errors;           /* rlec */
1459         u64 link_xon_rx;                /* lxonrxc */
1460         u64 link_xoff_rx;               /* lxoffrxc */
1461         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1462         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1463         u64 link_xon_tx;                /* lxontxc */
1464         u64 link_xoff_tx;               /* lxofftxc */
1465         u64 priority_xon_tx[8];         /* pxontxc[8] */
1466         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1467         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1468         u64 rx_size_64;                 /* prc64 */
1469         u64 rx_size_127;                /* prc127 */
1470         u64 rx_size_255;                /* prc255 */
1471         u64 rx_size_511;                /* prc511 */
1472         u64 rx_size_1023;               /* prc1023 */
1473         u64 rx_size_1522;               /* prc1522 */
1474         u64 rx_size_big;                /* prc9522 */
1475         u64 rx_undersize;               /* ruc */
1476         u64 rx_fragments;               /* rfc */
1477         u64 rx_oversize;                /* roc */
1478         u64 rx_jabber;                  /* rjc */
1479         u64 tx_size_64;                 /* ptc64 */
1480         u64 tx_size_127;                /* ptc127 */
1481         u64 tx_size_255;                /* ptc255 */
1482         u64 tx_size_511;                /* ptc511 */
1483         u64 tx_size_1023;               /* ptc1023 */
1484         u64 tx_size_1522;               /* ptc1522 */
1485         u64 tx_size_big;                /* ptc9522 */
1486         u64 mac_short_packet_dropped;   /* mspdc */
1487         u64 checksum_error;             /* xec */
1488         /* flow director stats */
1489         u64 fd_atr_match;
1490         u64 fd_sb_match;
1491         u64 fd_atr_tunnel_match;
1492         u32 fd_atr_status;
1493         u32 fd_sb_status;
1494         /* EEE LPI */
1495         u32 tx_lpi_status;
1496         u32 rx_lpi_status;
1497         u64 tx_lpi_count;               /* etlpic */
1498         u64 rx_lpi_count;               /* erlpic */
1499         u64 tx_lpi_duration;
1500         u64 rx_lpi_duration;
1501 };
1502
1503 /* Checksum and Shadow RAM pointers */
1504 #define I40E_SR_NVM_CONTROL_WORD                0x00
1505 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1506 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1507 #define I40E_SR_OPTION_ROM_PTR                  0x05
1508 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1509 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1510 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1511 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1512 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1513 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1514 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1515 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1516 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1517 #define I40E_EMP_MODULE_PTR                     0x0F
1518 #define I40E_SR_EMP_MODULE_PTR                  0x48
1519 #define I40E_SR_PBA_FLAGS                       0x15
1520 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1521 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1522 #define I40E_NVM_OEM_VER_OFF                    0x83
1523 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1524 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1525 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1526 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1527 #define I40E_SR_NVM_MAP_VERSION                 0x29
1528 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1529 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1530 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1531 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1532 #define I40E_SR_VPD_PTR                         0x2F
1533 #define I40E_SR_PXE_SETUP_PTR                   0x30
1534 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1535 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1536 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1537 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1538 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1539 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1540 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1541 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1542 #define I40E_SR_PHY_ACTIVITY_LIST_PTR           0x3D
1543 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1544 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1545 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1546 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1547 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1548 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1549 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1550 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1551 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1552 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1553 #define I40E_SR_5TH_FREE_PROVISION_AREA_PTR     0x50
1554
1555 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1556 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1557 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1558 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1559 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1560 #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID   BIT(5)
1561 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE          BIT(12)
1562 #define I40E_PTR_TYPE                           BIT(15)
1563 #define I40E_SR_OCP_CFG_WORD0                   0x2B
1564 #define I40E_SR_OCP_ENABLED                     BIT(15)
1565
1566 /* Shadow RAM related */
1567 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1568 #define I40E_SR_BUF_ALIGNMENT           4096
1569 #define I40E_SR_WORDS_IN_1KB            512
1570 /* Checksum should be calculated such that after adding all the words,
1571  * including the checksum word itself, the sum should be 0xBABA.
1572  */
1573 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1574
1575 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1576
1577 enum i40e_switch_element_types {
1578         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1579         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1580         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1581         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1582         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1583         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1584         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1585         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1586         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1587 };
1588
1589 /* Supported EtherType filters */
1590 enum i40e_ether_type_index {
1591         I40E_ETHER_TYPE_1588            = 0,
1592         I40E_ETHER_TYPE_FIP             = 1,
1593         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1594         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1595         I40E_ETHER_TYPE_LLDP            = 4,
1596         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1597         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1598         I40E_ETHER_TYPE_QCN_CNM         = 7,
1599         I40E_ETHER_TYPE_8021X           = 8,
1600         I40E_ETHER_TYPE_ARP             = 9,
1601         I40E_ETHER_TYPE_RSV1            = 10,
1602         I40E_ETHER_TYPE_RSV2            = 11,
1603 };
1604
1605 /* Filter context base size is 1K */
1606 #define I40E_HASH_FILTER_BASE_SIZE      1024
1607 /* Supported Hash filter values */
1608 enum i40e_hash_filter_size {
1609         I40E_HASH_FILTER_SIZE_1K        = 0,
1610         I40E_HASH_FILTER_SIZE_2K        = 1,
1611         I40E_HASH_FILTER_SIZE_4K        = 2,
1612         I40E_HASH_FILTER_SIZE_8K        = 3,
1613         I40E_HASH_FILTER_SIZE_16K       = 4,
1614         I40E_HASH_FILTER_SIZE_32K       = 5,
1615         I40E_HASH_FILTER_SIZE_64K       = 6,
1616         I40E_HASH_FILTER_SIZE_128K      = 7,
1617         I40E_HASH_FILTER_SIZE_256K      = 8,
1618         I40E_HASH_FILTER_SIZE_512K      = 9,
1619         I40E_HASH_FILTER_SIZE_1M        = 10,
1620 };
1621
1622 /* DMA context base size is 0.5K */
1623 #define I40E_DMA_CNTX_BASE_SIZE         512
1624 /* Supported DMA context values */
1625 enum i40e_dma_cntx_size {
1626         I40E_DMA_CNTX_SIZE_512          = 0,
1627         I40E_DMA_CNTX_SIZE_1K           = 1,
1628         I40E_DMA_CNTX_SIZE_2K           = 2,
1629         I40E_DMA_CNTX_SIZE_4K           = 3,
1630         I40E_DMA_CNTX_SIZE_8K           = 4,
1631         I40E_DMA_CNTX_SIZE_16K          = 5,
1632         I40E_DMA_CNTX_SIZE_32K          = 6,
1633         I40E_DMA_CNTX_SIZE_64K          = 7,
1634         I40E_DMA_CNTX_SIZE_128K         = 8,
1635         I40E_DMA_CNTX_SIZE_256K         = 9,
1636 };
1637
1638 /* Supported Hash look up table (LUT) sizes */
1639 enum i40e_hash_lut_size {
1640         I40E_HASH_LUT_SIZE_128          = 0,
1641         I40E_HASH_LUT_SIZE_512          = 1,
1642 };
1643
1644 /* Structure to hold a per PF filter control settings */
1645 struct i40e_filter_control_settings {
1646         /* number of PE Quad Hash filter buckets */
1647         enum i40e_hash_filter_size pe_filt_num;
1648         /* number of PE Quad Hash contexts */
1649         enum i40e_dma_cntx_size pe_cntx_num;
1650         /* number of FCoE filter buckets */
1651         enum i40e_hash_filter_size fcoe_filt_num;
1652         /* number of FCoE DDP contexts */
1653         enum i40e_dma_cntx_size fcoe_cntx_num;
1654         /* size of the Hash LUT */
1655         enum i40e_hash_lut_size hash_lut_size;
1656         /* enable FDIR filters for PF and its VFs */
1657         bool enable_fdir;
1658         /* enable Ethertype filters for PF and its VFs */
1659         bool enable_ethtype;
1660         /* enable MAC/VLAN filters for PF and its VFs */
1661         bool enable_macvlan;
1662 };
1663
1664 /* Structure to hold device level control filter counts */
1665 struct i40e_control_filter_stats {
1666         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1667         u16 etype_used;       /* Used perfect EtherType filters */
1668         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1669         u16 etype_free;       /* Un-used perfect EtherType filters */
1670 };
1671
1672 enum i40e_reset_type {
1673         I40E_RESET_POR          = 0,
1674         I40E_RESET_CORER        = 1,
1675         I40E_RESET_GLOBR        = 2,
1676         I40E_RESET_EMPR         = 3,
1677 };
1678
1679 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1680 #define I40E_NVM_LLDP_CFG_PTR   0x06
1681 #define I40E_SR_LLDP_CFG_PTR    0x31
1682 struct i40e_lldp_variables {
1683         u16 length;
1684         u16 adminstatus;
1685         u16 msgfasttx;
1686         u16 msgtxinterval;
1687         u16 txparams;
1688         u16 timers;
1689         u16 crc8;
1690 };
1691
1692 /* Offsets into Alternate Ram */
1693 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1694 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1695 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1696 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1697 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1698 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1699
1700 /* Alternate Ram Bandwidth Masks */
1701 #define I40E_ALT_BW_VALUE_MASK          0xFF
1702 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1703 #define I40E_ALT_BW_VALID_MASK          0x80000000
1704
1705 /* RSS Hash Table Size */
1706 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1707
1708 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1709 #define I40E_L3_SRC_SHIFT               47
1710 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1711 #define I40E_L3_V6_SRC_SHIFT            43
1712 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1713 #define I40E_L3_DST_SHIFT               35
1714 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1715 #define I40E_L3_V6_DST_SHIFT            35
1716 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1717 #define I40E_L4_SRC_SHIFT               34
1718 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1719 #define I40E_L4_DST_SHIFT               33
1720 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1721 #define I40E_VERIFY_TAG_SHIFT           31
1722 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1723
1724 #define I40E_FLEX_50_SHIFT              13
1725 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1726 #define I40E_FLEX_51_SHIFT              12
1727 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1728 #define I40E_FLEX_52_SHIFT              11
1729 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1730 #define I40E_FLEX_53_SHIFT              10
1731 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1732 #define I40E_FLEX_54_SHIFT              9
1733 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1734 #define I40E_FLEX_55_SHIFT              8
1735 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1736 #define I40E_FLEX_56_SHIFT              7
1737 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1738 #define I40E_FLEX_57_SHIFT              6
1739 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1740 #define I40E_BCM_PHY_PCS_STATUS1_PAGE   0x3
1741 #define I40E_BCM_PHY_PCS_STATUS1_REG    0x0001
1742 #define I40E_BCM_PHY_PCS_STATUS1_RX_LPI BIT(8)
1743 #define I40E_BCM_PHY_PCS_STATUS1_TX_LPI BIT(9)
1744
1745 #endif /* _I40E_TYPE_H_ */