1 /******************************************************************************
3 Copyright (c) 2013-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
37 #define IXL_I2C_T_RISE 1
38 #define IXL_I2C_T_FALL 1
39 #define IXL_I2C_T_SU_DATA 1
40 #define IXL_I2C_T_SU_STA 5
41 #define IXL_I2C_T_SU_STO 4
42 #define IXL_I2C_T_HD_STA 4
43 #define IXL_I2C_T_LOW 5
44 #define IXL_I2C_T_HIGH 4
45 #define IXL_I2C_T_BUF 5
46 #define IXL_I2C_CLOCK_STRETCHING_TIMEOUT 500
48 #define IXL_I2C_REG(_hw) \
49 I40E_GLGEN_I2CPARAMS(((struct i40e_osdep *)(_hw)->back)->i2c_intfc_num)
52 static s32 ixl_set_i2c_data(struct ixl_pf *pf, u32 *i2cctl, bool data);
53 static bool ixl_get_i2c_data(struct ixl_pf *pf, u32 *i2cctl);
54 static void ixl_raise_i2c_clk(struct ixl_pf *pf, u32 *i2cctl);
55 static void ixl_lower_i2c_clk(struct ixl_pf *pf, u32 *i2cctl);
56 static s32 ixl_clock_out_i2c_bit(struct ixl_pf *pf, bool data);
57 static s32 ixl_get_i2c_ack(struct ixl_pf *pf);
58 static s32 ixl_clock_out_i2c_byte(struct ixl_pf *pf, u8 data);
59 static s32 ixl_clock_in_i2c_bit(struct ixl_pf *pf, bool *data);
60 static s32 ixl_clock_in_i2c_byte(struct ixl_pf *pf, u8 *data);
61 static void ixl_i2c_bus_clear(struct ixl_pf *pf);
62 static void ixl_i2c_start(struct ixl_pf *pf);
63 static void ixl_i2c_stop(struct ixl_pf *pf);
66 * ixl_i2c_bus_clear - Clears the I2C bus
67 * @hw: pointer to hardware structure
69 * Clears the I2C bus by sending nine clock pulses.
70 * Used when data line is stuck low.
73 ixl_i2c_bus_clear(struct ixl_pf *pf)
75 struct i40e_hw *hw = &pf->hw;
76 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
79 DEBUGFUNC("ixl_i2c_bus_clear");
83 ixl_set_i2c_data(pf, &i2cctl, 1);
85 for (i = 0; i < 9; i++) {
86 ixl_raise_i2c_clk(pf, &i2cctl);
88 /* Min high period of clock is 4us */
89 i40e_usec_delay(IXL_I2C_T_HIGH);
91 ixl_lower_i2c_clk(pf, &i2cctl);
93 /* Min low period of clock is 4.7us*/
94 i40e_usec_delay(IXL_I2C_T_LOW);
99 /* Put the i2c bus back to default state */
104 * ixl_i2c_stop - Sets I2C stop condition
105 * @hw: pointer to hardware structure
107 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
110 ixl_i2c_stop(struct ixl_pf *pf)
112 struct i40e_hw *hw = &pf->hw;
113 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
115 DEBUGFUNC("ixl_i2c_stop");
117 /* Stop condition must begin with data low and clock high */
118 ixl_set_i2c_data(pf, &i2cctl, 0);
119 ixl_raise_i2c_clk(pf, &i2cctl);
121 /* Setup time for stop condition (4us) */
122 i40e_usec_delay(IXL_I2C_T_SU_STO);
124 ixl_set_i2c_data(pf, &i2cctl, 1);
126 /* bus free time between stop and start (4.7us)*/
127 i40e_usec_delay(IXL_I2C_T_BUF);
131 * ixl_clock_in_i2c_byte - Clocks in one byte via I2C
132 * @hw: pointer to hardware structure
133 * @data: data byte to clock in
135 * Clocks in one byte data via I2C data/clock
138 ixl_clock_in_i2c_byte(struct ixl_pf *pf, u8 *data)
143 DEBUGFUNC("ixl_clock_in_i2c_byte");
145 for (i = 7; i >= 0; i--) {
146 ixl_clock_in_i2c_bit(pf, &bit);
154 * ixl_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
155 * @hw: pointer to hardware structure
156 * @data: read data value
158 * Clocks in one bit via I2C data/clock
161 ixl_clock_in_i2c_bit(struct ixl_pf *pf, bool *data)
163 struct i40e_hw *hw = &pf->hw;
164 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
166 DEBUGFUNC("ixl_clock_in_i2c_bit");
168 ixl_raise_i2c_clk(pf, &i2cctl);
170 /* Minimum high period of clock is 4us */
171 i40e_usec_delay(IXL_I2C_T_HIGH);
173 i2cctl = rd32(hw, IXL_I2C_REG(hw));
174 i2cctl |= I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK;
175 wr32(hw, IXL_I2C_REG(hw), i2cctl);
178 i2cctl = rd32(hw, IXL_I2C_REG(hw));
179 *data = ixl_get_i2c_data(pf, &i2cctl);
181 ixl_lower_i2c_clk(pf, &i2cctl);
183 /* Minimum low period of clock is 4.7 us */
184 i40e_usec_delay(IXL_I2C_T_LOW);
190 * ixl_get_i2c_ack - Polls for I2C ACK
191 * @hw: pointer to hardware structure
193 * Clocks in/out one bit via I2C data/clock
196 ixl_get_i2c_ack(struct ixl_pf *pf)
198 struct i40e_hw *hw = &pf->hw;
199 s32 status = I40E_SUCCESS;
201 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
205 ixl_raise_i2c_clk(pf, &i2cctl);
207 /* Minimum high period of clock is 4us */
208 i40e_usec_delay(IXL_I2C_T_HIGH);
210 i2cctl = rd32(hw, IXL_I2C_REG(hw));
211 i2cctl |= I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK;
212 wr32(hw, IXL_I2C_REG(hw), i2cctl);
215 /* Poll for ACK. Note that ACK in I2C spec is
216 * transition from 1 to 0 */
217 for (i = 0; i < timeout; i++) {
218 i2cctl = rd32(hw, IXL_I2C_REG(hw));
219 ack = ixl_get_i2c_data(pf, &i2cctl);
227 ixl_dbg(pf, IXL_DBG_I2C, "I2C ack was not received.\n");
228 status = I40E_ERR_PHY;
231 ixl_lower_i2c_clk(pf, &i2cctl);
233 /* Minimum low period of clock is 4.7 us */
234 i40e_usec_delay(IXL_I2C_T_LOW);
240 * ixl_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
241 * @hw: pointer to hardware structure
242 * @data: data value to write
244 * Clocks out one bit via I2C data/clock
247 ixl_clock_out_i2c_bit(struct ixl_pf *pf, bool data)
249 struct i40e_hw *hw = &pf->hw;
251 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
253 status = ixl_set_i2c_data(pf, &i2cctl, data);
254 if (status == I40E_SUCCESS) {
255 ixl_raise_i2c_clk(pf, &i2cctl);
257 /* Minimum high period of clock is 4us */
258 i40e_usec_delay(IXL_I2C_T_HIGH);
260 ixl_lower_i2c_clk(pf, &i2cctl);
262 /* Minimum low period of clock is 4.7 us.
263 * This also takes care of the data hold time.
265 i40e_usec_delay(IXL_I2C_T_LOW);
267 status = I40E_ERR_PHY;
268 ixl_dbg(pf, IXL_DBG_I2C, "I2C data was not set to %#x\n", data);
275 * ixl_clock_out_i2c_byte - Clocks out one byte via I2C
276 * @hw: pointer to hardware structure
277 * @data: data byte clocked out
279 * Clocks out one byte data via I2C data/clock
282 ixl_clock_out_i2c_byte(struct ixl_pf *pf, u8 data)
284 struct i40e_hw *hw = &pf->hw;
285 s32 status = I40E_SUCCESS;
290 DEBUGFUNC("ixl_clock_out_i2c_byte");
292 for (i = 7; i >= 0; i--) {
293 bit = (data >> i) & 0x1;
294 status = ixl_clock_out_i2c_bit(pf, bit);
296 if (status != I40E_SUCCESS)
300 /* Release SDA line (set high) */
301 i2cctl = rd32(hw, IXL_I2C_REG(hw));
302 i2cctl |= I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK;
303 i2cctl &= ~(I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK);
304 wr32(hw, IXL_I2C_REG(hw), i2cctl);
311 * ixl_lower_i2c_clk - Lowers the I2C SCL clock
312 * @hw: pointer to hardware structure
313 * @i2cctl: Current value of I2CCTL register
315 * Lowers the I2C clock line '1'->'0'
318 ixl_lower_i2c_clk(struct ixl_pf *pf, u32 *i2cctl)
320 struct i40e_hw *hw = &pf->hw;
322 *i2cctl &= ~(I40E_GLGEN_I2CPARAMS_CLK_MASK);
323 *i2cctl &= ~(I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK);
325 wr32(hw, IXL_I2C_REG(hw), *i2cctl);
328 /* SCL fall time (300ns) */
329 i40e_usec_delay(IXL_I2C_T_FALL);
333 * ixl_raise_i2c_clk - Raises the I2C SCL clock
334 * @hw: pointer to hardware structure
335 * @i2cctl: Current value of I2CCTL register
337 * Raises the I2C clock line '0'->'1'
340 ixl_raise_i2c_clk(struct ixl_pf *pf, u32 *i2cctl)
342 struct i40e_hw *hw = &pf->hw;
344 u32 timeout = IXL_I2C_CLOCK_STRETCHING_TIMEOUT;
347 for (i = 0; i < timeout; i++) {
348 *i2cctl |= I40E_GLGEN_I2CPARAMS_CLK_MASK;
349 *i2cctl &= ~(I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK);
351 wr32(hw, IXL_I2C_REG(hw), *i2cctl);
353 /* SCL rise time (1000ns) */
354 i40e_usec_delay(IXL_I2C_T_RISE);
356 i2cctl_r = rd32(hw, IXL_I2C_REG(hw));
357 if (i2cctl_r & I40E_GLGEN_I2CPARAMS_CLK_IN_MASK)
363 * ixl_get_i2c_data - Reads the I2C SDA data bit
364 * @hw: pointer to hardware structure
365 * @i2cctl: Current value of I2CCTL register
367 * Returns the I2C data bit value
370 ixl_get_i2c_data(struct ixl_pf *pf, u32 *i2cctl)
374 if (*i2cctl & I40E_GLGEN_I2CPARAMS_DATA_IN_MASK)
383 * ixl_set_i2c_data - Sets the I2C data bit
384 * @hw: pointer to hardware structure
385 * @i2cctl: Current value of I2CCTL register
386 * @data: I2C data value (0 or 1) to set
388 * Sets the I2C data bit
391 ixl_set_i2c_data(struct ixl_pf *pf, u32 *i2cctl, bool data)
393 struct i40e_hw *hw = &pf->hw;
394 s32 status = I40E_SUCCESS;
396 DEBUGFUNC("ixl_set_i2c_data");
399 *i2cctl |= I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK;
401 *i2cctl &= ~(I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK);
402 *i2cctl &= ~(I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK);
404 wr32(hw, IXL_I2C_REG(hw), *i2cctl);
407 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
408 i40e_usec_delay(IXL_I2C_T_RISE + IXL_I2C_T_FALL + IXL_I2C_T_SU_DATA);
410 /* Verify data was set correctly */
411 *i2cctl = rd32(hw, IXL_I2C_REG(hw));
412 if (data != ixl_get_i2c_data(pf, i2cctl)) {
413 status = I40E_ERR_PHY;
414 ixl_dbg(pf, IXL_DBG_I2C, "Error - I2C data was not set to %X.\n", data);
421 * ixl_i2c_start - Sets I2C start condition
422 * Sets I2C start condition (High -> Low on SDA while SCL is High)
425 ixl_i2c_start(struct ixl_pf *pf)
427 struct i40e_hw *hw = &pf->hw;
428 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
430 DEBUGFUNC("ixl_i2c_start");
432 /* Start condition must begin with data and clock high */
433 ixl_set_i2c_data(pf, &i2cctl, 1);
434 ixl_raise_i2c_clk(pf, &i2cctl);
436 /* Setup time for start condition (4.7us) */
437 i40e_usec_delay(IXL_I2C_T_SU_STA);
439 ixl_set_i2c_data(pf, &i2cctl, 0);
441 /* Hold time for start condition (4us) */
442 i40e_usec_delay(IXL_I2C_T_HD_STA);
444 ixl_lower_i2c_clk(pf, &i2cctl);
446 /* Minimum low period of clock is 4.7 us */
447 i40e_usec_delay(IXL_I2C_T_LOW);
452 * ixl_read_i2c_byte - Reads 8 bit word over I2C
455 ixl_read_i2c_byte(struct ixl_pf *pf, u8 byte_offset,
456 u8 dev_addr, u8 *data)
458 struct i40e_hw *hw = &pf->hw;
465 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
466 i2cctl |= I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK;
467 wr32(hw, IXL_I2C_REG(hw), i2cctl);
473 /* Device Address and write indication */
474 status = ixl_clock_out_i2c_byte(pf, dev_addr);
475 if (status != I40E_SUCCESS) {
476 ixl_dbg(pf, IXL_DBG_I2C, "dev_addr clock out error\n");
480 status = ixl_get_i2c_ack(pf);
481 if (status != I40E_SUCCESS) {
482 ixl_dbg(pf, IXL_DBG_I2C, "dev_addr i2c ack error\n");
486 status = ixl_clock_out_i2c_byte(pf, byte_offset);
487 if (status != I40E_SUCCESS) {
488 ixl_dbg(pf, IXL_DBG_I2C, "byte_offset clock out error\n");
492 status = ixl_get_i2c_ack(pf);
493 if (status != I40E_SUCCESS) {
494 ixl_dbg(pf, IXL_DBG_I2C, "byte_offset i2c ack error\n");
500 /* Device Address and read indication */
501 status = ixl_clock_out_i2c_byte(pf, (dev_addr | 0x1));
502 if (status != I40E_SUCCESS)
505 status = ixl_get_i2c_ack(pf);
506 if (status != I40E_SUCCESS)
509 status = ixl_clock_in_i2c_byte(pf, data);
510 if (status != I40E_SUCCESS)
513 status = ixl_clock_out_i2c_bit(pf, nack);
514 if (status != I40E_SUCCESS)
518 status = I40E_SUCCESS;
522 ixl_i2c_bus_clear(pf);
523 i40e_msec_delay(100);
525 if (retry < max_retry)
526 ixl_dbg(pf, IXL_DBG_I2C, "I2C byte read error - Retrying.\n");
528 ixl_dbg(pf, IXL_DBG_I2C, "I2C byte read error.\n");
530 } while (retry < max_retry);
532 i2cctl = rd32(hw, IXL_I2C_REG(hw));
533 i2cctl &= ~I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK;
534 wr32(hw, IXL_I2C_REG(hw), i2cctl);
541 * ixl_write_i2c_byte - Writes 8 bit word over I2C
544 ixl_write_i2c_byte(struct ixl_pf *pf, u8 byte_offset,
545 u8 dev_addr, u8 data)
547 struct i40e_hw *hw = &pf->hw;
548 s32 status = I40E_SUCCESS;
552 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
553 i2cctl |= I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK;
554 wr32(hw, IXL_I2C_REG(hw), i2cctl);
560 status = ixl_clock_out_i2c_byte(pf, dev_addr);
561 if (status != I40E_SUCCESS)
564 status = ixl_get_i2c_ack(pf);
565 if (status != I40E_SUCCESS)
568 status = ixl_clock_out_i2c_byte(pf, byte_offset);
569 if (status != I40E_SUCCESS)
572 status = ixl_get_i2c_ack(pf);
573 if (status != I40E_SUCCESS)
576 status = ixl_clock_out_i2c_byte(pf, data);
577 if (status != I40E_SUCCESS)
580 status = ixl_get_i2c_ack(pf);
581 if (status != I40E_SUCCESS)
588 ixl_i2c_bus_clear(pf);
589 i40e_msec_delay(100);
591 if (retry < max_retry)
592 ixl_dbg(pf, IXL_DBG_I2C, "I2C byte write error - Retrying.\n");
594 ixl_dbg(pf, IXL_DBG_I2C, "I2C byte write error.\n");
595 } while (retry < max_retry);
598 i2cctl = rd32(hw, IXL_I2C_REG(hw));
599 i2cctl &= ~I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK;
600 wr32(hw, IXL_I2C_REG(hw), i2cctl);