2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 2001 Wind River Systems
5 * Copyright (c) 1997, 1998, 1999, 2000, 2001
6 * Bill Paul <william.paul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
40 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
41 * documentation not available, but ask me nicely.
43 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
44 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
45 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
46 * are three supported methods for data transfer between host and
47 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
48 * Propulsion Technology (tm) DMA. The latter mechanism is a form
49 * of double buffer DMA where the packet data is copied to a
50 * pre-allocated DMA buffer who's physical address has been loaded
51 * into a table at device initialization time. The rationale is that
52 * the virtual to physical address translation needed for normal
53 * scatter/gather DMA is more expensive than the data copy needed
54 * for double buffering. This may be true in Windows NT and the like,
55 * but it isn't true for us, at least on the x86 arch. This driver
56 * uses the scatter/gather I/O method for both TX and RX.
58 * The LXT1001 only supports TCP/IP checksum offload on receive.
59 * Also, the VLAN tagging is done using a 16-entry table which allows
60 * the chip to perform hardware filtering based on VLAN tags. Sadly,
61 * our vlan support doesn't currently play well with this kind of
65 * - Jeff James at Intel, for arranging to have the LXT1001 manual
66 * released (at long last)
67 * - Beny Chen at D-Link, for actually sending it to me
68 * - Brad Short and Keith Alexis at SMC, for sending me sample
69 * SMC9462SX and SMC9462TX adapters for testing
70 * - Paul Saab at Y!, for not killing me (though it remains to be seen
71 * if in fact he did me much of a favor)
74 #include <sys/param.h>
75 #include <sys/systm.h>
76 #include <sys/sockio.h>
78 #include <sys/malloc.h>
79 #include <sys/kernel.h>
80 #include <sys/module.h>
81 #include <sys/socket.h>
84 #include <net/if_var.h>
85 #include <net/if_arp.h>
86 #include <net/ethernet.h>
87 #include <net/if_dl.h>
88 #include <net/if_media.h>
89 #include <net/if_types.h>
93 #include <vm/vm.h> /* for vtophys */
94 #include <vm/pmap.h> /* for vtophys */
95 #include <machine/bus.h>
96 #include <machine/resource.h>
100 #include <dev/mii/mii.h>
101 #include <dev/mii/miivar.h>
103 #include <dev/pci/pcireg.h>
104 #include <dev/pci/pcivar.h>
106 #define LGE_USEIOSPACE
108 #include <dev/lge/if_lgereg.h>
110 /* "device miibus" required. See GENERIC if you get errors here. */
111 #include "miibus_if.h"
114 * Various supported device vendors/types and their names.
116 static const struct lge_type lge_devs[] = {
117 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
121 static int lge_probe(device_t);
122 static int lge_attach(device_t);
123 static int lge_detach(device_t);
125 static int lge_alloc_jumbo_mem(struct lge_softc *);
126 static void lge_free_jumbo_mem(struct lge_softc *);
127 static void *lge_jalloc(struct lge_softc *);
128 static void lge_jfree(struct mbuf *);
130 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *);
131 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *);
132 static void lge_rxeof(struct lge_softc *, int);
133 static void lge_rxeoc(struct lge_softc *);
134 static void lge_txeof(struct lge_softc *);
135 static void lge_intr(void *);
136 static void lge_tick(void *);
137 static void lge_start(struct ifnet *);
138 static void lge_start_locked(struct ifnet *);
139 static int lge_ioctl(struct ifnet *, u_long, caddr_t);
140 static void lge_init(void *);
141 static void lge_init_locked(struct lge_softc *);
142 static void lge_stop(struct lge_softc *);
143 static void lge_watchdog(struct lge_softc *);
144 static int lge_shutdown(device_t);
145 static int lge_ifmedia_upd(struct ifnet *);
146 static void lge_ifmedia_upd_locked(struct ifnet *);
147 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
149 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *);
150 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int);
152 static int lge_miibus_readreg(device_t, int, int);
153 static int lge_miibus_writereg(device_t, int, int, int);
154 static void lge_miibus_statchg(device_t);
156 static void lge_setmulti(struct lge_softc *);
157 static void lge_reset(struct lge_softc *);
158 static int lge_list_rx_init(struct lge_softc *);
159 static int lge_list_tx_init(struct lge_softc *);
161 #ifdef LGE_USEIOSPACE
162 #define LGE_RES SYS_RES_IOPORT
163 #define LGE_RID LGE_PCI_LOIO
165 #define LGE_RES SYS_RES_MEMORY
166 #define LGE_RID LGE_PCI_LOMEM
169 static device_method_t lge_methods[] = {
170 /* Device interface */
171 DEVMETHOD(device_probe, lge_probe),
172 DEVMETHOD(device_attach, lge_attach),
173 DEVMETHOD(device_detach, lge_detach),
174 DEVMETHOD(device_shutdown, lge_shutdown),
177 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
178 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
179 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
184 static driver_t lge_driver = {
187 sizeof(struct lge_softc)
190 static devclass_t lge_devclass;
192 DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0);
193 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
194 MODULE_DEPEND(lge, pci, 1, 1, 1);
195 MODULE_DEPEND(lge, ether, 1, 1, 1);
196 MODULE_DEPEND(lge, miibus, 1, 1, 1);
198 #define LGE_SETBIT(sc, reg, x) \
199 CSR_WRITE_4(sc, reg, \
200 CSR_READ_4(sc, reg) | (x))
202 #define LGE_CLRBIT(sc, reg, x) \
203 CSR_WRITE_4(sc, reg, \
204 CSR_READ_4(sc, reg) & ~(x))
207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
210 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
213 * Read a word of data stored in the EEPROM at address 'addr.'
216 lge_eeprom_getword(sc, addr, dest)
217 struct lge_softc *sc;
224 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
225 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
227 for (i = 0; i < LGE_TIMEOUT; i++)
228 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
231 if (i == LGE_TIMEOUT) {
232 device_printf(sc->lge_dev, "EEPROM read timed out\n");
236 val = CSR_READ_4(sc, LGE_EEDATA);
239 *dest = (val >> 16) & 0xFFFF;
241 *dest = val & 0xFFFF;
247 * Read a sequence of words from the EEPROM.
250 lge_read_eeprom(sc, dest, off, cnt, swap)
251 struct lge_softc *sc;
258 u_int16_t word = 0, *ptr;
260 for (i = 0; i < cnt; i++) {
261 lge_eeprom_getword(sc, off + i, &word);
262 ptr = (u_int16_t *)(dest + (i * 2));
273 lge_miibus_readreg(dev, phy, reg)
277 struct lge_softc *sc;
280 sc = device_get_softc(dev);
283 * If we have a non-PCS PHY, pretend that the internal
284 * autoneg stuff at PHY address 0 isn't there so that
285 * the miibus code will find only the GMII PHY.
287 if (sc->lge_pcs == 0 && phy == 0)
290 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
292 for (i = 0; i < LGE_TIMEOUT; i++)
293 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
296 if (i == LGE_TIMEOUT) {
297 device_printf(sc->lge_dev, "PHY read timed out\n");
301 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
305 lge_miibus_writereg(dev, phy, reg, data)
309 struct lge_softc *sc;
312 sc = device_get_softc(dev);
314 CSR_WRITE_4(sc, LGE_GMIICTL,
315 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
317 for (i = 0; i < LGE_TIMEOUT; i++)
318 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
321 if (i == LGE_TIMEOUT) {
322 device_printf(sc->lge_dev, "PHY write timed out\n");
330 lge_miibus_statchg(dev)
333 struct lge_softc *sc;
334 struct mii_data *mii;
336 sc = device_get_softc(dev);
337 mii = device_get_softc(sc->lge_miibus);
339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
340 switch (IFM_SUBTYPE(mii->mii_media_active)) {
343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
353 * Choose something, even if it's wrong. Clearing
354 * all the bits will hose autoneg on the internal
357 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
361 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
364 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
371 lge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int count)
373 uint32_t h, *hashes = arg;
375 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
377 hashes[0] |= (1 << h);
379 hashes[1] |= (1 << (h - 32));
385 struct lge_softc *sc;
388 uint32_t hashes[2] = { 0, 0 };
393 /* Make sure multicast hash table is enabled. */
394 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
396 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
397 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
398 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
402 /* first, zot all the existing hash bits */
403 CSR_WRITE_4(sc, LGE_MAR0, 0);
404 CSR_WRITE_4(sc, LGE_MAR1, 0);
406 /* now program new ones */
407 if_foreach_llmaddr(ifp, lge_hash_maddr, hashes);
409 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
410 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
417 struct lge_softc *sc;
421 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
423 for (i = 0; i < LGE_TIMEOUT; i++) {
424 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
428 if (i == LGE_TIMEOUT)
429 device_printf(sc->lge_dev, "reset never completed\n");
431 /* Wait a little while for the chip to get its brains in order. */
438 * Probe for a Level 1 chip. Check the PCI vendor and device
439 * IDs against our list and return a device name if we find a match.
445 const struct lge_type *t;
449 while(t->lge_name != NULL) {
450 if ((pci_get_vendor(dev) == t->lge_vid) &&
451 (pci_get_device(dev) == t->lge_did)) {
452 device_set_desc(dev, t->lge_name);
453 return(BUS_PROBE_DEFAULT);
462 * Attach the interface. Allocate softc structures, do ifmedia
463 * setup and ethernet/BPF attach.
469 u_char eaddr[ETHER_ADDR_LEN];
470 struct lge_softc *sc;
471 struct ifnet *ifp = NULL;
474 sc = device_get_softc(dev);
477 mtx_init(&sc->lge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
479 callout_init_mtx(&sc->lge_stat_callout, &sc->lge_mtx, 0);
482 * Map control/status registers.
484 pci_enable_busmaster(dev);
487 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE);
489 if (sc->lge_res == NULL) {
490 device_printf(dev, "couldn't map ports/memory\n");
495 sc->lge_btag = rman_get_bustag(sc->lge_res);
496 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
498 /* Allocate interrupt */
500 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
501 RF_SHAREABLE | RF_ACTIVE);
503 if (sc->lge_irq == NULL) {
504 device_printf(dev, "couldn't map interrupt\n");
509 /* Reset the adapter. */
513 * Get station address from the EEPROM.
515 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
516 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
517 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
519 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
520 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
522 if (sc->lge_ldata == NULL) {
523 device_printf(dev, "no memory for list buffers!\n");
528 /* Try to allocate memory for jumbo buffers. */
529 if (lge_alloc_jumbo_mem(sc)) {
530 device_printf(dev, "jumbo buffer allocation failed\n");
535 ifp = sc->lge_ifp = if_alloc(IFT_ETHER);
537 device_printf(dev, "can not if_alloc()\n");
542 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
543 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
544 ifp->if_ioctl = lge_ioctl;
545 ifp->if_start = lge_start;
546 ifp->if_init = lge_init;
547 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1;
548 ifp->if_capabilities = IFCAP_RXCSUM;
549 ifp->if_capenable = ifp->if_capabilities;
551 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
559 error = mii_attach(dev, &sc->lge_miibus, ifp, lge_ifmedia_upd,
560 lge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
562 device_printf(dev, "attaching PHYs failed\n");
567 * Call MI attach routine.
569 ether_ifattach(ifp, eaddr);
571 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET | INTR_MPSAFE,
572 NULL, lge_intr, sc, &sc->lge_intrhand);
576 device_printf(dev, "couldn't set up irq\n");
582 lge_free_jumbo_mem(sc);
584 contigfree(sc->lge_ldata,
585 sizeof(struct lge_list_data), M_DEVBUF);
589 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
591 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
592 mtx_destroy(&sc->lge_mtx);
600 struct lge_softc *sc;
603 sc = device_get_softc(dev);
610 callout_drain(&sc->lge_stat_callout);
613 bus_generic_detach(dev);
614 device_delete_child(dev, sc->lge_miibus);
616 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
617 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
618 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
620 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
622 lge_free_jumbo_mem(sc);
623 mtx_destroy(&sc->lge_mtx);
629 * Initialize the transmit descriptors.
633 struct lge_softc *sc;
635 struct lge_list_data *ld;
636 struct lge_ring_data *cd;
641 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
642 ld->lge_tx_list[i].lge_mbuf = NULL;
643 ld->lge_tx_list[i].lge_ctl = 0;
646 cd->lge_tx_prod = cd->lge_tx_cons = 0;
653 * Initialize the RX descriptors and allocate mbufs for them. Note that
654 * we arralge the descriptors in a closed ring, so that the last descriptor
655 * points back to the first.
659 struct lge_softc *sc;
661 struct lge_list_data *ld;
662 struct lge_ring_data *cd;
668 cd->lge_rx_prod = cd->lge_rx_cons = 0;
670 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
672 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
673 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
675 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
679 /* Clear possible 'rx command queue empty' interrupt. */
680 CSR_READ_4(sc, LGE_ISR);
686 * Initialize an RX descriptor and attach an MBUF cluster.
690 struct lge_softc *sc;
691 struct lge_rx_desc *c;
694 struct mbuf *m_new = NULL;
698 MGETHDR(m_new, M_NOWAIT, MT_DATA);
700 device_printf(sc->lge_dev, "no memory for rx list "
701 "-- packet dropped!\n");
705 /* Allocate the jumbo buffer */
706 buf = lge_jalloc(sc);
709 device_printf(sc->lge_dev, "jumbo allocation failed "
710 "-- packet dropped!\n");
715 /* Attach the buffer to the mbuf */
716 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
717 m_extadd(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, sc, NULL,
721 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
722 m_new->m_data = m_new->m_ext.ext_buf;
726 * Adjust alignment so packet payload begins on a
727 * longword boundary. Mandatory for Alpha, useful on
730 m_adj(m_new, ETHER_ALIGN);
733 c->lge_fragptr_hi = 0;
734 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
735 c->lge_fraglen = m_new->m_len;
736 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
740 * Put this buffer in the RX command FIFO. To do this,
741 * we just write the physical address of the descriptor
742 * into the RX descriptor address registers. Note that
743 * there are two registers, one high DWORD and one low
744 * DWORD, which lets us specify a 64-bit address if
745 * desired. We only use a 32-bit address for now.
746 * Writing to the low DWORD register is what actually
747 * causes the command to be issued, so we do that
750 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
751 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
757 lge_alloc_jumbo_mem(sc)
758 struct lge_softc *sc;
762 struct lge_jpool_entry *entry;
764 /* Grab a big chunk o' storage. */
765 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
766 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
768 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
769 device_printf(sc->lge_dev, "no memory for jumbo buffers!\n");
773 SLIST_INIT(&sc->lge_jfree_listhead);
774 SLIST_INIT(&sc->lge_jinuse_listhead);
777 * Now divide it up into 9K pieces and save the addresses
780 ptr = sc->lge_cdata.lge_jumbo_buf;
781 for (i = 0; i < LGE_JSLOTS; i++) {
782 sc->lge_cdata.lge_jslots[i] = ptr;
784 entry = malloc(sizeof(struct lge_jpool_entry),
787 device_printf(sc->lge_dev, "no memory for jumbo "
792 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
793 entry, jpool_entries);
800 lge_free_jumbo_mem(sc)
801 struct lge_softc *sc;
803 struct lge_jpool_entry *entry;
805 if (sc->lge_cdata.lge_jumbo_buf == NULL)
808 while ((entry = SLIST_FIRST(&sc->lge_jinuse_listhead))) {
809 device_printf(sc->lge_dev,
810 "asked to free buffer that is in use!\n");
811 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
812 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry,
815 while (!SLIST_EMPTY(&sc->lge_jfree_listhead)) {
816 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
817 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
818 free(entry, M_DEVBUF);
821 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
827 * Allocate a jumbo buffer.
831 struct lge_softc *sc;
833 struct lge_jpool_entry *entry;
835 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
839 device_printf(sc->lge_dev, "no free jumbo buffers\n");
844 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
845 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
846 return(sc->lge_cdata.lge_jslots[entry->slot]);
850 * Release a jumbo buffer.
853 lge_jfree(struct mbuf *m)
855 struct lge_softc *sc;
857 struct lge_jpool_entry *entry;
859 /* Extract the softc struct pointer. */
860 sc = m->m_ext.ext_arg1;
863 panic("lge_jfree: can't find softc pointer!");
865 /* calculate the slot this buffer belongs to */
866 i = ((vm_offset_t)m->m_ext.ext_buf
867 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
869 if ((i < 0) || (i >= LGE_JSLOTS))
870 panic("lge_jfree: asked to free buffer that we don't manage!");
872 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
874 panic("lge_jfree: buffer not in use!");
876 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
877 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries);
881 * A frame has been uploaded: pass the resulting mbuf chain up to
882 * the higher level protocols.
886 struct lge_softc *sc;
891 struct lge_rx_desc *cur_rx;
892 int c, i, total_len = 0;
893 u_int32_t rxsts, rxctl;
897 /* Find out how many frames were processed. */
899 i = sc->lge_cdata.lge_rx_cons;
903 struct mbuf *m0 = NULL;
905 cur_rx = &sc->lge_ldata->lge_rx_list[i];
906 rxctl = cur_rx->lge_ctl;
907 rxsts = cur_rx->lge_sts;
908 m = cur_rx->lge_mbuf;
909 cur_rx->lge_mbuf = NULL;
910 total_len = LGE_RXBYTES(cur_rx);
911 LGE_INC(i, LGE_RX_LIST_CNT);
915 * If an error occurs, update stats, clear the
916 * status word and leave the mbuf cluster in place:
917 * it should simply get re-used next time this descriptor
918 * comes up in the ring.
920 if (rxctl & LGE_RXCTL_ERRMASK) {
921 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
922 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
926 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
927 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN,
929 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
931 device_printf(sc->lge_dev, "no receive buffers "
932 "available -- packet dropped!\n");
933 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
938 m->m_pkthdr.rcvif = ifp;
939 m->m_pkthdr.len = m->m_len = total_len;
942 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
944 /* Do IP checksum checking. */
945 if (rxsts & LGE_RXSTS_ISIP)
946 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
947 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
948 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
949 if ((rxsts & LGE_RXSTS_ISTCP &&
950 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
951 (rxsts & LGE_RXSTS_ISUDP &&
952 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
953 m->m_pkthdr.csum_flags |=
954 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
955 m->m_pkthdr.csum_data = 0xffff;
959 (*ifp->if_input)(ifp, m);
963 sc->lge_cdata.lge_rx_cons = i;
970 struct lge_softc *sc;
975 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
981 * A frame was downloaded to the chip. It's safe for us to clean up
987 struct lge_softc *sc;
989 struct lge_tx_desc *cur_tx = NULL;
991 u_int32_t idx, txdone;
995 /* Clear the timeout timer. */
999 * Go through our tx list and free mbufs for those
1000 * frames that have been transmitted.
1002 idx = sc->lge_cdata.lge_tx_cons;
1003 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1005 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1006 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1008 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1009 if (cur_tx->lge_mbuf != NULL) {
1010 m_freem(cur_tx->lge_mbuf);
1011 cur_tx->lge_mbuf = NULL;
1013 cur_tx->lge_ctl = 0;
1016 LGE_INC(idx, LGE_TX_LIST_CNT);
1020 sc->lge_cdata.lge_tx_cons = idx;
1023 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1032 struct lge_softc *sc;
1033 struct mii_data *mii;
1038 LGE_LOCK_ASSERT(sc);
1040 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1041 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL));
1042 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1043 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL));
1045 if (!sc->lge_link) {
1046 mii = device_get_softc(sc->lge_miibus);
1048 if (mii->mii_media_status & IFM_ACTIVE &&
1049 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1052 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1053 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T))
1054 device_printf(sc->lge_dev, "gigabit link up\n");
1055 if (ifp->if_snd.ifq_head != NULL)
1056 lge_start_locked(ifp);
1060 if (sc->lge_timer != 0 && --sc->lge_timer == 0)
1062 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc);
1071 struct lge_softc *sc;
1079 /* Suppress unwanted interrupts */
1080 if (!(ifp->if_flags & IFF_UP)) {
1088 * Reading the ISR register clears all interrupts, and
1089 * clears the 'interrupts enabled' bit in the IMR
1092 status = CSR_READ_4(sc, LGE_ISR);
1094 if ((status & LGE_INTRS) == 0)
1097 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1100 if (status & LGE_ISR_RXDMA_DONE)
1101 lge_rxeof(sc, LGE_RX_DMACNT(status));
1103 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1106 if (status & LGE_ISR_PHY_INTR) {
1108 callout_stop(&sc->lge_stat_callout);
1113 /* Re-enable interrupts. */
1114 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1116 if (ifp->if_snd.ifq_head != NULL)
1117 lge_start_locked(ifp);
1124 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1125 * pointers to the fragment pointers.
1128 lge_encap(sc, m_head, txidx)
1129 struct lge_softc *sc;
1130 struct mbuf *m_head;
1133 struct lge_frag *f = NULL;
1134 struct lge_tx_desc *cur_tx;
1136 int frag = 0, tot_len = 0;
1139 * Start packing the mbufs in this chain into
1140 * the fragment pointers. Stop when we run out
1141 * of fragments or hit the end of the mbuf chain.
1144 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1147 for (m = m_head; m != NULL; m = m->m_next) {
1148 if (m->m_len != 0) {
1149 tot_len += m->m_len;
1150 f = &cur_tx->lge_frags[frag];
1151 f->lge_fraglen = m->m_len;
1152 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1153 f->lge_fragptr_hi = 0;
1161 cur_tx->lge_mbuf = m_head;
1162 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1163 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1165 /* Queue for transmit */
1166 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1172 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1173 * to the mbuf data regions directly in the transmit lists. We also save a
1174 * copy of the pointers since the transmit list fragment pointers are
1175 * physical addresses.
1182 struct lge_softc *sc;
1186 lge_start_locked(ifp);
1191 lge_start_locked(ifp)
1194 struct lge_softc *sc;
1195 struct mbuf *m_head = NULL;
1203 idx = sc->lge_cdata.lge_tx_prod;
1205 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1208 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1209 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1212 IF_DEQUEUE(&ifp->if_snd, m_head);
1216 if (lge_encap(sc, m_head, &idx)) {
1217 IF_PREPEND(&ifp->if_snd, m_head);
1218 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1223 * If there's a BPF listener, bounce a copy of this frame
1226 BPF_MTAP(ifp, m_head);
1229 sc->lge_cdata.lge_tx_prod = idx;
1232 * Set a timeout in case the chip goes out to lunch.
1243 struct lge_softc *sc = xsc;
1246 lge_init_locked(sc);
1252 struct lge_softc *sc;
1254 struct ifnet *ifp = sc->lge_ifp;
1256 LGE_LOCK_ASSERT(sc);
1257 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1261 * Cancel pending I/O and free all RX/TX buffers.
1266 /* Set MAC address */
1267 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[0]));
1268 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[4]));
1270 /* Init circular RX list. */
1271 if (lge_list_rx_init(sc) == ENOBUFS) {
1272 device_printf(sc->lge_dev, "initialization failed: no "
1273 "memory for rx buffers\n");
1279 * Init tx descriptors.
1281 lge_list_tx_init(sc);
1283 /* Set initial value for MODE1 register. */
1284 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1285 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1286 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1287 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1289 /* If we want promiscuous mode, set the allframes bit. */
1290 if (ifp->if_flags & IFF_PROMISC) {
1291 CSR_WRITE_4(sc, LGE_MODE1,
1292 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1294 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1298 * Set the capture broadcast bit to capture broadcast frames.
1300 if (ifp->if_flags & IFF_BROADCAST) {
1301 CSR_WRITE_4(sc, LGE_MODE1,
1302 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1304 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1307 /* Packet padding workaround? */
1308 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1310 /* No error frames */
1311 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1313 /* Receive large frames */
1314 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1316 /* Workaround: disable RX/TX flow control */
1317 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1318 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1320 /* Make sure to strip CRC from received frames */
1321 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1323 /* Turn off magic packet mode */
1324 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1326 /* Turn off all VLAN stuff */
1327 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1328 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1330 /* Workarond: FIFO overflow */
1331 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1332 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1335 * Load the multicast filter.
1340 * Enable hardware checksum validation for all received IPv4
1341 * packets, do not reject packets with bad checksums.
1343 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1344 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1345 LGE_MODE2_RX_ERRCSUM);
1348 * Enable the delivery of PHY interrupts based on
1349 * link/speed/duplex status chalges.
1351 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1353 /* Enable receiver and transmitter. */
1354 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1355 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1357 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1358 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1361 * Enable interrupts.
1363 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1364 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1366 lge_ifmedia_upd_locked(ifp);
1368 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1369 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1371 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc);
1377 * Set media options.
1380 lge_ifmedia_upd(ifp)
1383 struct lge_softc *sc;
1387 lge_ifmedia_upd_locked(ifp);
1394 lge_ifmedia_upd_locked(ifp)
1397 struct lge_softc *sc;
1398 struct mii_data *mii;
1399 struct mii_softc *miisc;
1403 LGE_LOCK_ASSERT(sc);
1404 mii = device_get_softc(sc->lge_miibus);
1406 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1412 * Report current media status.
1415 lge_ifmedia_sts(ifp, ifmr)
1417 struct ifmediareq *ifmr;
1419 struct lge_softc *sc;
1420 struct mii_data *mii;
1425 mii = device_get_softc(sc->lge_miibus);
1427 ifmr->ifm_active = mii->mii_media_active;
1428 ifmr->ifm_status = mii->mii_media_status;
1435 lge_ioctl(ifp, command, data)
1440 struct lge_softc *sc = ifp->if_softc;
1441 struct ifreq *ifr = (struct ifreq *) data;
1442 struct mii_data *mii;
1448 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1451 ifp->if_mtu = ifr->ifr_mtu;
1456 if (ifp->if_flags & IFF_UP) {
1457 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1458 ifp->if_flags & IFF_PROMISC &&
1459 !(sc->lge_if_flags & IFF_PROMISC)) {
1460 CSR_WRITE_4(sc, LGE_MODE1,
1461 LGE_MODE1_SETRST_CTL1|
1462 LGE_MODE1_RX_PROMISC);
1463 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1464 !(ifp->if_flags & IFF_PROMISC) &&
1465 sc->lge_if_flags & IFF_PROMISC) {
1466 CSR_WRITE_4(sc, LGE_MODE1,
1467 LGE_MODE1_RX_PROMISC);
1469 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1470 lge_init_locked(sc);
1473 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1476 sc->lge_if_flags = ifp->if_flags;
1489 mii = device_get_softc(sc->lge_miibus);
1490 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1493 error = ether_ioctl(ifp, command, data);
1502 struct lge_softc *sc;
1506 LGE_LOCK_ASSERT(sc);
1509 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1510 if_printf(ifp, "watchdog timeout\n");
1514 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1515 lge_init_locked(sc);
1517 if (ifp->if_snd.ifq_head != NULL)
1518 lge_start_locked(ifp);
1522 * Stop the adapter and free any mbufs allocated to the
1527 struct lge_softc *sc;
1532 LGE_LOCK_ASSERT(sc);
1535 callout_stop(&sc->lge_stat_callout);
1536 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1538 /* Disable receiver and transmitter. */
1539 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1543 * Free data in the RX lists.
1545 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1546 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1547 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1548 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1551 bzero((char *)&sc->lge_ldata->lge_rx_list,
1552 sizeof(sc->lge_ldata->lge_rx_list));
1555 * Free the TX list buffers.
1557 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1558 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1559 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1560 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1564 bzero((char *)&sc->lge_ldata->lge_tx_list,
1565 sizeof(sc->lge_ldata->lge_tx_list));
1567 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1573 * Stop all chip I/O so that the kernel's probe routines don't
1574 * get confused by errant DMAs when rebooting.
1580 struct lge_softc *sc;
1582 sc = device_get_softc(dev);