2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
39 * documentation not available, but ask me nicely.
41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
42 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
44 * are three supported methods for data transfer between host and
45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
46 * Propulsion Technology (tm) DMA. The latter mechanism is a form
47 * of double buffer DMA where the packet data is copied to a
48 * pre-allocated DMA buffer who's physical address has been loaded
49 * into a table at device initialization time. The rationale is that
50 * the virtual to physical address translation needed for normal
51 * scatter/gather DMA is more expensive than the data copy needed
52 * for double buffering. This may be true in Windows NT and the like,
53 * but it isn't true for us, at least on the x86 arch. This driver
54 * uses the scatter/gather I/O method for both TX and RX.
56 * The LXT1001 only supports TCP/IP checksum offload on receive.
57 * Also, the VLAN tagging is done using a 16-entry table which allows
58 * the chip to perform hardware filtering based on VLAN tags. Sadly,
59 * our vlan support doesn't currently play well with this kind of
63 * - Jeff James at Intel, for arranging to have the LXT1001 manual
64 * released (at long last)
65 * - Beny Chen at D-Link, for actually sending it to me
66 * - Brad Short and Keith Alexis at SMC, for sending me sample
67 * SMC9462SX and SMC9462TX adapters for testing
68 * - Paul Saab at Y!, for not killing me (though it remains to be seen
69 * if in fact he did me much of a favor)
72 #include <sys/param.h>
73 #include <sys/systm.h>
74 #include <sys/sockio.h>
76 #include <sys/malloc.h>
77 #include <sys/kernel.h>
78 #include <sys/module.h>
79 #include <sys/socket.h>
82 #include <net/if_var.h>
83 #include <net/if_arp.h>
84 #include <net/ethernet.h>
85 #include <net/if_dl.h>
86 #include <net/if_media.h>
87 #include <net/if_types.h>
91 #include <vm/vm.h> /* for vtophys */
92 #include <vm/pmap.h> /* for vtophys */
93 #include <machine/bus.h>
94 #include <machine/resource.h>
98 #include <dev/mii/mii.h>
99 #include <dev/mii/miivar.h>
101 #include <dev/pci/pcireg.h>
102 #include <dev/pci/pcivar.h>
104 #define LGE_USEIOSPACE
106 #include <dev/lge/if_lgereg.h>
108 /* "device miibus" required. See GENERIC if you get errors here. */
109 #include "miibus_if.h"
112 * Various supported device vendors/types and their names.
114 static const struct lge_type lge_devs[] = {
115 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
119 static int lge_probe(device_t);
120 static int lge_attach(device_t);
121 static int lge_detach(device_t);
123 static int lge_alloc_jumbo_mem(struct lge_softc *);
124 static void lge_free_jumbo_mem(struct lge_softc *);
125 static void *lge_jalloc(struct lge_softc *);
126 static void lge_jfree(struct mbuf *, void *, void *);
128 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *);
129 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *);
130 static void lge_rxeof(struct lge_softc *, int);
131 static void lge_rxeoc(struct lge_softc *);
132 static void lge_txeof(struct lge_softc *);
133 static void lge_intr(void *);
134 static void lge_tick(void *);
135 static void lge_start(struct ifnet *);
136 static void lge_start_locked(struct ifnet *);
137 static int lge_ioctl(struct ifnet *, u_long, caddr_t);
138 static void lge_init(void *);
139 static void lge_init_locked(struct lge_softc *);
140 static void lge_stop(struct lge_softc *);
141 static void lge_watchdog(struct lge_softc *);
142 static int lge_shutdown(device_t);
143 static int lge_ifmedia_upd(struct ifnet *);
144 static void lge_ifmedia_upd_locked(struct ifnet *);
145 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
147 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *);
148 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int);
150 static int lge_miibus_readreg(device_t, int, int);
151 static int lge_miibus_writereg(device_t, int, int, int);
152 static void lge_miibus_statchg(device_t);
154 static void lge_setmulti(struct lge_softc *);
155 static void lge_reset(struct lge_softc *);
156 static int lge_list_rx_init(struct lge_softc *);
157 static int lge_list_tx_init(struct lge_softc *);
159 #ifdef LGE_USEIOSPACE
160 #define LGE_RES SYS_RES_IOPORT
161 #define LGE_RID LGE_PCI_LOIO
163 #define LGE_RES SYS_RES_MEMORY
164 #define LGE_RID LGE_PCI_LOMEM
167 static device_method_t lge_methods[] = {
168 /* Device interface */
169 DEVMETHOD(device_probe, lge_probe),
170 DEVMETHOD(device_attach, lge_attach),
171 DEVMETHOD(device_detach, lge_detach),
172 DEVMETHOD(device_shutdown, lge_shutdown),
175 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
176 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
177 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
182 static driver_t lge_driver = {
185 sizeof(struct lge_softc)
188 static devclass_t lge_devclass;
190 DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0);
191 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
192 MODULE_DEPEND(lge, pci, 1, 1, 1);
193 MODULE_DEPEND(lge, ether, 1, 1, 1);
194 MODULE_DEPEND(lge, miibus, 1, 1, 1);
196 #define LGE_SETBIT(sc, reg, x) \
197 CSR_WRITE_4(sc, reg, \
198 CSR_READ_4(sc, reg) | (x))
200 #define LGE_CLRBIT(sc, reg, x) \
201 CSR_WRITE_4(sc, reg, \
202 CSR_READ_4(sc, reg) & ~(x))
205 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
208 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
211 * Read a word of data stored in the EEPROM at address 'addr.'
214 lge_eeprom_getword(sc, addr, dest)
215 struct lge_softc *sc;
222 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
223 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
225 for (i = 0; i < LGE_TIMEOUT; i++)
226 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
229 if (i == LGE_TIMEOUT) {
230 device_printf(sc->lge_dev, "EEPROM read timed out\n");
234 val = CSR_READ_4(sc, LGE_EEDATA);
237 *dest = (val >> 16) & 0xFFFF;
239 *dest = val & 0xFFFF;
245 * Read a sequence of words from the EEPROM.
248 lge_read_eeprom(sc, dest, off, cnt, swap)
249 struct lge_softc *sc;
256 u_int16_t word = 0, *ptr;
258 for (i = 0; i < cnt; i++) {
259 lge_eeprom_getword(sc, off + i, &word);
260 ptr = (u_int16_t *)(dest + (i * 2));
271 lge_miibus_readreg(dev, phy, reg)
275 struct lge_softc *sc;
278 sc = device_get_softc(dev);
281 * If we have a non-PCS PHY, pretend that the internal
282 * autoneg stuff at PHY address 0 isn't there so that
283 * the miibus code will find only the GMII PHY.
285 if (sc->lge_pcs == 0 && phy == 0)
288 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
290 for (i = 0; i < LGE_TIMEOUT; i++)
291 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
294 if (i == LGE_TIMEOUT) {
295 device_printf(sc->lge_dev, "PHY read timed out\n");
299 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
303 lge_miibus_writereg(dev, phy, reg, data)
307 struct lge_softc *sc;
310 sc = device_get_softc(dev);
312 CSR_WRITE_4(sc, LGE_GMIICTL,
313 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
315 for (i = 0; i < LGE_TIMEOUT; i++)
316 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
319 if (i == LGE_TIMEOUT) {
320 device_printf(sc->lge_dev, "PHY write timed out\n");
328 lge_miibus_statchg(dev)
331 struct lge_softc *sc;
332 struct mii_data *mii;
334 sc = device_get_softc(dev);
335 mii = device_get_softc(sc->lge_miibus);
337 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
338 switch (IFM_SUBTYPE(mii->mii_media_active)) {
341 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
344 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
347 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
351 * Choose something, even if it's wrong. Clearing
352 * all the bits will hose autoneg on the internal
355 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
359 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
360 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
362 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
370 struct lge_softc *sc;
373 struct ifmultiaddr *ifma;
374 u_int32_t h = 0, hashes[2] = { 0, 0 };
379 /* Make sure multicast hash table is enabled. */
380 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
382 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
383 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
384 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
388 /* first, zot all the existing hash bits */
389 CSR_WRITE_4(sc, LGE_MAR0, 0);
390 CSR_WRITE_4(sc, LGE_MAR1, 0);
392 /* now program new ones */
394 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
395 if (ifma->ifma_addr->sa_family != AF_LINK)
397 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
398 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
400 hashes[0] |= (1 << h);
402 hashes[1] |= (1 << (h - 32));
404 if_maddr_runlock(ifp);
406 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
407 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
414 struct lge_softc *sc;
418 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
420 for (i = 0; i < LGE_TIMEOUT; i++) {
421 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
425 if (i == LGE_TIMEOUT)
426 device_printf(sc->lge_dev, "reset never completed\n");
428 /* Wait a little while for the chip to get its brains in order. */
435 * Probe for a Level 1 chip. Check the PCI vendor and device
436 * IDs against our list and return a device name if we find a match.
442 const struct lge_type *t;
446 while(t->lge_name != NULL) {
447 if ((pci_get_vendor(dev) == t->lge_vid) &&
448 (pci_get_device(dev) == t->lge_did)) {
449 device_set_desc(dev, t->lge_name);
450 return(BUS_PROBE_DEFAULT);
459 * Attach the interface. Allocate softc structures, do ifmedia
460 * setup and ethernet/BPF attach.
466 u_char eaddr[ETHER_ADDR_LEN];
467 struct lge_softc *sc;
468 struct ifnet *ifp = NULL;
471 sc = device_get_softc(dev);
474 mtx_init(&sc->lge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
476 callout_init_mtx(&sc->lge_stat_callout, &sc->lge_mtx, 0);
479 * Map control/status registers.
481 pci_enable_busmaster(dev);
484 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE);
486 if (sc->lge_res == NULL) {
487 device_printf(dev, "couldn't map ports/memory\n");
492 sc->lge_btag = rman_get_bustag(sc->lge_res);
493 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
495 /* Allocate interrupt */
497 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
498 RF_SHAREABLE | RF_ACTIVE);
500 if (sc->lge_irq == NULL) {
501 device_printf(dev, "couldn't map interrupt\n");
506 /* Reset the adapter. */
510 * Get station address from the EEPROM.
512 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
513 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
514 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
516 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
517 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
519 if (sc->lge_ldata == NULL) {
520 device_printf(dev, "no memory for list buffers!\n");
525 /* Try to allocate memory for jumbo buffers. */
526 if (lge_alloc_jumbo_mem(sc)) {
527 device_printf(dev, "jumbo buffer allocation failed\n");
532 ifp = sc->lge_ifp = if_alloc(IFT_ETHER);
534 device_printf(dev, "can not if_alloc()\n");
539 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
540 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
541 ifp->if_ioctl = lge_ioctl;
542 ifp->if_start = lge_start;
543 ifp->if_init = lge_init;
544 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1;
545 ifp->if_capabilities = IFCAP_RXCSUM;
546 ifp->if_capenable = ifp->if_capabilities;
548 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
556 error = mii_attach(dev, &sc->lge_miibus, ifp, lge_ifmedia_upd,
557 lge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
559 device_printf(dev, "attaching PHYs failed\n");
564 * Call MI attach routine.
566 ether_ifattach(ifp, eaddr);
568 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET | INTR_MPSAFE,
569 NULL, lge_intr, sc, &sc->lge_intrhand);
573 device_printf(dev, "couldn't set up irq\n");
579 lge_free_jumbo_mem(sc);
581 contigfree(sc->lge_ldata,
582 sizeof(struct lge_list_data), M_DEVBUF);
586 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
588 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
589 mtx_destroy(&sc->lge_mtx);
597 struct lge_softc *sc;
600 sc = device_get_softc(dev);
607 callout_drain(&sc->lge_stat_callout);
610 bus_generic_detach(dev);
611 device_delete_child(dev, sc->lge_miibus);
613 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
614 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
615 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
617 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
619 lge_free_jumbo_mem(sc);
620 mtx_destroy(&sc->lge_mtx);
626 * Initialize the transmit descriptors.
630 struct lge_softc *sc;
632 struct lge_list_data *ld;
633 struct lge_ring_data *cd;
638 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
639 ld->lge_tx_list[i].lge_mbuf = NULL;
640 ld->lge_tx_list[i].lge_ctl = 0;
643 cd->lge_tx_prod = cd->lge_tx_cons = 0;
650 * Initialize the RX descriptors and allocate mbufs for them. Note that
651 * we arralge the descriptors in a closed ring, so that the last descriptor
652 * points back to the first.
656 struct lge_softc *sc;
658 struct lge_list_data *ld;
659 struct lge_ring_data *cd;
665 cd->lge_rx_prod = cd->lge_rx_cons = 0;
667 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
669 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
670 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
672 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
676 /* Clear possible 'rx command queue empty' interrupt. */
677 CSR_READ_4(sc, LGE_ISR);
683 * Initialize an RX descriptor and attach an MBUF cluster.
687 struct lge_softc *sc;
688 struct lge_rx_desc *c;
691 struct mbuf *m_new = NULL;
695 MGETHDR(m_new, M_NOWAIT, MT_DATA);
697 device_printf(sc->lge_dev, "no memory for rx list "
698 "-- packet dropped!\n");
702 /* Allocate the jumbo buffer */
703 buf = lge_jalloc(sc);
706 device_printf(sc->lge_dev, "jumbo allocation failed "
707 "-- packet dropped!\n");
712 /* Attach the buffer to the mbuf */
713 m_new->m_data = (void *)buf;
714 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
715 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree,
716 buf, (struct lge_softc *)sc, 0, EXT_NET_DRV);
719 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
720 m_new->m_data = m_new->m_ext.ext_buf;
724 * Adjust alignment so packet payload begins on a
725 * longword boundary. Mandatory for Alpha, useful on
728 m_adj(m_new, ETHER_ALIGN);
731 c->lge_fragptr_hi = 0;
732 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
733 c->lge_fraglen = m_new->m_len;
734 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
738 * Put this buffer in the RX command FIFO. To do this,
739 * we just write the physical address of the descriptor
740 * into the RX descriptor address registers. Note that
741 * there are two registers, one high DWORD and one low
742 * DWORD, which lets us specify a 64-bit address if
743 * desired. We only use a 32-bit address for now.
744 * Writing to the low DWORD register is what actually
745 * causes the command to be issued, so we do that
748 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
749 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
755 lge_alloc_jumbo_mem(sc)
756 struct lge_softc *sc;
760 struct lge_jpool_entry *entry;
762 /* Grab a big chunk o' storage. */
763 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
764 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
766 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
767 device_printf(sc->lge_dev, "no memory for jumbo buffers!\n");
771 SLIST_INIT(&sc->lge_jfree_listhead);
772 SLIST_INIT(&sc->lge_jinuse_listhead);
775 * Now divide it up into 9K pieces and save the addresses
778 ptr = sc->lge_cdata.lge_jumbo_buf;
779 for (i = 0; i < LGE_JSLOTS; i++) {
780 sc->lge_cdata.lge_jslots[i] = ptr;
782 entry = malloc(sizeof(struct lge_jpool_entry),
785 device_printf(sc->lge_dev, "no memory for jumbo "
790 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
791 entry, jpool_entries);
798 lge_free_jumbo_mem(sc)
799 struct lge_softc *sc;
801 struct lge_jpool_entry *entry;
803 if (sc->lge_cdata.lge_jumbo_buf == NULL)
806 while ((entry = SLIST_FIRST(&sc->lge_jinuse_listhead))) {
807 device_printf(sc->lge_dev,
808 "asked to free buffer that is in use!\n");
809 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
810 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry,
813 while (!SLIST_EMPTY(&sc->lge_jfree_listhead)) {
814 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
815 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
816 free(entry, M_DEVBUF);
819 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
825 * Allocate a jumbo buffer.
829 struct lge_softc *sc;
831 struct lge_jpool_entry *entry;
833 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
837 device_printf(sc->lge_dev, "no free jumbo buffers\n");
842 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
843 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
844 return(sc->lge_cdata.lge_jslots[entry->slot]);
848 * Release a jumbo buffer.
851 lge_jfree(struct mbuf *m, void *buf, void *args)
853 struct lge_softc *sc;
855 struct lge_jpool_entry *entry;
857 /* Extract the softc struct pointer. */
861 panic("lge_jfree: can't find softc pointer!");
863 /* calculate the slot this buffer belongs to */
864 i = ((vm_offset_t)buf
865 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
867 if ((i < 0) || (i >= LGE_JSLOTS))
868 panic("lge_jfree: asked to free buffer that we don't manage!");
870 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
872 panic("lge_jfree: buffer not in use!");
874 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
875 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries);
879 * A frame has been uploaded: pass the resulting mbuf chain up to
880 * the higher level protocols.
884 struct lge_softc *sc;
889 struct lge_rx_desc *cur_rx;
890 int c, i, total_len = 0;
891 u_int32_t rxsts, rxctl;
895 /* Find out how many frames were processed. */
897 i = sc->lge_cdata.lge_rx_cons;
901 struct mbuf *m0 = NULL;
903 cur_rx = &sc->lge_ldata->lge_rx_list[i];
904 rxctl = cur_rx->lge_ctl;
905 rxsts = cur_rx->lge_sts;
906 m = cur_rx->lge_mbuf;
907 cur_rx->lge_mbuf = NULL;
908 total_len = LGE_RXBYTES(cur_rx);
909 LGE_INC(i, LGE_RX_LIST_CNT);
913 * If an error occurs, update stats, clear the
914 * status word and leave the mbuf cluster in place:
915 * it should simply get re-used next time this descriptor
916 * comes up in the ring.
918 if (rxctl & LGE_RXCTL_ERRMASK) {
919 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
920 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
924 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
925 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN,
927 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
929 device_printf(sc->lge_dev, "no receive buffers "
930 "available -- packet dropped!\n");
931 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
936 m->m_pkthdr.rcvif = ifp;
937 m->m_pkthdr.len = m->m_len = total_len;
940 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
942 /* Do IP checksum checking. */
943 if (rxsts & LGE_RXSTS_ISIP)
944 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
945 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
946 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
947 if ((rxsts & LGE_RXSTS_ISTCP &&
948 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
949 (rxsts & LGE_RXSTS_ISUDP &&
950 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
951 m->m_pkthdr.csum_flags |=
952 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
953 m->m_pkthdr.csum_data = 0xffff;
957 (*ifp->if_input)(ifp, m);
961 sc->lge_cdata.lge_rx_cons = i;
968 struct lge_softc *sc;
973 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
979 * A frame was downloaded to the chip. It's safe for us to clean up
985 struct lge_softc *sc;
987 struct lge_tx_desc *cur_tx = NULL;
989 u_int32_t idx, txdone;
993 /* Clear the timeout timer. */
997 * Go through our tx list and free mbufs for those
998 * frames that have been transmitted.
1000 idx = sc->lge_cdata.lge_tx_cons;
1001 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1003 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1004 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1006 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1007 if (cur_tx->lge_mbuf != NULL) {
1008 m_freem(cur_tx->lge_mbuf);
1009 cur_tx->lge_mbuf = NULL;
1011 cur_tx->lge_ctl = 0;
1014 LGE_INC(idx, LGE_TX_LIST_CNT);
1018 sc->lge_cdata.lge_tx_cons = idx;
1021 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1030 struct lge_softc *sc;
1031 struct mii_data *mii;
1036 LGE_LOCK_ASSERT(sc);
1038 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1039 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL));
1040 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1041 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL));
1043 if (!sc->lge_link) {
1044 mii = device_get_softc(sc->lge_miibus);
1046 if (mii->mii_media_status & IFM_ACTIVE &&
1047 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1050 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1051 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T))
1052 device_printf(sc->lge_dev, "gigabit link up\n");
1053 if (ifp->if_snd.ifq_head != NULL)
1054 lge_start_locked(ifp);
1058 if (sc->lge_timer != 0 && --sc->lge_timer == 0)
1060 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc);
1069 struct lge_softc *sc;
1077 /* Supress unwanted interrupts */
1078 if (!(ifp->if_flags & IFF_UP)) {
1086 * Reading the ISR register clears all interrupts, and
1087 * clears the 'interrupts enabled' bit in the IMR
1090 status = CSR_READ_4(sc, LGE_ISR);
1092 if ((status & LGE_INTRS) == 0)
1095 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1098 if (status & LGE_ISR_RXDMA_DONE)
1099 lge_rxeof(sc, LGE_RX_DMACNT(status));
1101 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1104 if (status & LGE_ISR_PHY_INTR) {
1106 callout_stop(&sc->lge_stat_callout);
1111 /* Re-enable interrupts. */
1112 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1114 if (ifp->if_snd.ifq_head != NULL)
1115 lge_start_locked(ifp);
1122 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1123 * pointers to the fragment pointers.
1126 lge_encap(sc, m_head, txidx)
1127 struct lge_softc *sc;
1128 struct mbuf *m_head;
1131 struct lge_frag *f = NULL;
1132 struct lge_tx_desc *cur_tx;
1134 int frag = 0, tot_len = 0;
1137 * Start packing the mbufs in this chain into
1138 * the fragment pointers. Stop when we run out
1139 * of fragments or hit the end of the mbuf chain.
1142 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1145 for (m = m_head; m != NULL; m = m->m_next) {
1146 if (m->m_len != 0) {
1147 tot_len += m->m_len;
1148 f = &cur_tx->lge_frags[frag];
1149 f->lge_fraglen = m->m_len;
1150 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1151 f->lge_fragptr_hi = 0;
1159 cur_tx->lge_mbuf = m_head;
1160 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1161 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1163 /* Queue for transmit */
1164 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1170 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1171 * to the mbuf data regions directly in the transmit lists. We also save a
1172 * copy of the pointers since the transmit list fragment pointers are
1173 * physical addresses.
1180 struct lge_softc *sc;
1184 lge_start_locked(ifp);
1189 lge_start_locked(ifp)
1192 struct lge_softc *sc;
1193 struct mbuf *m_head = NULL;
1201 idx = sc->lge_cdata.lge_tx_prod;
1203 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1206 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1207 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1210 IF_DEQUEUE(&ifp->if_snd, m_head);
1214 if (lge_encap(sc, m_head, &idx)) {
1215 IF_PREPEND(&ifp->if_snd, m_head);
1216 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1221 * If there's a BPF listener, bounce a copy of this frame
1224 BPF_MTAP(ifp, m_head);
1227 sc->lge_cdata.lge_tx_prod = idx;
1230 * Set a timeout in case the chip goes out to lunch.
1241 struct lge_softc *sc = xsc;
1244 lge_init_locked(sc);
1250 struct lge_softc *sc;
1252 struct ifnet *ifp = sc->lge_ifp;
1254 LGE_LOCK_ASSERT(sc);
1255 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1259 * Cancel pending I/O and free all RX/TX buffers.
1264 /* Set MAC address */
1265 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[0]));
1266 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&IF_LLADDR(sc->lge_ifp)[4]));
1268 /* Init circular RX list. */
1269 if (lge_list_rx_init(sc) == ENOBUFS) {
1270 device_printf(sc->lge_dev, "initialization failed: no "
1271 "memory for rx buffers\n");
1277 * Init tx descriptors.
1279 lge_list_tx_init(sc);
1281 /* Set initial value for MODE1 register. */
1282 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1283 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1284 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1285 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1287 /* If we want promiscuous mode, set the allframes bit. */
1288 if (ifp->if_flags & IFF_PROMISC) {
1289 CSR_WRITE_4(sc, LGE_MODE1,
1290 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1292 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1296 * Set the capture broadcast bit to capture broadcast frames.
1298 if (ifp->if_flags & IFF_BROADCAST) {
1299 CSR_WRITE_4(sc, LGE_MODE1,
1300 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1302 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1305 /* Packet padding workaround? */
1306 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1308 /* No error frames */
1309 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1311 /* Receive large frames */
1312 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1314 /* Workaround: disable RX/TX flow control */
1315 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1316 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1318 /* Make sure to strip CRC from received frames */
1319 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1321 /* Turn off magic packet mode */
1322 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1324 /* Turn off all VLAN stuff */
1325 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1326 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1328 /* Workarond: FIFO overflow */
1329 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1330 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1333 * Load the multicast filter.
1338 * Enable hardware checksum validation for all received IPv4
1339 * packets, do not reject packets with bad checksums.
1341 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1342 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1343 LGE_MODE2_RX_ERRCSUM);
1346 * Enable the delivery of PHY interrupts based on
1347 * link/speed/duplex status chalges.
1349 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1351 /* Enable receiver and transmitter. */
1352 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1353 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1355 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1356 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1359 * Enable interrupts.
1361 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1362 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1364 lge_ifmedia_upd_locked(ifp);
1366 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1367 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1369 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc);
1375 * Set media options.
1378 lge_ifmedia_upd(ifp)
1381 struct lge_softc *sc;
1385 lge_ifmedia_upd_locked(ifp);
1392 lge_ifmedia_upd_locked(ifp)
1395 struct lge_softc *sc;
1396 struct mii_data *mii;
1397 struct mii_softc *miisc;
1401 LGE_LOCK_ASSERT(sc);
1402 mii = device_get_softc(sc->lge_miibus);
1404 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1410 * Report current media status.
1413 lge_ifmedia_sts(ifp, ifmr)
1415 struct ifmediareq *ifmr;
1417 struct lge_softc *sc;
1418 struct mii_data *mii;
1423 mii = device_get_softc(sc->lge_miibus);
1425 ifmr->ifm_active = mii->mii_media_active;
1426 ifmr->ifm_status = mii->mii_media_status;
1433 lge_ioctl(ifp, command, data)
1438 struct lge_softc *sc = ifp->if_softc;
1439 struct ifreq *ifr = (struct ifreq *) data;
1440 struct mii_data *mii;
1446 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1449 ifp->if_mtu = ifr->ifr_mtu;
1454 if (ifp->if_flags & IFF_UP) {
1455 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1456 ifp->if_flags & IFF_PROMISC &&
1457 !(sc->lge_if_flags & IFF_PROMISC)) {
1458 CSR_WRITE_4(sc, LGE_MODE1,
1459 LGE_MODE1_SETRST_CTL1|
1460 LGE_MODE1_RX_PROMISC);
1461 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1462 !(ifp->if_flags & IFF_PROMISC) &&
1463 sc->lge_if_flags & IFF_PROMISC) {
1464 CSR_WRITE_4(sc, LGE_MODE1,
1465 LGE_MODE1_RX_PROMISC);
1467 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1468 lge_init_locked(sc);
1471 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1474 sc->lge_if_flags = ifp->if_flags;
1487 mii = device_get_softc(sc->lge_miibus);
1488 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1491 error = ether_ioctl(ifp, command, data);
1500 struct lge_softc *sc;
1504 LGE_LOCK_ASSERT(sc);
1507 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1508 if_printf(ifp, "watchdog timeout\n");
1512 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1513 lge_init_locked(sc);
1515 if (ifp->if_snd.ifq_head != NULL)
1516 lge_start_locked(ifp);
1520 * Stop the adapter and free any mbufs allocated to the
1525 struct lge_softc *sc;
1530 LGE_LOCK_ASSERT(sc);
1533 callout_stop(&sc->lge_stat_callout);
1534 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1536 /* Disable receiver and transmitter. */
1537 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1541 * Free data in the RX lists.
1543 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1544 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1545 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1546 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1549 bzero((char *)&sc->lge_ldata->lge_rx_list,
1550 sizeof(sc->lge_ldata->lge_rx_list));
1553 * Free the TX list buffers.
1555 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1556 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1557 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1558 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1562 bzero((char *)&sc->lge_ldata->lge_tx_list,
1563 sizeof(sc->lge_ldata->lge_tx_list));
1565 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1571 * Stop all chip I/O so that the kernel's probe routines don't
1572 * get confused by errant DMAs when rebooting.
1578 struct lge_softc *sc;
1580 sc = device_get_softc(dev);