2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 2001 Wind River Systems
5 * Copyright (c) 1997, 1998, 1999, 2000, 2001
6 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
39 #define LGE_MODE1 0x00 /* CSR00 */
40 #define LGE_MODE2 0x04 /* CSR01 */
41 #define LGE_PPTXBUF_IDX 0x08 /* CSR02 */
42 #define LGE_PRODID 0x0C /* CSR03 */
43 #define LGE_PPTXBUF_ADDR_LO 0x10 /* CSR04 */
44 #define LGE_PPTXBUF_ADDR_HI 0x14 /* CSR05 */
45 #define LGE_RSVD0 0x18 /* CSR06 */
46 #define LGE_PPRXBUF_IDX 0x1C /* CSR07 */
47 #define LGE_PPRXBUF_ADDR_LO 0x20 /* CSR08 */
48 #define LGE_PPRXBUF_ADDR_HI 0x24 /* CSR09 */
49 #define LGE_EECTL 0x28 /* CSR10 */
50 #define LGE_CHIPSTS 0x2C /* CSR11 */
51 #define LGE_TXDESC_ADDR_LO 0x30 /* CSR12 */
52 #define LGE_TXDESC_ADDR_HI 0x34 /* CSR13 */
53 #define LGE_RXDESC_ADDR_LO 0x38 /* CSR14 */
54 #define LGE_RXDESC_ADDR_HI 0x3C /* CSR15 */
55 #define LGE_PPTXCTL 0x40 /* CSR16 */
56 #define LGE_PPRXCTL 0x44 /* CSR17 */
57 #define LGE_INTR_PERIOD 0x48 /* CSR18 */
58 #define LGE_TXFIFO_PKTCNT 0x4C /* CSR19 */
59 #define LGE_TXFIFO_LOWAT 0x50 /* CSR20 */
60 #define LGE_TXFIFO_FREEDWORDS 0x54 /* CSR21 */
61 #define LGE_TXFIFO_WRITE 0x58 /* CSR22 */
62 #define LGE_RSVD1 0x5C /* CSR23 */
63 #define LGE_RXFIFO_READ 0x60 /* CSR24 */
64 #define LGE_RSVD2 0x64 /* CSR25 */
65 #define LGE_RXFIFO_DWORDCNT 0x68 /* CSR26 */
66 #define LGE_RXFIFO_HIWAT 0x6C /* CSR27 */
67 #define LGE_RXFIFO_PKTCNT 0x70 /* CSR28 */
68 #define LGE_CMD 0x74 /* CSR29 */
69 #define LGE_IMR 0x78 /* CSR30 */
70 #define LGE_RSVD3 0x7C /* CSR31 */
71 #define LGE_ISR 0x80 /* CSR32 */
72 #define LGE_RSVD4 0x84 /* CSR33 */
73 #define LGE_MAR0 0x88 /* CSR34 */
74 #define LGE_MAR1 0x8C /* CSR35 */
75 #define LGE_LEDCFG0 0x90 /* CSR36 */
76 #define LGE_LEDCFG1 0x84 /* CSR37 */
77 #define LGE_LEDCFG2 0x98 /* CSR38 */
78 #define LGE_LEDCFG3 0x9C /* CSR39 */
79 #define LGE_RSVD5 0xA0 /* CSR40 */
80 #define LGE_EEDATA 0xA4 /* CSR41 */
81 #define LGE_PAR0 0xA8 /* CSR42 */
82 #define LGE_PAR1 0xAC /* CSR43 */
83 #define LGE_GMIICTL 0xB0 /* CSR44 */
84 #define LGE_GMIIMODE 0xB4 /* CSR45 */
85 #define LGE_STATSIDX 0xB8 /* CSR46 */
86 #define LGE_STATSVAL 0xBC /* CSR47 */
87 #define LGE_VLANCTL 0xC0 /* CSR48 */
88 #define LGE_RSVD6 0xC4 /* CSR49 */
89 #define LGE_RSVD7 0xC8 /* CSR50 */
90 #define LGE_CMDSTS 0xCC /* CSR51 */
91 #define LGE_FLOWCTL_WAT 0xD0 /* CSR52 */
92 #define LGE_RSVD8 0xD4 /* CSR53 */
93 #define LGE_RSVD9 0xD8 /* CSR54 */
94 #define LGE_RSVD10 0xDC /* CSR55 */
95 #define LGE_RSVD11 0xE0 /* CSR56 */
96 #define LGE_RSVD12 0xE4 /* CSR57 */
97 #define LGE_TIMER0_CNT 0xE8 /* CSR58 */
98 #define LGE_TIMER0_INT 0xEC /* CSR59 */
99 #define LGE_TIMER1_CNT 0xF0 /* CSR60 */
100 #define LGE_TIMER1_INT 0xF4 /* CSR61 */
101 #define LGE_DBG_CMD 0xF8 /* CSR62 */
102 #define LGE_DBG_DATA 0xFC /* CSR63 */
105 /* Mode register 1 */
106 #define LGE_MODE1_SETRST_CTL0 0x00000001
107 #define LGE_MODE1_SOFTRST 0x00000002
108 #define LGE_MODE1_DEBTOD 0x00000004 /* Not documented? */
109 #define LGE_MODE1_TX_FLOWCTL 0x00000008 /* Not documented? */
110 #define LGE_MODE1_RXTXRIO 0x00000010
111 #define LGE_MODE1_GMIIPOLL 0x00000020
112 #define LGE_MODE1_TXPAD 0x00000040
113 #define LGE_MODE1_RMVPAD 0x00000080 /* Not documented? */
114 #define LGE_MODE1_SETRST_CTL1 0x00000100
115 #define LGE_MODE1_TX_ENB 0x00000200
116 #define LGE_MODE1_RX_ENB 0x00000400
117 #define LGE_MODE1_RX_MCAST 0x00000800
118 #define LGE_MODE1_RX_BCAST 0x00001000
119 #define LGE_MODE1_RX_PROMISC 0x00002000
120 #define LGE_MODE1_RX_UCAST 0x00004000
121 #define LGE_MODE1_RX_GIANTS 0x00008000
122 #define LGE_MODE1_SETRST_CTL2 0x00010000
123 #define LGE_MODE1_RX_CRC 0x00020000
124 #define LGE_MODE1_RX_ERRPKTS 0x00040000
125 #define LGE_MODE1_TX_CRC 0x00080000
126 #define LGE_MODE1_DEMDEN 0x00100000 /* Not documented? */
127 #define LGE_MODE1_MPACK_ENB 0x00200000
128 #define LGE_MODE1_MPACK_BCAST 0x00400000
129 #define LGE_MODE1_RX_FLOWCTL 0x00800000
130 #define LGE_MODE1_SETRST_CTL3 0x01000000
131 #define LGE_MODE1_VLAN_RX 0x02000000
132 #define LGE_MODE1_VLAN_TX 0x04000000
133 #define LGE_MODE1_VLAN_STRIP 0x08000000
134 #define LGE_MODE1_VLAN_INSERT 0x10000000
135 #define LGE_MODE1_GPIO_CTL0 0x20000000
136 #define LGE_MODE1_GPIO_CTL1 0x40000000
137 #define LGE_MODE1_RX_LENCHK 0x80000000
140 /* Mode register 2 */
141 #define LGE_MODE2_LOOPBACK 0x000000E0
142 #define LGE_MODE2_RX_IPCSUM 0x00001000
143 #define LGE_MODE2_RX_TCPCSUM 0x00002000
144 #define LGE_MODE2_RX_UDPCSUM 0x00004000
145 #define LGE_MODE2_RX_ERRCSUM 0x00008000
148 /* EEPROM register */
149 #define LGE_EECTL_HAVE_EEPROM 0x00000001
150 #define LGE_EECTL_CMD_READ 0x00000002
151 #define LGE_EECTL_CMD_WRITE 0x00000004
152 #define LGE_EECTL_CSUMERR 0x00000010
153 #define LGE_EECTL_MULTIACCESS 0x00000020
154 #define LGE_EECTL_SINGLEACCESS 0x00000040
155 #define LGE_EECTL_ADDR 0x00001F00
156 #define LGE_EECTL_ROM_TIMING 0x000F0000
157 #define LGE_EECTL_HAVE_FLASH 0x00100000
158 #define LGE_EECTL_WRITEFLASH 0x00200000
160 #define LGE_EE_NODEADDR_0 0x12
161 #define LGE_EE_NODEADDR_1 0x13
162 #define LGE_EE_NODEADDR_2 0x10
165 /* Chip status register */
166 #define LGE_CHIPSTS_HAVETXSPC 0x00000001 /* have room in TX FIFO for pkt */
167 #define LGE_CHIPSTS_HAVERXPKT 0x00000002 /* RX FIFO holds complete pkt */
168 #define LGE_CHIPSTS_FLOWCTL_STS 0x00000004
169 #define LGE_CHIPSTS_GPIO_STS0 0x00000008
170 #define LGE_CHIPSTS_GPIO_STS1 0x00000010
171 #define LGE_CHIPSTS_TXIDLE 0x00000020
172 #define LGE_CHIPSTS_RXIDLE 0x00000040
175 /* TX PacketPropulsion control register */
176 #define LGE_PPTXCTL_BUFLEN 0x0000FFFF
177 #define LGE_PPTXCTL_BUFID 0x003F0000
178 #define LGE_PPTXCTL_WANTINTR 0x01000000
181 /* RX PacketPropulsion control register */
182 #define LGE_PPRXCTL_BUFLEN 0x0000FFFF
183 #define LGE_PPRXCTL_BUFID 0x003F0000
184 #define LGE_PPRXCTL_WANTINTR 0x10000000
187 /* Command register */
188 #define LGE_CMD_SETRST_CTL0 0x00000001
189 #define LGE_CMD_STARTTX 0x00000002
190 #define LGE_CMD_SKIP_RXPKT 0x00000004
191 #define LGE_CMD_DEL_INTREQ 0x00000008
192 #define LGE_CMD_PER_INTREQ 0x00000010
193 #define LGE_CMD_TIMER0 0x00000020
194 #define LGE_CMD_TIMER1 0x00000040
197 /* Interrupt mask register */
198 #define LGE_IMR_SETRST_CTL0 0x00000001
199 #define LGE_IMR_TXCMDFIFO_EMPTY 0x00000002
200 #define LGE_IMR_TXFIFO_WAT 0x00000004
201 #define LGE_IMR_TXDMA_DONE 0x00000008
202 #define LGE_IMR_DELAYEDINTR 0x00000040
203 #define LGE_IMR_INTR_ENB 0x00000080
204 #define LGE_IMR_SETRST_CTL1 0x00000100
205 #define LGE_IMR_RXCMDFIFO_EMPTY 0x00000200
206 #define LGE_IMR_RXFIFO_WAT 0x00000400
207 #define LGE_IMR_RX_DONE 0x00000800
208 #define LGE_IMR_RXDMA_DONE 0x00001000
209 #define LGE_IMR_PHY_INTR 0x00002000
210 #define LGE_IMR_MAGICPKT 0x00004000
211 #define LGE_IMR_SETRST_CTL2 0x00010000
212 #define LGE_IMR_GPIO0 0x00020000
213 #define LGE_IMR_GPIO1 0x00040000
214 #define LGE_IMR_TIMER0 0x00080000
215 #define LGE_IMR_TIMER1 0x00100000
219 (LGE_IMR_TXCMDFIFO_EMPTY|LGE_IMR_TXDMA_DONE|LGE_IMR_RX_DONE| \
220 LGE_IMR_RXCMDFIFO_EMPTY|LGE_IMR_RXDMA_DONE|LGE_IMR_PHY_INTR)
223 /* Interrupt status register */
224 #define LGE_ISR_TXCMDFIFO_EMPTY 0x00000002
225 #define LGE_ISR_TXFIFO_WAT 0x00000004
226 #define LGE_ISR_TXDMA_DONE 0x00000008
227 #define LGE_ISR_DELAYEDINTR 0x00000040
228 #define LGE_ISR_INTR_ENB 0x00000080
229 #define LGE_ISR_RXCMDFIFO_EMPTY 0x00000200
230 #define LGE_ISR_RXFIFO_WAT 0x00000400
231 #define LGE_ISR_RX_DONE 0x00000800
232 #define LGE_ISR_RXDMA_DONE 0x00001000
233 #define LGE_ISR_PHY_INTR 0x00002000
234 #define LGE_ISR_MAGICPKT 0x00004000
235 #define LGE_ISR_GPIO0 0x00020000
236 #define LGE_ISR_GPIO1 0x00040000
237 #define LGE_ISR_TIMER0 0x00080000
238 #define LGE_ISR_TIMER1 0x00100000
239 #define LGE_ISR_RXDMADONE_CNT 0xFF000000
240 #define LGE_RX_DMACNT(x) ((x & LGE_ISR_RXDMADONE_CNT) >> 24)
242 /* LED0 config register */
243 #define LGE_LED0CFG_ENABLE 0x00000002
244 #define LGE_LED0CFG_INPUT_POL 0x00000004
245 #define LGE_LED0CFG_PULSE_EXP 0x00000008
246 #define LGE_LED0CFG_10MBPS 0x00000010
247 #define LGE_LED0CFG_100MBPS 0x00000100
248 #define LGE_LED0CFG_1000MBPS 0x00000200
249 #define LGE_LED0CFG_FDX 0x00000400
250 #define LGE_LED0CFG_ANEG 0x00000800
251 #define LGE_LED0CFG_LINKSTS 0x00001000
252 #define LGE_LED0CFG_RXMATCH 0x00002000
253 #define LGE_LED0CFG_TX 0x00004000
254 #define LGE_LED0CFG_RX 0x00008000
255 #define LGE_LED0CFG_JABBER 0x00010000
256 #define LGE_LED0CFG_COLLISION 0x00020000
257 #define LGE_LED0CFG_CARRIER 0x00040000
258 #define LGE_LED0CFG_LEDOUT 0x10000000
261 /* LED1 config register */
262 #define LGE_LED1CFG_ENABLE 0x00000002
263 #define LGE_LED1CFG_INPUT_POL 0x00000004
264 #define LGE_LED1CFG_PULSE_EXP 0x00000008
265 #define LGE_LED1CFG_10MBPS 0x00000010
266 #define LGE_LED1CFG_100MBPS 0x00000100
267 #define LGE_LED1CFG_1000MBPS 0x00000200
268 #define LGE_LED1CFG_FDX 0x00000400
269 #define LGE_LED1CFG_ANEG 0x00000800
270 #define LGE_LED1CFG_LINKSTS 0x00001000
271 #define LGE_LED1CFG_RXMATCH 0x00002000
272 #define LGE_LED1CFG_TX 0x00004000
273 #define LGE_LED1CFG_RX 0x00008000
274 #define LGE_LED1CFG_JABBER 0x00010000
275 #define LGE_LED1CFG_COLLISION 0x00020000
276 #define LGE_LED1CFG_CARRIER 0x00040000
277 #define LGE_LED1CFG_LEDOUT 0x10000000
280 /* LED2 config register */
281 #define LGE_LED2CFG_ENABLE 0x00000002
282 #define LGE_LED2CFG_INPUT_POL 0x00000004
283 #define LGE_LED2CFG_PULSE_EXP 0x00000008
284 #define LGE_LED2CFG_10MBPS 0x00000010
285 #define LGE_LED2CFG_100MBPS 0x00000100
286 #define LGE_LED2CFG_1000MBPS 0x00000200
287 #define LGE_LED2CFG_FDX 0x00000400
288 #define LGE_LED2CFG_ANEG 0x00000800
289 #define LGE_LED2CFG_LINKSTS 0x00001000
290 #define LGE_LED2CFG_RXMATCH 0x00002000
291 #define LGE_LED2CFG_TX 0x00004000
292 #define LGE_LED2CFG_RX 0x00008000
293 #define LGE_LED2CFG_JABBER 0x00010000
294 #define LGE_LED2CFG_COLLISION 0x00020000
295 #define LGE_LED2CFG_CARRIER 0x00040000
296 #define LGE_LED2CFG_LEDOUT 0x10000000
299 /* GMII PHY access register */
300 #define LGE_GMIICTL_PHYREG 0x0000001F
301 #define LGE_GMIICTL_CMD 0x00000080
302 #define LGE_GMIICTL_PHYADDR 0x00001F00
303 #define LGE_GMIICTL_CMDBUSY 0x00008000
304 #define LGE_GMIICTL_DATA 0xFFFF0000
306 #define LGE_GMIICMD_READ 0x00000000
307 #define LGE_GMIICMD_WRITE 0x00000080
309 /* GMII PHY mode register */
310 #define LGE_GMIIMODE_SPEED 0x00000003
311 #define LGE_GMIIMODE_FDX 0x00000004
312 #define LGE_GMIIMODE_PROTSEL 0x00000100 /* 0 == GMII, 1 == TBI */
313 #define LGE_GMIIMODE_PCSENH 0x00000200
315 #define LGE_SPEED_10 0x00000000
316 #define LGE_SPEED_100 0x00000001
317 #define LGE_SPEED_1000 0x00000002
320 /* VLAN tag control register */
321 #define LGE_VLANCTL_VLID 0x00000FFF
322 #define LGE_VLANCTL_USERPRIO 0x0000E000
323 #define LGE_VLANCTL_TCI_IDX 0x000D0000
324 #define LGE_VLANCTL_TBLCMD 0x00200000
327 /* Command status register */
328 #define LGE_CMDSTS_TXDMADONE 0x000000FF
329 #define LGE_CMDSTS_RXDMADONE 0x0000FF00
330 #define LGE_CMDSTS_TXCMDFREE 0x003F0000
331 #define LGE_CMDSTS_RXCMDFREE 0x3F000000
333 #define LGE_TXDMADONE_8BIT LGE_CMDSTS
334 #define LGE_RXDMADONE_8BIT (LGE_CMDSTS + 1)
335 #define LGE_TXCMDFREE_8BIT (LGE_CMDSTS + 2)
336 #define LGE_RXCMDFREE_8BIT (LGE_CMDSTS + 3)
338 #define LGE_MAXCMDS 31
340 /* Index for statistics counters. */
341 #define LGE_STATS_TX_PKTS_OK 0x00
342 #define LGE_STATS_SINGLE_COLL_PKTS 0x01
343 #define LGE_STATS_MULTI_COLL_PKTS 0x02
344 #define LGE_STATS_RX_PKTS_OK 0x03
345 #define LGE_STATS_FCS_ERRS 0x04
346 #define LGE_STATS_ALIGN_ERRS 0x05
347 #define LGE_STATS_DROPPED_PKTS 0x06
348 #define LGE_STATS_RX_ERR_PKTS 0x07
349 #define LGE_STATS_TX_ERR_PKTS 0x08
350 #define LGE_STATS_LATE_COLLS 0x09
351 #define LGE_STATS_RX_RUNTS 0x0A
352 #define LGE_STATS_RX_GIANTS 0x0B
353 #define LGE_STATS_VLAN_PKTS_ACCEPT 0x0C
354 #define LGE_STATS_VLAN_PKTS_REJECT 0x0D
355 #define LGE_STATS_IP_CSUM_ERR 0x0E
356 #define LGE_STATS_UDP_CSUM_ERR 0x0F
357 #define LGE_STATS_RANGELEN_ERRS 0x10
358 #define LGE_STATS_TCP_CSUM_ERR 0x11
359 #define LGE_STATS_RSVD0 0x12
360 #define LGE_STATS_TX_EXCESS_COLLS 0x13
361 #define LGE_STATS_RX_UCASTS 0x14
362 #define LGE_STATS_RX_MCASTS 0x15
363 #define LGE_STATS_RX_BCASTS 0x16
364 #define LGE_STATS_RX_PAUSE_PKTS 0x17
365 #define LGE_STATS_TX_PAUSE_PKTS 0x18
366 #define LGE_STATS_TX_PKTS_DEFERRED 0x19
367 #define LGE_STATS_TX_EXCESS_DEFER 0x1A
368 #define LGE_STATS_CARRIER_SENSE_ERR 0x1B
372 * RX and TX DMA descriptor structures for scatter/gather.
373 * Each descriptor can have up to 31 fragments in it, however for
374 * RX we only need one fragment, and for transmit we only allocate
375 * 10 in order to reduce the amount of space we need for the
377 * Note: descriptor structures must be 64-bit aligned.
381 /* Hardware descriptor section */
384 u_int32_t lge_fragptr_lo;
385 u_int32_t lge_fragptr_hi;
386 u_int16_t lge_fraglen;
389 /* Driver software section */
391 struct mbuf *lge_mbuf;
398 u_int32_t lge_fragptr_lo;
399 u_int32_t lge_fragptr_hi;
400 u_int16_t lge_fraglen;
405 /* Hardware descriptor section */
407 struct lge_frag lge_frags[10];
410 struct mbuf *lge_mbuf;
415 #define lge_mbuf lge_u.lge_mbuf
417 #define LGE_RXCTL_BUFLEN 0x0000FFFF
418 #define LGE_RXCTL_FRAGCNT 0x001F0000
419 #define LGE_RXCTL_LENERR 0x00400000
420 #define LGE_RXCTL_UCAST 0x00800000
421 #define LGR_RXCTL_BCAST 0x01000000
422 #define LGE_RXCTL_MCAST 0x02000000
423 #define LGE_RXCTL_GIANT 0x04000000
424 #define LGE_RXCTL_OFLOW 0x08000000
425 #define LGE_RXCTL_CRCERR 0x10000000
426 #define LGE_RXCTL_RUNT 0x20000000
427 #define LGE_RXCTL_ALGNERR 0x40000000
428 #define LGE_RXCTL_WANTINTR 0x80000000
430 #define LGE_RXCTL_ERRMASK \
431 (LGE_RXCTL_LENERR|LGE_RXCTL_OFLOW| \
432 LGE_RXCTL_CRCERR|LGE_RXCTL_RUNT| \
435 #define LGE_RXSTS_VLTBIDX 0x0000000F
436 #define LGE_RXSTS_VLTBLHIT 0x00000010
437 #define LGE_RXSTS_IPCSUMERR 0x00000100
438 #define LGE_RXSTS_TCPCSUMERR 0x00000200
439 #define LGE_RXSTS_UDPCSUMERR 0x00000400
440 #define LGE_RXSTS_ISIP 0x00000800
441 #define LGE_RXSTS_ISTCP 0x00001000
442 #define LGE_RXSTS_ISUDP 0x00002000
444 #define LGE_TXCTL_BUFLEN 0x0000FFFF
445 #define LGE_TXCTL_FRAGCNT 0x001F0000
446 #define LGE_TXCTL_VLTBIDX 0x0F000000
447 #define LGE_TXCTL_VLIS 0x10000000
448 #define LGE_TXCTL_WANTINTR 0x80000000
450 #define LGE_INC(x, y) (x) = (x + 1) % y
451 #define LGE_FRAGCNT_1 (1<<16)
452 #define LGE_FRAGCNT_10 (10<<16)
453 #define LGE_FRAGCNT(x) (x<<16)
454 #define LGE_RXBYTES(x) (x->lge_ctl & 0xFFFF)
455 #define LGE_RXTAIL(x) \
456 (x->lge_ldata->lge_rx_list[x->lge_cdata.lge_rx_prod])
458 #define LGE_RX_LIST_CNT 64
459 #define LGE_TX_LIST_CNT 128
461 struct lge_list_data {
462 struct lge_rx_desc lge_rx_list[LGE_RX_LIST_CNT];
463 struct lge_tx_desc lge_tx_list[LGE_TX_LIST_CNT];
468 * Level 1 PCI vendor ID.
470 #define LGE_VENDORID 0x1394
473 * LXT 1001 PCI device IDs
475 #define LGE_DEVICEID 0x0001
480 const char *lge_name;
483 #define LGE_JUMBO_FRAMELEN 9018
484 #define LGE_JUMBO_MTU (LGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
485 #define LGE_JSLOTS 384
487 #define LGE_JRAWLEN (LGE_JUMBO_FRAMELEN + ETHER_ALIGN)
488 #define LGE_JLEN (LGE_JRAWLEN + (sizeof(u_int64_t) - \
489 (LGE_JRAWLEN % sizeof(u_int64_t))))
490 #define LGE_JPAGESZ PAGE_SIZE
491 #define LGE_RESID (LGE_JPAGESZ - (LGE_JLEN * LGE_JSLOTS) % LGE_JPAGESZ)
492 #define LGE_JMEM ((LGE_JLEN * LGE_JSLOTS) + LGE_RESID)
494 struct lge_jpool_entry {
496 SLIST_ENTRY(lge_jpool_entry) jpool_entries;
499 struct lge_ring_data {
504 /* Stick the jumbo mem management stuff here too. */
505 caddr_t lge_jslots[LGE_JSLOTS];
510 struct ifnet *lge_ifp;
512 bus_space_handle_t lge_bhandle;
513 bus_space_tag_t lge_btag;
514 struct resource *lge_res;
515 struct resource *lge_irq;
523 struct lge_list_data *lge_ldata;
524 struct lge_ring_data lge_cdata;
525 struct callout lge_stat_callout;
527 SLIST_HEAD(__lge_jfreehead, lge_jpool_entry) lge_jfree_listhead;
528 SLIST_HEAD(__lge_jinusehead, lge_jpool_entry) lge_jinuse_listhead;
532 * register space access macros
534 #define CSR_WRITE_4(sc, reg, val) \
535 bus_space_write_4(sc->lge_btag, sc->lge_bhandle, reg, val)
537 #define CSR_READ_2(sc, reg) \
538 bus_space_read_2(sc->lge_btag, sc->lge_bhandle, reg)
540 #define CSR_WRITE_2(sc, reg, val) \
541 bus_space_write_2(sc->lge_btag, sc->lge_bhandle, reg, val)
543 #define CSR_READ_4(sc, reg) \
544 bus_space_read_4(sc->lge_btag, sc->lge_bhandle, reg)
546 #define CSR_WRITE_1(sc, reg, val) \
547 bus_space_write_1(sc->lge_btag, sc->lge_bhandle, reg, val)
549 #define CSR_READ_1(sc, reg) \
550 bus_space_read_1(sc->lge_btag, sc->lge_bhandle, reg)
552 #define LGE_LOCK(sc) mtx_lock(&(sc)->lge_mtx)
553 #define LGE_UNLOCK(sc) mtx_unlock(&(sc)->lge_mtx)
554 #define LGE_LOCK_ASSERT(sc) mtx_assert(&(sc)->lge_mtx, MA_OWNED)
556 #define LGE_TIMEOUT 1000
557 #define LGE_RXLEN 1536
558 #define LGE_MIN_FRAMELEN 60
561 * PCI low memory base and low I/O base register, and
562 * other PCI registers.
565 #define LGE_PCI_VENDOR_ID 0x00
566 #define LGE_PCI_DEVICE_ID 0x02
567 #define LGE_PCI_COMMAND 0x04
568 #define LGE_PCI_STATUS 0x06
569 #define LGE_PCI_REVID 0x08
570 #define LGE_PCI_CLASSCODE 0x09
571 #define LGE_PCI_CACHELEN 0x0C
572 #define LGE_PCI_LATENCY_TIMER 0x0D
573 #define LGE_PCI_HEADER_TYPE 0x0E
574 #define LGE_PCI_LOIO 0x10
575 #define LGE_PCI_LOMEM 0x14
576 #define LGE_PCI_BIOSROM 0x30
577 #define LGE_PCI_INTLINE 0x3C
578 #define LGE_PCI_INTPIN 0x3D
579 #define LGE_PCI_MINGNT 0x3E
580 #define LGE_PCI_MINLAT 0x0F
581 #define LGE_PCI_RESETOPT 0x48
582 #define LGE_PCI_EEPROM_DATA 0x4C
584 /* power management registers */
585 #define LGE_PCI_CAPID 0x50 /* 8 bits */
586 #define LGE_PCI_NEXTPTR 0x51 /* 8 bits */
587 #define LGE_PCI_PWRMGMTCAP 0x52 /* 16 bits */
588 #define LGE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
590 #define LGE_PSTATE_MASK 0x0003
591 #define LGE_PSTATE_D0 0x0000
592 #define LGE_PSTATE_D1 0x0001
593 #define LGE_PSTATE_D2 0x0002
594 #define LGE_PSTATE_D3 0x0003
595 #define LGE_PME_EN 0x0010
596 #define LGE_PME_STATUS 0x8000