4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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15 * the documentation and/or other materials provided with the
17 * * Neither the name of Cavium, Inc. nor the names of its
18 * contributors may be used to endorse or promote products derived
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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36 #include "lio_common.h"
39 #include "lio_response_manager.h"
40 #include "lio_device.h"
41 #include "cn23xx_pf_device.h"
46 lio_cn23xx_pf_soft_reset(struct octeon_device *oct)
49 lio_write_csr64(oct, LIO_CN23XX_SLI_WIN_WR_MASK_REG, 0xFF);
51 lio_dev_dbg(oct, "BIST enabled for CN23XX soft reset\n");
53 lio_write_csr64(oct, LIO_CN23XX_SLI_SCRATCH1, 0x1234ULL);
55 /* Initiate chip-wide soft reset */
56 lio_pci_readq(oct, LIO_CN23XX_RST_SOFT_RST);
57 lio_pci_writeq(oct, 1, LIO_CN23XX_RST_SOFT_RST);
59 /* Wait for 100ms as Octeon resets. */
62 if (lio_read_csr64(oct, LIO_CN23XX_SLI_SCRATCH1)) {
63 lio_dev_err(oct, "Soft reset failed\n");
67 lio_dev_dbg(oct, "Reset completed\n");
69 /* restore the reset value */
70 lio_write_csr64(oct, LIO_CN23XX_SLI_WIN_WR_MASK_REG, 0xFF);
76 lio_cn23xx_pf_enable_error_reporting(struct octeon_device *oct)
78 uint32_t corrtable_err_status, uncorrectable_err_mask, regval;
80 regval = lio_read_pci_cfg(oct, LIO_CN23XX_CFG_PCIE_DEVCTL);
81 if (regval & LIO_CN23XX_CFG_PCIE_DEVCTL_MASK) {
82 uncorrectable_err_mask = 0;
83 corrtable_err_status = 0;
84 uncorrectable_err_mask =
86 LIO_CN23XX_CFG_PCIE_UNCORRECT_ERR_MASK);
87 corrtable_err_status =
89 LIO_CN23XX_CFG_PCIE_CORRECT_ERR_STATUS);
90 lio_dev_err(oct, "PCI-E Fatal error detected;\n"
91 "\tdev_ctl_status_reg = 0x%08x\n"
92 "\tuncorrectable_error_mask_reg = 0x%08x\n"
93 "\tcorrectable_error_status_reg = 0x%08x\n",
94 regval, uncorrectable_err_mask,
95 corrtable_err_status);
98 regval |= 0xf; /* Enable Link error reporting */
100 lio_dev_dbg(oct, "Enabling PCI-E error reporting..\n");
101 lio_write_pci_cfg(oct, LIO_CN23XX_CFG_PCIE_DEVCTL, regval);
105 lio_cn23xx_pf_coprocessor_clock(struct octeon_device *oct)
108 * Bits 29:24 of RST_BOOT[PNR_MUL] holds the ref.clock MULTIPLIER
112 /* TBD: get the info in Hand-shake */
113 return (((lio_pci_readq(oct, LIO_CN23XX_RST_BOOT) >> 24) & 0x3f) * 50);
117 lio_cn23xx_pf_get_oq_ticks(struct octeon_device *oct, uint32_t time_intr_in_us)
119 /* This gives the SLI clock per microsec */
120 uint32_t oqticks_per_us = lio_cn23xx_pf_coprocessor_clock(oct);
122 oct->pfvf_hsword.coproc_tics_per_us = oqticks_per_us;
124 /* This gives the clock cycles per millisecond */
125 oqticks_per_us *= 1000;
127 /* This gives the oq ticks (1024 core clock cycles) per millisecond */
128 oqticks_per_us /= 1024;
131 * time_intr is in microseconds. The next 2 steps gives the oq ticks
132 * corresponding to time_intr.
134 oqticks_per_us *= time_intr_in_us;
135 oqticks_per_us /= 1000;
137 return (oqticks_per_us);
141 lio_cn23xx_pf_setup_global_mac_regs(struct octeon_device *oct)
144 uint16_t mac_no = oct->pcie_port;
145 uint16_t pf_num = oct->pf_num;
146 /* programming SRN and TRS for each MAC(0..3) */
148 lio_dev_dbg(oct, "%s: Using pcie port %d\n", __func__, mac_no);
149 /* By default, mapping all 64 IOQs to a single MACs */
152 lio_read_csr64(oct, LIO_CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num));
154 /* setting SRN <6:0> */
155 reg_val = pf_num * LIO_CN23XX_PF_MAX_RINGS;
157 /* setting TRS <23:16> */
159 (oct->sriov_info.trs << LIO_CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS);
161 /* write these settings to MAC register */
162 lio_write_csr64(oct, LIO_CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num),
165 lio_dev_dbg(oct, "SLI_PKT_MAC(%d)_PF(%d)_RINFO : 0x%016llx\n", mac_no,
167 LIO_CAST64(lio_read_csr64(oct,
168 LIO_CN23XX_SLI_PKT_MAC_RINFO64(mac_no,
173 lio_cn23xx_pf_reset_io_queues(struct octeon_device *oct)
176 uint32_t ern, loop = BUSY_READING_REG_PF_LOOP_COUNT;
180 srn = oct->sriov_info.pf_srn;
181 ern = srn + oct->sriov_info.num_pf_rings;
183 /* As per HRM reg description, s/w cant write 0 to ENB. */
184 /* to make the queue off, need to set the RST bit. */
186 /* Reset the Enable bit for all the 64 IQs. */
187 for (q_no = srn; q_no < ern; q_no++) {
188 /* set RST bit to 1. This bit applies to both IQ and OQ */
189 d64 = lio_read_csr64(oct,
190 LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
191 d64 = d64 | LIO_CN23XX_PKT_INPUT_CTL_RST;
193 LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no), d64);
196 /* wait until the RST bit is clear or the RST and quiet bits are set */
197 for (q_no = srn; q_no < ern; q_no++) {
198 volatile uint64_t reg_val =
200 LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
201 while ((reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) &&
202 !(reg_val & LIO_CN23XX_PKT_INPUT_CTL_QUIET) &&
204 reg_val = lio_read_csr64(oct,
205 LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
211 "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n",
216 reg_val &= ~LIO_CN23XX_PKT_INPUT_CTL_RST;
217 lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
220 reg_val = lio_read_csr64(oct,
221 LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
222 if (reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) {
223 lio_dev_err(oct, "clearing the reset failed for qno: %u\n",
233 lio_cn23xx_pf_setup_global_input_regs(struct octeon_device *oct)
235 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip;
236 struct lio_instr_queue *iq;
237 uint64_t intr_threshold;
238 uint64_t pf_num, reg_val;
239 uint32_t q_no, ern, srn;
241 pf_num = oct->pf_num;
243 srn = oct->sriov_info.pf_srn;
244 ern = srn + oct->sriov_info.num_pf_rings;
246 if (lio_cn23xx_pf_reset_io_queues(oct))
250 * Set the MAC_NUM and PVF_NUM in IQ_PKT_CONTROL reg
251 * for all queues.Only PF can set these bits.
252 * bits 29:30 indicate the MAC num.
253 * bits 32:47 indicate the PVF num.
255 for (q_no = 0; q_no < ern; q_no++) {
256 reg_val = oct->pcie_port <<
257 LIO_CN23XX_PKT_INPUT_CTL_MAC_NUM_POS;
259 reg_val |= pf_num << LIO_CN23XX_PKT_INPUT_CTL_PF_NUM_POS;
261 lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
266 * Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for
269 for (q_no = srn; q_no < ern; q_no++) {
270 uint32_t inst_cnt_reg;
272 iq = oct->instr_queue[q_no];
274 inst_cnt_reg = iq->inst_cnt_reg;
276 inst_cnt_reg = LIO_CN23XX_SLI_IQ_INSTR_COUNT64(q_no);
279 lio_read_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
281 reg_val |= LIO_CN23XX_PKT_INPUT_CTL_MASK;
283 lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
286 /* Set WMARK level for triggering PI_INT */
287 /* intr_threshold = LIO_CN23XX_DEF_IQ_INTR_THRESHOLD & */
288 intr_threshold = LIO_GET_IQ_INTR_PKT_CFG(cn23xx->conf) &
289 LIO_CN23XX_PKT_IN_DONE_WMARK_MASK;
291 lio_write_csr64(oct, inst_cnt_reg,
292 (lio_read_csr64(oct, inst_cnt_reg) &
293 ~(LIO_CN23XX_PKT_IN_DONE_WMARK_MASK <<
294 LIO_CN23XX_PKT_IN_DONE_WMARK_BIT_POS)) |
296 LIO_CN23XX_PKT_IN_DONE_WMARK_BIT_POS));
302 lio_cn23xx_pf_setup_global_output_regs(struct octeon_device *oct)
304 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip;
305 uint64_t time_threshold;
306 uint32_t ern, q_no, reg_val, srn;
308 srn = oct->sriov_info.pf_srn;
309 ern = srn + oct->sriov_info.num_pf_rings;
311 if (LIO_GET_IS_SLI_BP_ON_CFG(cn23xx->conf)) {
312 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_WMARK, 32);
314 /* Set Output queue watermark to 0 to disable backpressure */
315 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_WMARK, 0);
318 for (q_no = srn; q_no < ern; q_no++) {
319 reg_val = lio_read_csr32(oct,
320 LIO_CN23XX_SLI_OQ_PKT_CONTROL(q_no));
322 /* set IPTR & DPTR */
323 reg_val |= LIO_CN23XX_PKT_OUTPUT_CTL_DPTR;
326 reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_BMODE);
329 * No Relaxed Ordering, No Snoop, 64-bit Byte swap for
330 * Output Queue ScatterList reset ROR_P, NSR_P
332 reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_ROR_P);
333 reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_NSR_P);
335 #if BYTE_ORDER == LITTLE_ENDIAN
336 reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_ES_P);
337 #else /* BYTE_ORDER != LITTLE_ENDIAN */
338 reg_val |= (LIO_CN23XX_PKT_OUTPUT_CTL_ES_P);
339 #endif /* BYTE_ORDER == LITTLE_ENDIAN */
342 * No Relaxed Ordering, No Snoop, 64-bit Byte swap for
343 * Output Queue Data reset ROR, NSR
345 reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_ROR);
346 reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_NSR);
348 reg_val |= (LIO_CN23XX_PKT_OUTPUT_CTL_ES);
350 /* write all the selected settings */
351 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(q_no),
355 * Enabling these interrupt in oct->fn_list.enable_interrupt()
356 * routine which called after IOQ init.
357 * Set up interrupt packet and time thresholds
360 time_threshold =lio_cn23xx_pf_get_oq_ticks(
361 oct, (uint32_t)LIO_GET_OQ_INTR_TIME_CFG(cn23xx->conf));
363 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no),
364 (LIO_GET_OQ_INTR_PKT_CFG(cn23xx->conf) |
365 (time_threshold << 32)));
368 /* Setting the water mark level for pko back pressure * */
369 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_WMARK, 0x40);
371 /* Enable channel-level backpressure */
373 lio_write_csr64(oct, LIO_CN23XX_SLI_OUT_BP_EN2_W1S,
374 0xffffffffffffffffULL);
376 lio_write_csr64(oct, LIO_CN23XX_SLI_OUT_BP_EN_W1S,
377 0xffffffffffffffffULL);
381 lio_cn23xx_pf_setup_device_regs(struct octeon_device *oct)
384 lio_cn23xx_pf_enable_error_reporting(oct);
386 /* program the MAC(0..3)_RINFO before setting up input/output regs */
387 lio_cn23xx_pf_setup_global_mac_regs(oct);
389 if (lio_cn23xx_pf_setup_global_input_regs(oct))
392 lio_cn23xx_pf_setup_global_output_regs(oct);
395 * Default error timeout value should be 0x200000 to avoid host hang
396 * when reads invalid register
398 lio_write_csr64(oct, LIO_CN23XX_SLI_WINDOW_CTL,
399 LIO_CN23XX_SLI_WINDOW_CTL_DEFAULT);
401 /* set SLI_PKT_IN_JABBER to handle large VXLAN packets */
402 lio_write_csr64(oct, LIO_CN23XX_SLI_PKT_IN_JABBER,
403 LIO_CN23XX_MAX_INPUT_JABBER);
408 lio_cn23xx_pf_setup_iq_regs(struct octeon_device *oct, uint32_t iq_no)
410 struct lio_instr_queue *iq = oct->instr_queue[iq_no];
411 uint64_t pkt_in_done;
413 iq_no += oct->sriov_info.pf_srn;
415 /* Write the start of the input queue's ring and its size */
416 lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_BASE_ADDR64(iq_no),
418 lio_write_csr32(oct, LIO_CN23XX_SLI_IQ_SIZE(iq_no), iq->max_count);
421 * Remember the doorbell & instruction count register addr
424 iq->doorbell_reg = LIO_CN23XX_SLI_IQ_DOORBELL(iq_no);
425 iq->inst_cnt_reg = LIO_CN23XX_SLI_IQ_INSTR_COUNT64(iq_no);
426 lio_dev_dbg(oct, "InstQ[%d]:dbell reg @ 0x%x instcnt_reg @ 0x%x\n",
427 iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
430 * Store the current instruction counter (used in flush_iq
433 pkt_in_done = lio_read_csr64(oct, iq->inst_cnt_reg);
436 /* Set CINT_ENB to enable IQ interrupt */
437 lio_write_csr64(oct, iq->inst_cnt_reg,
438 (pkt_in_done | LIO_CN23XX_INTR_CINT_ENB));
441 * Clear the count by writing back what we read, but don't
444 lio_write_csr64(oct, iq->inst_cnt_reg, pkt_in_done);
447 iq->reset_instr_cnt = 0;
451 lio_cn23xx_pf_setup_oq_regs(struct octeon_device *oct, uint32_t oq_no)
453 struct lio_droq *droq = oct->droq[oq_no];
454 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip;
455 uint64_t cnt_threshold;
456 uint64_t time_threshold;
459 oq_no += oct->sriov_info.pf_srn;
461 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_BASE_ADDR64(oq_no),
462 droq->desc_ring_dma);
463 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_SIZE(oq_no), droq->max_count);
465 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq_no),
468 /* pkt_sent and pkts_credit regs */
469 droq->pkts_sent_reg = LIO_CN23XX_SLI_OQ_PKTS_SENT(oq_no);
470 droq->pkts_credit_reg = LIO_CN23XX_SLI_OQ_PKTS_CREDIT(oq_no);
474 * Enable this output queue to generate Packet Timer
478 lio_read_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq_no));
479 reg_val |= LIO_CN23XX_PKT_OUTPUT_CTL_TENB;
480 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq_no),
484 * Enable this output queue to generate Packet Count
488 lio_read_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq_no));
489 reg_val |= LIO_CN23XX_PKT_OUTPUT_CTL_CENB;
490 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq_no),
493 time_threshold = lio_cn23xx_pf_get_oq_ticks(oct,
494 (uint32_t)LIO_GET_OQ_INTR_TIME_CFG(cn23xx->conf));
495 cnt_threshold = (uint32_t)LIO_GET_OQ_INTR_PKT_CFG(cn23xx->conf);
497 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_PKT_INT_LEVELS(oq_no),
498 ((time_threshold << 32 | cnt_threshold)));
504 lio_cn23xx_pf_enable_io_queues(struct octeon_device *oct)
507 uint32_t ern, loop = BUSY_READING_REG_PF_LOOP_COUNT;
510 srn = oct->sriov_info.pf_srn;
511 ern = srn + oct->num_iqs;
513 for (q_no = srn; q_no < ern; q_no++) {
514 /* set the corresponding IQ IS_64B bit */
515 if (oct->io_qmask.iq64B & BIT_ULL(q_no - srn)) {
516 reg_val = lio_read_csr64(oct,
517 LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
518 reg_val = reg_val | LIO_CN23XX_PKT_INPUT_CTL_IS_64B;
520 LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
523 /* set the corresponding IQ ENB bit */
524 if (oct->io_qmask.iq & BIT_ULL(q_no - srn)) {
526 * IOQs are in reset by default in PEM2 mode,
529 reg_val = lio_read_csr64(oct,
530 LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
532 if (reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) {
534 LIO_CN23XX_PKT_INPUT_CTL_RST) &&
536 LIO_CN23XX_PKT_INPUT_CTL_QUIET) &&
538 reg_val = lio_read_csr64(oct,
539 LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
543 lio_dev_err(oct, "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n",
548 ~LIO_CN23XX_PKT_INPUT_CTL_RST;
550 LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
553 reg_val = lio_read_csr64(oct,
554 LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
555 if (reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) {
556 lio_dev_err(oct, "clearing the reset failed for qno: %u\n",
561 reg_val = lio_read_csr64(oct,
562 LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
563 reg_val = reg_val | LIO_CN23XX_PKT_INPUT_CTL_RING_ENB;
565 LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
569 for (q_no = srn; q_no < ern; q_no++) {
571 /* set the corresponding OQ ENB bit */
572 if (oct->io_qmask.oq & BIT_ULL(q_no - srn)) {
573 reg_val = lio_read_csr32(oct,
574 LIO_CN23XX_SLI_OQ_PKT_CONTROL(q_no));
575 reg_val = reg_val | LIO_CN23XX_PKT_OUTPUT_CTL_RING_ENB;
577 LIO_CN23XX_SLI_OQ_PKT_CONTROL(q_no),
585 lio_cn23xx_pf_disable_io_queues(struct octeon_device *oct)
587 volatile uint64_t d64;
588 volatile uint32_t d32;
593 srn = oct->sriov_info.pf_srn;
594 ern = srn + oct->num_iqs;
596 /* Disable Input Queues. */
597 for (q_no = srn; q_no < ern; q_no++) {
598 loop = lio_ms_to_ticks(1000);
600 /* start the Reset for a particular ring */
601 d64 = lio_read_csr64(oct,
602 LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
603 d64 &= ~LIO_CN23XX_PKT_INPUT_CTL_RING_ENB;
604 d64 |= LIO_CN23XX_PKT_INPUT_CTL_RST;
605 lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
609 * Wait until hardware indicates that the particular IQ
612 d64 = lio_read_csr64(oct, LIO_CN23XX_SLI_PKT_IOQ_RING_RST);
613 while (!(d64 & BIT_ULL(q_no)) && loop--) {
614 d64 = lio_read_csr64(oct,
615 LIO_CN23XX_SLI_PKT_IOQ_RING_RST);
616 lio_sleep_timeout(1);
620 /* Reset the doorbell register for this Input Queue. */
621 lio_write_csr32(oct, LIO_CN23XX_SLI_IQ_DOORBELL(q_no),
623 while (((lio_read_csr64(oct,
624 LIO_CN23XX_SLI_IQ_DOORBELL(q_no))) !=
626 lio_sleep_timeout(1);
630 /* Disable Output Queues. */
631 for (q_no = srn; q_no < ern; q_no++) {
632 loop = lio_ms_to_ticks(1000);
635 * Wait until hardware indicates that the particular IQ
636 * is out of reset.It given that SLI_PKT_RING_RST is
637 * common for both IQs and OQs
639 d64 = lio_read_csr64(oct, LIO_CN23XX_SLI_PKT_IOQ_RING_RST);
640 while (!(d64 & BIT_ULL(q_no)) && loop--) {
641 d64 = lio_read_csr64(oct,
642 LIO_CN23XX_SLI_PKT_IOQ_RING_RST);
643 lio_sleep_timeout(1);
647 /* Reset the doorbell register for this Output Queue. */
648 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKTS_CREDIT(q_no),
650 while ((lio_read_csr64(oct,
651 LIO_CN23XX_SLI_OQ_PKTS_CREDIT(q_no)) !=
653 lio_sleep_timeout(1);
656 /* clear the SLI_PKT(0..63)_CNTS[CNT] reg value */
657 d32 = lio_read_csr32(oct, LIO_CN23XX_SLI_OQ_PKTS_SENT(q_no));
658 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKTS_SENT(q_no), d32);
663 lio_cn23xx_pf_msix_interrupt_handler(void *dev)
665 struct lio_ioq_vector *ioq_vector = (struct lio_ioq_vector *)dev;
666 struct octeon_device *oct = ioq_vector->oct_dev;
667 struct lio_droq *droq = oct->droq[ioq_vector->droq_index];
672 lio_dev_err(oct, "23XX bringup FIXME: oct pfnum:%d ioq_vector->ioq_num :%d droq is NULL\n",
673 oct->pf_num, ioq_vector->ioq_num);
676 pkts_sent = lio_read_csr64(oct, droq->pkts_sent_reg);
679 * If our device has interrupted, then proceed. Also check
680 * for all f's if interrupt was triggered on an error
681 * and the PCI read fails.
683 if (!pkts_sent || (pkts_sent == 0xFFFFFFFFFFFFFFFFULL))
686 /* Write count reg in sli_pkt_cnts to clear these int. */
687 if (pkts_sent & LIO_CN23XX_INTR_PO_INT)
688 ret |= LIO_MSIX_PO_INT;
690 if (pkts_sent & LIO_CN23XX_INTR_PI_INT)
691 /* We will clear the count when we update the read_index. */
692 ret |= LIO_MSIX_PI_INT;
695 * Never need to handle msix mbox intr for pf. They arrive on the last
702 lio_cn23xx_pf_interrupt_handler(void *dev)
704 struct octeon_device *oct = (struct octeon_device *)dev;
705 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip;
708 lio_dev_dbg(oct, "In %s octeon_dev @ %p\n", __func__, oct);
709 intr64 = lio_read_csr64(oct, cn23xx->intr_sum_reg64);
713 if (intr64 & LIO_CN23XX_INTR_ERR)
714 lio_dev_err(oct, "Error Intr: 0x%016llx\n",
717 if (oct->msix_on != LIO_FLAG_MSIX_ENABLED) {
718 if (intr64 & LIO_CN23XX_INTR_PKT_DATA)
719 oct->int_status |= LIO_DEV_INTR_PKT_DATA;
722 if (intr64 & (LIO_CN23XX_INTR_DMA0_FORCE))
723 oct->int_status |= LIO_DEV_INTR_DMA0_FORCE;
725 if (intr64 & (LIO_CN23XX_INTR_DMA1_FORCE))
726 oct->int_status |= LIO_DEV_INTR_DMA1_FORCE;
728 /* Clear the current interrupts */
729 lio_write_csr64(oct, cn23xx->intr_sum_reg64, intr64);
733 lio_cn23xx_pf_bar1_idx_setup(struct octeon_device *oct, uint64_t core_addr,
734 uint32_t idx, int valid)
736 volatile uint64_t bar1;
740 reg_adr = lio_pci_readq(oct,
741 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port,
744 lio_pci_writeq(oct, (bar1 & 0xFFFFFFFEULL),
745 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port,
747 reg_adr = lio_pci_readq(oct,
748 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port,
754 * The PEM(0..3)_BAR1_INDEX(0..15)[ADDR_IDX]<23:4> stores
755 * bits <41:22> of the Core Addr
757 lio_pci_writeq(oct, (((core_addr >> 22) << 4) | LIO_PCI_BAR1_MASK),
758 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
760 bar1 = lio_pci_readq(oct, LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port,
765 lio_cn23xx_pf_bar1_idx_write(struct octeon_device *oct, uint32_t idx,
769 lio_pci_writeq(oct, mask,
770 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
774 lio_cn23xx_pf_bar1_idx_read(struct octeon_device *oct, uint32_t idx)
777 return ((uint32_t)lio_pci_readq(oct,
778 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port,
782 /* always call with lock held */
784 lio_cn23xx_pf_update_read_index(struct lio_instr_queue *iq)
786 struct octeon_device *oct = iq->oct_dev;
789 uint32_t pkt_in_done = lio_read_csr32(oct, iq->inst_cnt_reg);
791 last_done = pkt_in_done - iq->pkt_in_done;
792 iq->pkt_in_done = pkt_in_done;
795 * Modulo of the new index with the IQ size will give us
796 * the new index. The iq->reset_instr_cnt is always zero for
797 * cn23xx, so no extra adjustments are needed.
799 new_idx = (iq->octeon_read_index +
800 ((uint32_t)(last_done & LIO_CN23XX_PKT_IN_DONE_CNT_MASK))) %
807 lio_cn23xx_pf_enable_interrupt(struct octeon_device *oct, uint8_t intr_flag)
809 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip;
810 uint64_t intr_val = 0;
812 /* Divide the single write to multiple writes based on the flag. */
813 /* Enable Interrupt */
814 if (intr_flag == OCTEON_ALL_INTR) {
815 lio_write_csr64(oct, cn23xx->intr_enb_reg64,
816 cn23xx->intr_mask64);
817 } else if (intr_flag & OCTEON_OUTPUT_INTR) {
818 intr_val = lio_read_csr64(oct, cn23xx->intr_enb_reg64);
819 intr_val |= LIO_CN23XX_INTR_PKT_DATA;
820 lio_write_csr64(oct, cn23xx->intr_enb_reg64, intr_val);
825 lio_cn23xx_pf_disable_interrupt(struct octeon_device *oct, uint8_t intr_flag)
827 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip;
828 uint64_t intr_val = 0;
830 /* Disable Interrupts */
831 if (intr_flag == OCTEON_ALL_INTR) {
832 lio_write_csr64(oct, cn23xx->intr_enb_reg64, 0);
833 } else if (intr_flag & OCTEON_OUTPUT_INTR) {
834 intr_val = lio_read_csr64(oct, cn23xx->intr_enb_reg64);
835 intr_val &= ~LIO_CN23XX_INTR_PKT_DATA;
836 lio_write_csr64(oct, cn23xx->intr_enb_reg64, intr_val);
841 lio_cn23xx_pf_get_pcie_qlmport(struct octeon_device *oct)
843 oct->pcie_port = (lio_read_csr32(oct,
844 LIO_CN23XX_SLI_MAC_NUMBER)) & 0xff;
846 lio_dev_dbg(oct, "CN23xx uses PCIE Port %d\n",
851 lio_cn23xx_pf_get_pf_num(struct octeon_device *oct)
855 /* Read Function Dependency Link reg to get the function number */
856 fdl_bit = lio_read_pci_cfg(oct, LIO_CN23XX_PCIE_SRIOV_FDL);
857 oct->pf_num = ((fdl_bit >> LIO_CN23XX_PCIE_SRIOV_FDL_BIT_POS) &
858 LIO_CN23XX_PCIE_SRIOV_FDL_MASK);
862 lio_cn23xx_pf_setup_reg_address(struct octeon_device *oct)
864 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip;
866 oct->reg_list.pci_win_wr_addr = LIO_CN23XX_SLI_WIN_WR_ADDR64;
868 oct->reg_list.pci_win_rd_addr_hi = LIO_CN23XX_SLI_WIN_RD_ADDR_HI;
869 oct->reg_list.pci_win_rd_addr_lo = LIO_CN23XX_SLI_WIN_RD_ADDR64;
870 oct->reg_list.pci_win_rd_addr = LIO_CN23XX_SLI_WIN_RD_ADDR64;
872 oct->reg_list.pci_win_wr_data_hi = LIO_CN23XX_SLI_WIN_WR_DATA_HI;
873 oct->reg_list.pci_win_wr_data_lo = LIO_CN23XX_SLI_WIN_WR_DATA_LO;
874 oct->reg_list.pci_win_wr_data = LIO_CN23XX_SLI_WIN_WR_DATA64;
876 oct->reg_list.pci_win_rd_data = LIO_CN23XX_SLI_WIN_RD_DATA64;
878 lio_cn23xx_pf_get_pcie_qlmport(oct);
880 cn23xx->intr_mask64 = LIO_CN23XX_INTR_MASK;
882 cn23xx->intr_mask64 |= LIO_CN23XX_INTR_PKT_TIME;
884 cn23xx->intr_sum_reg64 =
885 LIO_CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num);
886 cn23xx->intr_enb_reg64 =
887 LIO_CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num);
891 lio_cn23xx_pf_sriov_config(struct octeon_device *oct)
893 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip;
894 uint32_t num_pf_rings, total_rings, max_rings;
895 cn23xx->conf = (struct lio_config *)lio_get_config_info(oct, LIO_23XX);
897 max_rings = LIO_CN23XX_PF_MAX_RINGS;
899 if (oct->sriov_info.num_pf_rings) {
900 num_pf_rings = oct->sriov_info.num_pf_rings;
901 if (num_pf_rings > max_rings) {
902 num_pf_rings = min(mp_ncpus, max_rings);
903 lio_dev_warn(oct, "num_queues_per_pf requested %u is more than available rings (%u). Reducing to %u\n",
904 oct->sriov_info.num_pf_rings,
905 max_rings, num_pf_rings);
909 num_pf_rings = min(rss_getnumbuckets(), mp_ncpus);
911 num_pf_rings = min(mp_ncpus, max_rings);
916 total_rings = num_pf_rings;
917 oct->sriov_info.trs = total_rings;
918 oct->sriov_info.pf_srn = total_rings - num_pf_rings;
919 oct->sriov_info.num_pf_rings = num_pf_rings;
921 lio_dev_dbg(oct, "trs:%d pf_srn:%d num_pf_rings:%d\n",
922 oct->sriov_info.trs, oct->sriov_info.pf_srn,
923 oct->sriov_info.num_pf_rings);
929 lio_cn23xx_pf_setup_device(struct octeon_device *oct)
934 data32 = lio_read_pci_cfg(oct, 0x10);
935 BAR0 = (uint64_t)(data32 & ~0xf);
936 data32 = lio_read_pci_cfg(oct, 0x14);
937 BAR0 |= ((uint64_t)data32 << 32);
938 data32 = lio_read_pci_cfg(oct, 0x18);
939 BAR1 = (uint64_t)(data32 & ~0xf);
940 data32 = lio_read_pci_cfg(oct, 0x1c);
941 BAR1 |= ((uint64_t)data32 << 32);
943 if (!BAR0 || !BAR1) {
945 lio_dev_err(oct, "Device BAR0 unassigned\n");
948 lio_dev_err(oct, "Device BAR1 unassigned\n");
953 if (lio_map_pci_barx(oct, 0))
956 if (lio_map_pci_barx(oct, 1)) {
957 lio_dev_err(oct, "%s CN23XX BAR1 map failed\n", __func__);
958 lio_unmap_pci_barx(oct, 0);
962 lio_cn23xx_pf_get_pf_num(oct);
964 if (lio_cn23xx_pf_sriov_config(oct)) {
965 lio_unmap_pci_barx(oct, 0);
966 lio_unmap_pci_barx(oct, 1);
969 lio_write_csr64(oct, LIO_CN23XX_SLI_MAC_CREDIT_CNT,
970 0x3F802080802080ULL);
972 oct->fn_list.setup_iq_regs = lio_cn23xx_pf_setup_iq_regs;
973 oct->fn_list.setup_oq_regs = lio_cn23xx_pf_setup_oq_regs;
974 oct->fn_list.process_interrupt_regs = lio_cn23xx_pf_interrupt_handler;
975 oct->fn_list.msix_interrupt_handler =
976 lio_cn23xx_pf_msix_interrupt_handler;
978 oct->fn_list.soft_reset = lio_cn23xx_pf_soft_reset;
979 oct->fn_list.setup_device_regs = lio_cn23xx_pf_setup_device_regs;
980 oct->fn_list.update_iq_read_idx = lio_cn23xx_pf_update_read_index;
982 oct->fn_list.bar1_idx_setup = lio_cn23xx_pf_bar1_idx_setup;
983 oct->fn_list.bar1_idx_write = lio_cn23xx_pf_bar1_idx_write;
984 oct->fn_list.bar1_idx_read = lio_cn23xx_pf_bar1_idx_read;
986 oct->fn_list.enable_interrupt = lio_cn23xx_pf_enable_interrupt;
987 oct->fn_list.disable_interrupt = lio_cn23xx_pf_disable_interrupt;
989 oct->fn_list.enable_io_queues = lio_cn23xx_pf_enable_io_queues;
990 oct->fn_list.disable_io_queues = lio_cn23xx_pf_disable_io_queues;
992 lio_cn23xx_pf_setup_reg_address(oct);
994 oct->coproc_clock_rate = 1000000ULL *
995 lio_cn23xx_pf_coprocessor_clock(oct);
1001 lio_cn23xx_pf_fw_loaded(struct octeon_device *oct)
1005 val = lio_read_csr64(oct, LIO_CN23XX_SLI_SCRATCH2);
1006 return ((val >> SCR2_BIT_FW_LOADED) & 1ULL);