4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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15 * the documentation and/or other materials provided with the
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * \brief Common: Structures and macros used in PCI-NIC package by core and
40 #ifndef __LIO_COMMON_H__
41 #define __LIO_COMMON_H__
43 #include "lio_config.h"
45 #define LIO_STR_HELPER(x) #x
46 #define LIO_STR(x) LIO_STR_HELPER(x)
47 #define LIO_BASE_MAJOR_VERSION 1
48 #define LIO_BASE_MINOR_VERSION 6
49 #define LIO_BASE_MICRO_VERSION 1
50 #define LIO_BASE_VERSION LIO_STR(LIO_BASE_MAJOR_VERSION) "." \
51 LIO_STR(LIO_BASE_MINOR_VERSION)
52 #define LIO_VERSION LIO_STR(LIO_BASE_MAJOR_VERSION) "." \
53 LIO_STR(LIO_BASE_MINOR_VERSION) \
54 "." LIO_STR(LIO_BASE_MICRO_VERSION)
63 /* Tag types used by Octeon cores in its work. */
71 /* pre-defined host->NIC tag values */
72 #define LIO_CONTROL (0x11111110)
73 #define LIO_DATA(i) (0x11111111 + (i))
76 * Opcodes used by host driver/apps to perform operations on the core.
77 * These are used to identify the major subsystem that the operation
80 #define LIO_OPCODE_NIC 1 /* used for NIC operations */
83 * Subcodes are used by host driver/apps to identify the sub-operation
84 * for the core. They only need to by unique for a given subsystem.
86 #define LIO_OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f))
88 /* OPCODE_CORE subcodes. For future use. */
90 /* OPCODE_NIC subcodes */
92 /* This subcode is sent by core PCI driver to indicate cores are ready. */
93 #define LIO_OPCODE_NIC_CORE_DRV_ACTIVE 0x01
94 #define LIO_OPCODE_NIC_NW_DATA 0x02 /* network packet data */
95 #define LIO_OPCODE_NIC_CMD 0x03
96 #define LIO_OPCODE_NIC_INFO 0x04
97 #define LIO_OPCODE_NIC_PORT_STATS 0x05
98 #define LIO_OPCODE_NIC_INTRMOD_CFG 0x08
99 #define LIO_OPCODE_NIC_IF_CFG 0x09
100 #define LIO_OPCODE_NIC_INTRMOD_PARAMS 0x0B
102 /* Application codes advertised by the core driver initialization packet. */
103 #define LIO_DRV_APP_START 0x0
104 #define LIO_DRV_APP_COUNT 0x2
105 #define LIO_DRV_NIC_APP (LIO_DRV_APP_START + 0x1)
106 #define LIO_DRV_INVALID_APP (LIO_DRV_APP_START + 0x2)
107 #define LIO_DRV_APP_END (LIO_DRV_INVALID_APP - 1)
109 #define BYTES_PER_DHLEN_UNIT 8
111 #define SCR2_BIT_FW_LOADED 63
112 #define SCR2_BIT_FW_RELOADED 62
114 static inline uint32_t
115 lio_incr_index(uint32_t index, uint32_t count, uint32_t max)
117 if ((index + count) >= max)
118 index = index + count - max;
125 #define LIO_BOARD_NAME 32
126 #define LIO_SERIAL_NUM_LEN 64
129 * Structure used by core driver to send indication that the Octeon
130 * application is ready.
132 struct lio_core_setup {
135 char boardname[LIO_BOARD_NAME];
137 char board_serial_number[LIO_SERIAL_NUM_LEN];
139 uint64_t board_rev_major;
141 uint64_t board_rev_minor;
145 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/
148 * The Scatter-Gather List Entry. The scatter or gather component used with
149 * a Octeon input instruction has this format.
151 struct lio_sg_entry {
152 /* The first 64 bit gives the size of data in each dptr. */
158 /* The 4 dptr pointers for this entry. */
163 #define LIO_SG_ENTRY_SIZE (sizeof(struct lio_sg_entry))
166 * \brief Add size to gather list
167 * @param sg_entry scatter/gather entry
168 * @param size size to add
169 * @param pos position to add it.
172 lio_add_sg_size(struct lio_sg_entry *sg_entry, uint16_t size, uint32_t pos)
175 #if BYTE_ORDER == BIG_ENDIAN
176 sg_entry->u.size[pos] = size;
177 #else /* BYTE_ORDER != BIG_ENDIAN */
178 sg_entry->u.size[3 - pos] = size;
179 #endif /* BYTE_ORDER == BIG_ENDIAN */
182 /*------------------------- End Scatter/Gather ---------------------------*/
184 #define LIO_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */
186 #define LIO_MAX_FRM_SIZE (16000 + LIO_FRM_HEADER_SIZE)
188 #define LIO_DEFAULT_FRM_SIZE (1500 + LIO_FRM_HEADER_SIZE)
190 /* NIC Command types */
191 #define LIO_CMD_CHANGE_MTU 0x1
192 #define LIO_CMD_CHANGE_MACADDR 0x2
193 #define LIO_CMD_CHANGE_DEVFLAGS 0x3
194 #define LIO_CMD_RX_CTL 0x4
195 #define LIO_CMD_SET_MULTI_LIST 0x5
197 /* command for setting the speed, duplex & autoneg */
198 #define LIO_CMD_SET_SETTINGS 0x7
199 #define LIO_CMD_SET_FLOW_CTL 0x8
201 #define LIO_CMD_GPIO_ACCESS 0xA
202 #define LIO_CMD_LRO_ENABLE 0xB
203 #define LIO_CMD_LRO_DISABLE 0xC
204 #define LIO_CMD_SET_RSS 0xD
206 #define LIO_CMD_TNL_RX_CSUM_CTL 0x10
207 #define LIO_CMD_TNL_TX_CSUM_CTL 0x11
208 #define LIO_CMD_VERBOSE_ENABLE 0x14
209 #define LIO_CMD_VERBOSE_DISABLE 0x15
211 #define LIO_CMD_VLAN_FILTER_CTL 0x16
212 #define LIO_CMD_ADD_VLAN_FILTER 0x17
213 #define LIO_CMD_DEL_VLAN_FILTER 0x18
214 #define LIO_CMD_VXLAN_PORT_CONFIG 0x19
216 #define LIO_CMD_ID_ACTIVE 0x1a
218 #define LIO_CMD_SET_FNV 0x1d
220 #define LIO_CMD_PKT_STEERING_CTL 0x1e
222 #define LIO_CMD_QUEUE_COUNT_CTL 0x1f
224 #define LIO_CMD_VXLAN_PORT_ADD 0x0
225 #define LIO_CMD_VXLAN_PORT_DEL 0x1
226 #define LIO_CMD_RXCSUM_ENABLE 0x0
227 #define LIO_CMD_RXCSUM_DISABLE 0x1
228 #define LIO_CMD_TXCSUM_ENABLE 0x0
229 #define LIO_CMD_TXCSUM_DISABLE 0x1
230 #define LIO_CMD_FNV_ENABLE 0x1
231 #define LIO_CMD_FNV_DISABLE 0x0
232 #define LIO_CMD_PKT_STEERING_ENABLE 0x0
233 #define LIO_CMD_PKT_STEERING_DISABLE 0x1
235 /* RX(packets coming from wire) Checksum verification flags */
237 #define LIO_L4SUM_VERIFIED 0x1
238 #define LIO_IPSUM_VERIFIED 0x2
240 /*LROIPV4 and LROIPV6 Flags*/
241 #define LIO_LROIPV4 0x1
242 #define LIO_LROIPV6 0x2
244 /* Interface flags communicated between host driver and core app. */
246 LIO_IFFLAG_PROMISC = 0x01,
247 LIO_IFFLAG_ALLMULTI = 0x02,
248 LIO_IFFLAG_MULTICAST = 0x04,
249 LIO_IFFLAG_BROADCAST = 0x08,
250 LIO_IFFLAG_UNICAST = 0x10
274 #if BYTE_ORDER == BIG_ENDIAN
277 uint64_t more:6; /* How many udd words follow the command */
279 uint64_t reserved:29;
285 #else /* BYTE_ORDER != BIG_ENDIAN */
291 uint64_t reserved:29;
297 #endif /* BYTE_ORDER == BIG_ENDIAN */
302 #define OCTEON_CMD_SIZE (sizeof(union octeon_cmd))
304 /* pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */
305 #define LIO_SOFTCMDRESP_IH3 (40 + 8)
307 #define LIO_PCICMD_O3 (24 + 8)
309 /* Instruction Header(DPI) - for OCTEON-III models */
310 struct octeon_instr_ih3 {
311 #if BYTE_ORDER == BIG_ENDIAN
314 uint64_t reserved3:1;
316 /* Gather indicator 1=gather */
319 /* Data length OR no. of entries in gather list */
322 /* Front Data size */
326 uint64_t reserved2:4;
328 /* PKI port kind - PKIND */
332 uint64_t reserved1:32;
334 #else /* BYTE_ORDER != BIG_ENDIAN */
337 uint64_t reserved1:32;
339 /* PKI port kind - PKIND */
343 uint64_t reserved2:4;
345 /* Front Data size */
348 /* Data length OR no. of entries in gather list */
351 /* Gather indicator 1=gather */
355 uint64_t reserved3:1;
357 #endif /* BYTE_ORDER == BIG_ENDIAN */
360 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */
361 /* BIG ENDIAN format. */
362 struct octeon_instr_pki_ih3 {
363 #if BYTE_ORDER == BIG_ENDIAN
368 /* Raw mode indicator 1 = RAW */
378 uint64_t reserved2:1;
393 uint64_t reserved1:2;
401 #else /* BYTE_ORDER != BIG_ENDIAN */
410 uint64_t reserved1:2;
425 uint64_t reserved2:1;
433 /* Raw mode indicator 1 = RAW */
438 #endif /* BYTE_ORDER == BIG_ENDIAN */
442 /* Input Request Header */
443 struct octeon_instr_irh {
444 #if BYTE_ORDER == BIG_ENDIAN
451 uint64_t ossp:32; /* opcode/subcode specific parameters */
453 #else /* BYTE_ORDER != BIG_ENDIAN */
455 uint64_t ossp:32; /* opcode/subcode specific parameters */
462 #endif /* BYTE_ORDER == BIG_ENDIAN */
465 /* Return Data Parameters */
466 struct octeon_instr_rdp {
467 #if BYTE_ORDER == BIG_ENDIAN
468 uint64_t reserved:49;
469 uint64_t pcie_port:3;
472 #else /* BYTE_ORDER != BIG_ENDIAN */
475 uint64_t pcie_port:3;
476 uint64_t reserved:49;
477 #endif /* BYTE_ORDER == BIG_ENDIAN */
482 #if BYTE_ORDER == BIG_ENDIAN
487 uint64_t len:3; /* additional 64-bit words */
488 uint64_t reserved:17;
489 uint64_t ossp:32; /* opcode/subcode specific parameters */
494 uint64_t len:3; /* additional 64-bit words */
498 uint64_t csum_verified:3;/* checksum verified. */
499 uint64_t has_hwtstamp:1; /* Has hardware timestamp. 1 = yes. */
501 uint64_t has_hash:1; /* Has hash (rth or rss). 1 = yes. */
506 uint64_t len:3; /* additional 64-bit words */
507 uint64_t reserved:11;
508 uint64_t num_gmx_ports:8;
509 uint64_t max_nic_ports:10;
510 uint64_t app_cap_flags:4;
517 uint64_t len:3; /* additional 64-bit words */
522 #else /* BYTE_ORDER != BIG_ENDIAN */
525 uint64_t ossp:32; /* opcode/subcode specific parameters */
526 uint64_t reserved:17;
527 uint64_t len:3; /* additional 64-bit words */
532 uint64_t has_hash:1; /* Has hash (rth or rss). 1 = yes. */
534 uint64_t has_hwtstamp:1; /* 1 = has hwtstamp */
535 uint64_t csum_verified:3; /* checksum verified. */
539 uint64_t len:3; /* additional 64-bit words */
546 uint64_t app_cap_flags:4;
547 uint64_t max_nic_ports:10;
548 uint64_t num_gmx_ports:8;
549 uint64_t reserved:11;
550 uint64_t len:3; /* additional 64-bit words */
558 uint64_t len:3; /* additional 64-bit words */
562 #endif /* BYTE_ORDER == BIG_ENDIAN */
565 #define OCTEON_RH_SIZE (sizeof(union octeon_rh))
567 union octeon_packet_params {
568 uint32_t pkt_params32;
570 #if BYTE_ORDER == BIG_ENDIAN
571 uint32_t reserved:24;
572 uint32_t ip_csum:1; /* Perform IP header checksum(s) */
573 /* Perform Outer transport header checksum */
574 uint32_t transport_csum:1;
575 /* Find tunnel, and perform transport csum. */
577 uint32_t tsflag:1; /* Timestamp this packet */
578 uint32_t ipsec_ops:4; /* IPsec operation */
580 #else /* BYTE_ORDER != BIG_ENDIAN */
582 uint32_t ipsec_ops:4;
585 uint32_t transport_csum:1;
587 uint32_t reserved:24;
588 #endif /* BYTE_ORDER == BIG_ENDIAN */
592 /* Status of a RGMII Link on Octeon as seen by core driver. */
593 union octeon_link_status {
594 uint64_t link_status64;
597 #if BYTE_ORDER == BIG_ENDIAN
606 uint64_t reserved:15;
608 #else /* BYTE_ORDER != BIG_ENDIAN */
610 uint64_t reserved:15;
619 #endif /* BYTE_ORDER == BIG_ENDIAN */
623 /* The txpciq info passed to host from the firmware */
625 union octeon_txpciq {
629 #if BYTE_ORDER == BIG_ENDIAN
635 uint64_t aura_num:10;
636 uint64_t reserved:20;
638 #else /* BYTE_ORDER != BIG_ENDIAN */
640 uint64_t reserved:20;
641 uint64_t aura_num:10;
647 #endif /* BYTE_ORDER == BIG_ENDIAN */
651 /* The rxpciq info passed to host from the firmware */
653 union octeon_rxpciq {
657 #if BYTE_ORDER == BIG_ENDIAN
659 uint64_t reserved:56;
661 #else /* BYTE_ORDER != BIG_ENDIAN */
663 uint64_t reserved:56;
665 #endif /* BYTE_ORDER == BIG_ENDIAN */
669 /* Information for a OCTEON ethernet interface shared between core & host. */
670 struct octeon_link_info {
671 union octeon_link_status link;
674 #if BYTE_ORDER == BIG_ENDIAN
676 uint64_t macaddr_is_admin_asgnd:1;
677 uint64_t vlan_is_admin_assigned:1;
679 uint64_t num_txpciq:8;
680 uint64_t num_rxpciq:8;
682 #else /* BYTE_ORDER != BIG_ENDIAN */
684 uint64_t num_rxpciq:8;
685 uint64_t num_txpciq:8;
687 uint64_t vlan_is_admin_assigned:1;
688 uint64_t macaddr_is_admin_asgnd:1;
690 #endif /* BYTE_ORDER == BIG_ENDIAN */
692 union octeon_txpciq txpciq[LIO_MAX_IOQS_PER_NICIF];
693 union octeon_rxpciq rxpciq[LIO_MAX_IOQS_PER_NICIF];
696 struct octeon_if_cfg_info {
697 uint64_t iqmask; /* mask for IQs enabled for the port */
698 uint64_t oqmask; /* mask for OQs enabled for the port */
699 struct octeon_link_info linfo; /* initial link information */
700 char lio_firmware_version[32];
703 /* Stats for each NIC port in RX direction. */
704 struct octeon_rx_stats {
705 /* link-level stats */
712 uint64_t fifo_err; /* Accounts for over/under-run of buffers */
720 uint64_t fw_total_rcvd;
721 uint64_t fw_total_fwd;
722 uint64_t fw_total_fwd_bytes;
724 uint64_t fw_err_link;
725 uint64_t fw_err_drop;
726 uint64_t fw_rx_vxlan;
727 uint64_t fw_rx_vxlan_err;
730 uint64_t fw_lro_pkts; /* Number of packets that are LROed */
731 uint64_t fw_lro_octs; /* Number of octets that are LROed */
732 uint64_t fw_total_lro; /* Number of LRO packets formed */
733 uint64_t fw_lro_aborts; /* Number of times lRO of packet aborted */
734 uint64_t fw_lro_aborts_port;
735 uint64_t fw_lro_aborts_seq;
736 uint64_t fw_lro_aborts_tsval;
737 uint64_t fw_lro_aborts_timer;
738 /* intrmod: packet forward rate */
742 /* Stats for each NIC port in RX direction. */
743 struct octeon_tx_stats {
744 /* link-level stats */
745 uint64_t total_pkts_sent;
746 uint64_t total_bytes_sent;
747 uint64_t mcast_pkts_sent;
748 uint64_t bcast_pkts_sent;
750 uint64_t one_collision_sent; /* Packets sent after one collision */
751 uint64_t multi_collision_sent; /* Packets sent after multiple collision */
752 uint64_t max_collision_fail; /* Packets not sent due to max collisions */
753 uint64_t max_deferral_fail; /* Packets not sent due to max deferrals */
754 uint64_t fifo_err; /* Accounts for over/under-run of buffers */
756 uint64_t total_collisions; /* Total number of collisions detected */
759 uint64_t fw_total_sent;
760 uint64_t fw_total_fwd;
761 uint64_t fw_total_fwd_bytes;
763 uint64_t fw_err_link;
764 uint64_t fw_err_drop;
766 uint64_t fw_tso; /* number of tso requests */
767 uint64_t fw_tso_fwd; /* number of packets segmented in tso */
768 uint64_t fw_tx_vxlan;
772 struct octeon_link_stats {
773 struct octeon_rx_stats fromwire;
774 struct octeon_tx_stats fromhost;
779 lio_opcode_slow_path(union octeon_rh *rh)
781 uint16_t subcode1, subcode2;
783 subcode1 = LIO_OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode);
784 subcode2 = LIO_OPCODE_SUBCODE(LIO_OPCODE_NIC, LIO_OPCODE_NIC_NW_DATA);
786 return (subcode2 != subcode1);
789 struct octeon_mdio_cmd {
797 struct octeon_intrmod_cfg {
800 uint64_t check_intrvl;
801 uint64_t maxpkt_ratethr;
802 uint64_t minpkt_ratethr;
803 uint64_t rx_maxcnt_trigger;
804 uint64_t rx_mincnt_trigger;
805 uint64_t rx_maxtmr_trigger;
806 uint64_t rx_mintmr_trigger;
807 uint64_t tx_mincnt_trigger;
808 uint64_t tx_maxcnt_trigger;
814 #define LIO_BASE_QUEUE_NOT_REQUESTED 65535
816 union octeon_if_cfg {
819 #if BYTE_ORDER == BIG_ENDIAN
820 uint64_t base_queue:16;
821 uint64_t num_iqueues:16;
822 uint64_t num_oqueues:16;
823 uint64_t gmx_port_id:8;
826 #else /* BYTE_ORDER != BIG_ENDIAN */
829 uint64_t gmx_port_id:8;
830 uint64_t num_oqueues:16;
831 uint64_t num_iqueues:16;
832 uint64_t base_queue:16;
833 #endif /* BYTE_ORDER == BIG_ENDIAN */
837 #endif /* __LIO_COMMON_H__ */