4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Cavium, Inc. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include "lio_common.h"
39 #include "lio_response_manager.h"
40 #include "lio_device.h"
42 #include "lio_network.h"
43 #include "cn23xx_pf_device.h"
44 #include "lio_image.h"
45 #include "lio_mem_ops.h"
47 static struct lio_config default_cn23xx_conf = {
48 .card_type = LIO_23XX,
49 .card_name = LIO_23XX_NAME,
52 .max_iqs = LIO_CN23XX_CFG_IO_QUEUES,
53 .pending_list_size = (LIO_CN23XX_DEFAULT_IQ_DESCRIPTORS *
54 LIO_CN23XX_CFG_IO_QUEUES),
55 .instr_type = LIO_64BYTE_INSTR,
56 .db_min = LIO_CN23XX_DB_MIN,
57 .db_timeout = LIO_CN23XX_DB_TIMEOUT,
58 .iq_intr_pkt = LIO_CN23XX_DEF_IQ_INTR_THRESHOLD,
63 .max_oqs = LIO_CN23XX_CFG_IO_QUEUES,
64 .pkts_per_intr = LIO_CN23XX_OQ_PKTS_PER_INTR,
65 .refill_threshold = LIO_CN23XX_OQ_REFIL_THRESHOLD,
66 .oq_intr_pkt = LIO_CN23XX_OQ_INTR_PKT,
67 .oq_intr_time = LIO_CN23XX_OQ_INTR_TIME,
70 .num_nic_ports = LIO_CN23XX_DEFAULT_NUM_PORTS,
71 .num_def_rx_descs = LIO_CN23XX_DEFAULT_OQ_DESCRIPTORS,
72 .num_def_tx_descs = LIO_CN23XX_DEFAULT_IQ_DESCRIPTORS,
73 .def_rx_buf_size = LIO_CN23XX_OQ_BUF_SIZE,
75 /* For ethernet interface 0: Port cfg Attributes */
77 /* Max Txqs: Half for each of the two ports :max_iq/2 */
78 .max_txqs = LIO_MAX_TXQS_PER_INTF,
80 /* Actual configured value. Range could be: 1...max_txqs */
81 .num_txqs = LIO_DEF_TXQS_PER_INTF,
83 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
84 .max_rxqs = LIO_MAX_RXQS_PER_INTF,
86 /* Actual configured value. Range could be: 1...max_rxqs */
87 .num_rxqs = LIO_DEF_RXQS_PER_INTF,
89 /* Num of desc for rx rings */
90 .num_rx_descs = LIO_CN23XX_DEFAULT_OQ_DESCRIPTORS,
92 /* Num of desc for tx rings */
93 .num_tx_descs = LIO_CN23XX_DEFAULT_IQ_DESCRIPTORS,
96 * Mbuf size, We need not change buf size even for Jumbo frames.
97 * Octeon can send jumbo frames in 4 consecutive descriptors,
99 .rx_buf_size = LIO_CN23XX_OQ_BUF_SIZE,
101 .base_queue = LIO_BASE_QUEUE_NOT_REQUESTED,
107 /* Max Txqs: Half for each of the two ports :max_iq/2 */
108 .max_txqs = LIO_MAX_TXQS_PER_INTF,
110 /* Actual configured value. Range could be: 1...max_txqs */
111 .num_txqs = LIO_DEF_TXQS_PER_INTF,
113 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
114 .max_rxqs = LIO_MAX_RXQS_PER_INTF,
116 /* Actual configured value. Range could be: 1...max_rxqs */
117 .num_rxqs = LIO_DEF_RXQS_PER_INTF,
119 /* Num of desc for rx rings */
120 .num_rx_descs = LIO_CN23XX_DEFAULT_OQ_DESCRIPTORS,
122 /* Num of desc for tx rings */
123 .num_tx_descs = LIO_CN23XX_DEFAULT_IQ_DESCRIPTORS,
126 * Mbuf size, We need not change buf size even for Jumbo frames.
127 * Octeon can send jumbo frames in 4 consecutive descriptors,
129 .rx_buf_size = LIO_CN23XX_OQ_BUF_SIZE,
131 .base_queue = LIO_BASE_QUEUE_NOT_REQUESTED,
137 /* Host driver link query interval */
138 .oct_link_query_interval = 100,
140 /* Octeon link query interval */
141 .host_link_query_interval = 500,
143 .enable_sli_oq_bp = 0,
145 /* Control queue group */
150 static struct lio_config_ptr {
152 } oct_conf_info[LIO_MAX_DEVICES] = {
155 LIO_CFG_TYPE_DEFAULT,
157 LIO_CFG_TYPE_DEFAULT,
159 LIO_CFG_TYPE_DEFAULT,
161 LIO_CFG_TYPE_DEFAULT,
165 static char lio_state_str[LIO_DEV_STATES + 1][32] = {
166 "BEGIN", "PCI-ENABLE-DONE", "PCI-MAP-DONE", "DISPATCH-INIT-DONE",
167 "IQ-INIT-DONE", "SCBUFF-POOL-INIT-DONE", "RESPLIST-INIT-DONE",
168 "DROQ-INIT-DONE", "MBOX-SETUP-DONE", "MSIX-ALLOC-VECTOR-DONE",
169 "INTR-SET-DONE", "IO-QUEUES-INIT-DONE", "CONSOLE-INIT-DONE",
170 "HOST-READY", "CORE-READY", "RUNNING", "IN-RESET",
174 static char lio_app_str[LIO_DRV_APP_COUNT + 1][32] = {"BASE", "NIC", "UNKNOWN"};
176 static struct octeon_device *octeon_device[LIO_MAX_DEVICES];
177 static volatile int lio_adapter_refcounts[LIO_MAX_DEVICES];
179 static uint32_t octeon_device_count;
180 /* locks device array (i.e. octeon_device[]) */
181 struct mtx octeon_devices_lock;
183 static struct lio_core_setup core_setup[LIO_MAX_DEVICES];
186 oct_set_config_info(int oct_id, int conf_type)
189 if (conf_type < 0 || conf_type > (LIO_NUM_CFGS - 1))
190 conf_type = LIO_CFG_TYPE_DEFAULT;
191 oct_conf_info[oct_id].conf_type = conf_type;
195 lio_init_device_list(int conf_type)
199 bzero(octeon_device, (sizeof(void *) * LIO_MAX_DEVICES));
200 for (i = 0; i < LIO_MAX_DEVICES; i++)
201 oct_set_config_info(i, conf_type);
202 mtx_init(&octeon_devices_lock, "octeon_devices_lock", NULL, MTX_DEF);
206 __lio_retrieve_config_info(struct octeon_device *oct, uint16_t card_type)
209 uint32_t oct_id = oct->octeon_id;
211 switch (oct_conf_info[oct_id].conf_type) {
212 case LIO_CFG_TYPE_DEFAULT:
213 if (oct->chip_id == LIO_CN23XX_PF_VID) {
214 ret = &default_cn23xx_conf;
225 lio_get_config_info(struct octeon_device *oct, uint16_t card_type)
229 conf = __lio_retrieve_config_info(oct, card_type);
237 lio_get_state_string(volatile int *state_ptr)
239 int32_t istate = (int32_t)atomic_load_acq_int(state_ptr);
241 if (istate > LIO_DEV_STATES || istate < 0)
242 return (lio_state_str[LIO_DEV_STATE_INVALID]);
244 return (lio_state_str[istate]);
248 lio_get_app_string(uint32_t app_mode)
251 if (app_mode <= LIO_DRV_APP_END)
252 return (lio_app_str[app_mode - LIO_DRV_APP_START]);
254 return (lio_app_str[LIO_DRV_INVALID_APP - LIO_DRV_APP_START]);
258 lio_free_device_mem(struct octeon_device *oct)
262 for (i = 0; i < LIO_MAX_OUTPUT_QUEUES(oct); i++) {
263 if ((oct->io_qmask.oq & BIT_ULL(i)) && (oct->droq[i]))
264 free(oct->droq[i], M_DEVBUF);
267 for (i = 0; i < LIO_MAX_INSTR_QUEUES(oct); i++) {
268 if ((oct->io_qmask.iq & BIT_ULL(i)) && (oct->instr_queue[i]))
269 free(oct->instr_queue[i], M_DEVBUF);
273 free(oct->chip, M_DEVBUF);
275 octeon_device[i] = NULL;
276 octeon_device_count--;
279 static struct octeon_device *
280 lio_allocate_device_mem(device_t device)
282 struct octeon_device *oct;
283 uint32_t configsize = 0, pci_id = 0, size;
286 pci_id = pci_get_device(device);
288 case LIO_CN23XX_PF_VID:
289 configsize = sizeof(struct lio_cn23xx_pf);
292 device_printf(device, "Error: Unknown PCI Device: 0x%x\n",
297 if (configsize & 0x7)
298 configsize += (8 - (configsize & 0x7));
301 (sizeof(struct lio_dispatch) * LIO_DISPATCH_LIST_SIZE);
303 buf = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
307 oct = (struct octeon_device *)device_get_softc(device);
308 oct->chip = (void *)(buf);
309 oct->dispatch.dlist = (struct lio_dispatch *)(buf + configsize);
314 struct octeon_device *
315 lio_allocate_device(device_t device)
317 struct octeon_device *oct = NULL;
318 uint32_t oct_idx = 0;
320 mtx_lock(&octeon_devices_lock);
322 for (oct_idx = 0; oct_idx < LIO_MAX_DEVICES; oct_idx++)
323 if (!octeon_device[oct_idx])
326 if (oct_idx < LIO_MAX_DEVICES) {
327 oct = lio_allocate_device_mem(device);
329 octeon_device_count++;
330 octeon_device[oct_idx] = oct;
334 mtx_unlock(&octeon_devices_lock);
339 mtx_init(&oct->pci_win_lock, "pci_win_lock", NULL, MTX_DEF);
340 mtx_init(&oct->mem_access_lock, "mem_access_lock", NULL, MTX_DEF);
342 oct->octeon_id = oct_idx;
343 snprintf(oct->device_name, sizeof(oct->device_name), "%s%d",
344 LIO_DRV_NAME, oct->octeon_id);
350 * Register a device's bus location at initialization time.
351 * @param oct - pointer to the octeon device structure.
352 * @param bus - PCIe bus #
353 * @param dev - PCIe device #
354 * @param func - PCIe function #
355 * @param is_pf - TRUE for PF, FALSE for VF
356 * @return reference count of device's adapter
359 lio_register_device(struct octeon_device *oct, int bus, int dev, int func,
366 oct->loc.func = func;
368 oct->adapter_refcount = &lio_adapter_refcounts[oct->octeon_id];
369 atomic_store_rel_int(oct->adapter_refcount, 0);
371 mtx_lock(&octeon_devices_lock);
372 for (idx = (int)oct->octeon_id - 1; idx >= 0; idx--) {
373 if (octeon_device[idx] == NULL) {
374 lio_dev_err(oct, "%s: Internal driver error, missing dev\n",
376 mtx_unlock(&octeon_devices_lock);
377 atomic_add_int(oct->adapter_refcount, 1);
378 return (1); /* here, refcount is guaranteed to be 1 */
381 /* if another device is at same bus/dev, use its refcounter */
382 if ((octeon_device[idx]->loc.bus == bus) &&
383 (octeon_device[idx]->loc.dev == dev)) {
384 oct->adapter_refcount =
385 octeon_device[idx]->adapter_refcount;
390 mtx_unlock(&octeon_devices_lock);
392 atomic_add_int(oct->adapter_refcount, 1);
393 refcount = atomic_load_acq_int(oct->adapter_refcount);
395 lio_dev_dbg(oct, "%s: %02x:%02x:%d refcount %u\n", __func__,
396 oct->loc.bus, oct->loc.dev, oct->loc.func, refcount);
402 * Deregister a device at de-initialization time.
403 * @param oct - pointer to the octeon device structure.
404 * @return reference count of device's adapter
407 lio_deregister_device(struct octeon_device *oct)
411 atomic_subtract_int(oct->adapter_refcount, 1);
412 refcount = atomic_load_acq_int(oct->adapter_refcount);
414 lio_dev_dbg(oct, "%s: %04d:%02d:%d refcount %u\n", __func__,
415 oct->loc.bus, oct->loc.dev, oct->loc.func, refcount);
421 lio_allocate_ioq_vector(struct octeon_device *oct)
423 struct lio_ioq_vector *ioq_vector;
424 int i, cpu_num, num_ioqs = 0, size;
426 if (LIO_CN23XX_PF(oct))
427 num_ioqs = oct->sriov_info.num_pf_rings;
429 size = sizeof(struct lio_ioq_vector) * num_ioqs;
431 oct->ioq_vector = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
432 if (oct->ioq_vector == NULL)
435 for (i = 0; i < num_ioqs; i++) {
436 ioq_vector = &oct->ioq_vector[i];
437 ioq_vector->oct_dev = oct;
438 ioq_vector->droq_index = i;
439 cpu_num = i % mp_ncpus;
440 CPU_SETOF(cpu_num, &ioq_vector->affinity_mask);
442 if (oct->chip_id == LIO_CN23XX_PF_VID)
443 ioq_vector->ioq_num = i + oct->sriov_info.pf_srn;
445 ioq_vector->ioq_num = i;
451 lio_free_ioq_vector(struct octeon_device *oct)
454 free(oct->ioq_vector, M_DEVBUF);
455 oct->ioq_vector = NULL;
458 /* this function is only for setting up the first queue */
460 lio_setup_instr_queue0(struct octeon_device *oct)
462 union octeon_txpciq txpciq;
464 uint32_t num_descs = 0;
466 if (LIO_CN23XX_PF(oct))
468 LIO_GET_NUM_DEF_TX_DESCS_CFG(LIO_CHIP_CONF(oct,
473 oct->instr_queue[0]->q_index = 0;
474 oct->instr_queue[0]->app_ctx = (void *)(size_t)0;
475 oct->instr_queue[0]->ifidx = 0;
477 txpciq.s.q_no = iq_no;
478 txpciq.s.pkind = oct->pfvf_hsword.pkind;
479 txpciq.s.use_qpg = 0;
481 if (lio_init_instr_queue(oct, txpciq, num_descs)) {
482 /* prevent memory leak */
483 lio_delete_instr_queue(oct, 0);
492 lio_setup_output_queue0(struct octeon_device *oct)
494 uint32_t desc_size = 0, num_descs = 0, oq_no = 0;
496 if (LIO_CN23XX_PF(oct)) {
498 LIO_GET_NUM_DEF_RX_DESCS_CFG(LIO_CHIP_CONF(oct,
501 LIO_GET_DEF_RX_BUF_SIZE_CFG(LIO_CHIP_CONF(oct,
507 if (lio_init_droq(oct, oq_no, num_descs, desc_size, NULL)) {
517 lio_init_dispatch_list(struct octeon_device *oct)
521 oct->dispatch.count = 0;
523 for (i = 0; i < LIO_DISPATCH_LIST_SIZE; i++) {
524 oct->dispatch.dlist[i].opcode = 0;
525 STAILQ_INIT(&oct->dispatch.dlist[i].head);
528 mtx_init(&oct->dispatch.lock, "dispatch_lock", NULL, MTX_DEF);
534 lio_delete_dispatch_list(struct octeon_device *oct)
536 struct lio_stailq_head freelist;
537 struct lio_stailq_node *temp, *tmp2;
540 STAILQ_INIT(&freelist);
542 mtx_lock(&oct->dispatch.lock);
544 for (i = 0; i < LIO_DISPATCH_LIST_SIZE; i++) {
545 struct lio_stailq_head *dispatch;
547 dispatch = &oct->dispatch.dlist[i].head;
548 while (!STAILQ_EMPTY(dispatch)) {
549 temp = STAILQ_FIRST(dispatch);
550 STAILQ_REMOVE_HEAD(&oct->dispatch.dlist[i].head,
552 STAILQ_INSERT_TAIL(&freelist, temp, entries);
555 oct->dispatch.dlist[i].opcode = 0;
558 oct->dispatch.count = 0;
560 mtx_unlock(&oct->dispatch.lock);
562 STAILQ_FOREACH_SAFE(temp, &freelist, entries, tmp2) {
563 STAILQ_REMOVE_HEAD(&freelist, entries);
564 free(temp, M_DEVBUF);
569 lio_get_dispatch(struct octeon_device *octeon_dev, uint16_t opcode,
572 struct lio_stailq_node *dispatch;
573 lio_dispatch_fn_t fn = NULL;
575 uint16_t combined_opcode = LIO_OPCODE_SUBCODE(opcode, subcode);
577 idx = combined_opcode & LIO_OPCODE_MASK;
579 mtx_lock(&octeon_dev->dispatch.lock);
581 if (octeon_dev->dispatch.count == 0) {
582 mtx_unlock(&octeon_dev->dispatch.lock);
586 if (!(octeon_dev->dispatch.dlist[idx].opcode)) {
587 mtx_unlock(&octeon_dev->dispatch.lock);
591 if (octeon_dev->dispatch.dlist[idx].opcode == combined_opcode) {
592 fn = octeon_dev->dispatch.dlist[idx].dispatch_fn;
594 STAILQ_FOREACH(dispatch, &octeon_dev->dispatch.dlist[idx].head,
596 if (((struct lio_dispatch *)dispatch)->opcode ==
598 fn = ((struct lio_dispatch *)
599 dispatch)->dispatch_fn;
605 mtx_unlock(&octeon_dev->dispatch.lock);
610 * lio_register_dispatch_fn
612 * octeon_id - id of the octeon device.
613 * opcode - opcode for which driver should call the registered function
614 * subcode - subcode for which driver should call the registered function
615 * fn - The function to call when a packet with "opcode" arrives in
616 * octeon output queues.
617 * fn_arg - The argument to be passed when calling function "fn".
619 * Registers a function and its argument to be called when a packet
620 * arrives in Octeon output queues with "opcode".
628 lio_register_dispatch_fn(struct octeon_device *oct, uint16_t opcode,
629 uint16_t subcode, lio_dispatch_fn_t fn, void *fn_arg)
631 lio_dispatch_fn_t pfn;
633 uint16_t combined_opcode = LIO_OPCODE_SUBCODE(opcode, subcode);
635 idx = combined_opcode & LIO_OPCODE_MASK;
637 mtx_lock(&oct->dispatch.lock);
638 /* Add dispatch function to first level of lookup table */
639 if (oct->dispatch.dlist[idx].opcode == 0) {
640 oct->dispatch.dlist[idx].opcode = combined_opcode;
641 oct->dispatch.dlist[idx].dispatch_fn = fn;
642 oct->dispatch.dlist[idx].arg = fn_arg;
643 oct->dispatch.count++;
644 mtx_unlock(&oct->dispatch.lock);
648 mtx_unlock(&oct->dispatch.lock);
651 * Check if there was a function already registered for this
654 pfn = lio_get_dispatch(oct, opcode, subcode);
656 struct lio_dispatch *dispatch;
659 "Adding opcode to dispatch list linked list\n");
660 dispatch = (struct lio_dispatch *)
661 malloc(sizeof(struct lio_dispatch),
662 M_DEVBUF, M_NOWAIT | M_ZERO);
663 if (dispatch == NULL) {
665 "No memory to add dispatch function\n");
669 dispatch->opcode = combined_opcode;
670 dispatch->dispatch_fn = fn;
671 dispatch->arg = fn_arg;
674 * Add dispatch function to linked list of fn ptrs
675 * at the hashed index.
677 mtx_lock(&oct->dispatch.lock);
678 STAILQ_INSERT_HEAD(&oct->dispatch.dlist[idx].head,
679 &dispatch->node, entries);
680 oct->dispatch.count++;
681 mtx_unlock(&oct->dispatch.lock);
684 lio_dev_err(oct, "Found previously registered dispatch fn for opcode/subcode: %x/%x\n",
693 * lio_unregister_dispatch_fn
695 * oct - octeon device
696 * opcode - driver should unregister the function for this opcode
697 * subcode - driver should unregister the function for this subcode
699 * Unregister the function set for this opcode+subcode.
707 lio_unregister_dispatch_fn(struct octeon_device *oct, uint16_t opcode,
710 struct lio_stailq_head *dispatch_head;
711 struct lio_stailq_node *dispatch, *dfree = NULL, *tmp2;
714 uint16_t combined_opcode = LIO_OPCODE_SUBCODE(opcode, subcode);
716 idx = combined_opcode & LIO_OPCODE_MASK;
718 mtx_lock(&oct->dispatch.lock);
720 if (oct->dispatch.count == 0) {
721 mtx_unlock(&oct->dispatch.lock);
722 lio_dev_err(oct, "No dispatch functions registered for this device\n");
725 if (oct->dispatch.dlist[idx].opcode == combined_opcode) {
726 dispatch_head = &oct->dispatch.dlist[idx].head;
727 if (!STAILQ_EMPTY(dispatch_head)) {
728 dispatch = STAILQ_FIRST(dispatch_head);
729 oct->dispatch.dlist[idx].opcode =
730 ((struct lio_dispatch *)dispatch)->opcode;
731 oct->dispatch.dlist[idx].dispatch_fn =
732 ((struct lio_dispatch *)dispatch)->dispatch_fn;
733 oct->dispatch.dlist[idx].arg =
734 ((struct lio_dispatch *)dispatch)->arg;
735 STAILQ_REMOVE_HEAD(dispatch_head, entries);
738 oct->dispatch.dlist[idx].opcode = 0;
739 oct->dispatch.dlist[idx].dispatch_fn = NULL;
740 oct->dispatch.dlist[idx].arg = NULL;
744 STAILQ_FOREACH_SAFE(dispatch,
745 &oct->dispatch.dlist[idx].head,
747 if (((struct lio_dispatch *)dispatch)->opcode ==
749 STAILQ_REMOVE(&oct->dispatch.dlist[idx].head,
751 lio_stailq_node, entries);
759 oct->dispatch.count--;
761 mtx_unlock(&oct->dispatch.lock);
762 free(dfree, M_DEVBUF);
768 lio_core_drv_init(struct lio_recv_info *recv_info, void *buf)
770 struct octeon_device *oct = (struct octeon_device *)buf;
771 struct lio_recv_pkt *recv_pkt = recv_info->recv_pkt;
772 struct lio_core_setup *cs = NULL;
774 uint32_t num_nic_ports = 0;
777 if (LIO_CN23XX_PF(oct))
778 num_nic_ports = LIO_GET_NUM_NIC_PORTS_CFG(
779 LIO_CHIP_CONF(oct, cn23xx_pf));
781 if (atomic_load_acq_int(&oct->status) >= LIO_DEV_RUNNING) {
782 lio_dev_err(oct, "Received CORE OK when device state is 0x%x\n",
783 atomic_load_acq_int(&oct->status));
784 goto core_drv_init_err;
788 lio_get_app_string((uint32_t)
789 recv_pkt->rh.r_core_drv_init.app_mode),
790 sizeof(app_name) - 1);
791 oct->app_mode = (uint32_t)recv_pkt->rh.r_core_drv_init.app_mode;
792 if (recv_pkt->rh.r_core_drv_init.app_mode == LIO_DRV_NIC_APP) {
793 oct->fw_info.max_nic_ports =
794 (uint32_t)recv_pkt->rh.r_core_drv_init.max_nic_ports;
795 oct->fw_info.num_gmx_ports =
796 (uint32_t)recv_pkt->rh.r_core_drv_init.num_gmx_ports;
799 if (oct->fw_info.max_nic_ports < num_nic_ports) {
800 lio_dev_err(oct, "Config has more ports than firmware allows (%d > %d).\n",
801 num_nic_ports, oct->fw_info.max_nic_ports);
802 goto core_drv_init_err;
805 oct->fw_info.app_cap_flags = recv_pkt->rh.r_core_drv_init.app_cap_flags;
806 oct->fw_info.app_mode = (uint32_t)recv_pkt->rh.r_core_drv_init.app_mode;
807 oct->pfvf_hsword.app_mode =
808 (uint32_t)recv_pkt->rh.r_core_drv_init.app_mode;
810 oct->pfvf_hsword.pkind = recv_pkt->rh.r_core_drv_init.pkind;
812 for (i = 0; i < oct->num_iqs; i++)
813 oct->instr_queue[i]->txpciq.s.pkind = oct->pfvf_hsword.pkind;
815 atomic_store_rel_int(&oct->status, LIO_DEV_CORE_OK);
817 cs = &core_setup[oct->octeon_id];
819 if (recv_pkt->buffer_size[0] != (sizeof(*cs) + LIO_DROQ_INFO_SIZE)) {
820 lio_dev_dbg(oct, "Core setup bytes expected %llu found %d\n",
821 LIO_CAST64(sizeof(*cs) + LIO_DROQ_INFO_SIZE),
822 recv_pkt->buffer_size[0]);
825 memcpy(cs, recv_pkt->buffer_ptr[0]->m_data + LIO_DROQ_INFO_SIZE,
827 strncpy(oct->boardinfo.name, cs->boardname, LIO_BOARD_NAME);
828 strncpy(oct->boardinfo.serial_number, cs->board_serial_number,
831 lio_swap_8B_data((uint64_t *)cs, (sizeof(*cs) >> 3));
833 oct->boardinfo.major = cs->board_rev_major;
834 oct->boardinfo.minor = cs->board_rev_minor;
836 lio_dev_info(oct, "Running %s (%llu Hz)\n", app_name,
837 LIO_CAST64(cs->corefreq));
840 for (i = 0; i < recv_pkt->buffer_count; i++)
841 lio_recv_buffer_free(recv_pkt->buffer_ptr[i]);
843 lio_free_recv_info(recv_info);
848 lio_get_tx_qsize(struct octeon_device *oct, uint32_t q_no)
851 if ((oct != NULL) && (q_no < (uint32_t)LIO_MAX_INSTR_QUEUES(oct)) &&
852 (oct->io_qmask.iq & BIT_ULL(q_no)))
853 return (oct->instr_queue[q_no]->max_count);
860 lio_get_rx_qsize(struct octeon_device *oct, uint32_t q_no)
863 if ((oct != NULL) && (q_no < (uint32_t)LIO_MAX_OUTPUT_QUEUES(oct)) &&
864 (oct->io_qmask.oq & BIT_ULL(q_no)))
865 return (oct->droq[q_no]->max_count);
870 /* Returns the host firmware handshake OCTEON specific configuration */
872 lio_get_conf(struct octeon_device *oct)
874 struct lio_config *default_oct_conf = NULL;
877 * check the OCTEON Device model & return the corresponding octeon
880 if (LIO_CN23XX_PF(oct)) {
881 default_oct_conf = (struct lio_config *)(
882 LIO_CHIP_CONF(oct, cn23xx_pf));
885 return (default_oct_conf);
889 * Get the octeon device pointer.
890 * @param octeon_id - The id for which the octeon device pointer is required.
891 * @return Success: Octeon device pointer.
892 * @return Failure: NULL.
894 struct octeon_device *
895 lio_get_device(uint32_t octeon_id)
898 if (octeon_id >= LIO_MAX_DEVICES)
901 return (octeon_device[octeon_id]);
905 lio_pci_readq(struct octeon_device *oct, uint64_t addr)
908 volatile uint32_t val32, addrhi;
910 mtx_lock(&oct->pci_win_lock);
913 * The windowed read happens when the LSB of the addr is written.
916 addrhi = (addr >> 32);
917 if (oct->chip_id == LIO_CN23XX_PF_VID)
918 addrhi |= 0x00060000;
919 lio_write_csr32(oct, oct->reg_list.pci_win_rd_addr_hi, addrhi);
921 /* Read back to preserve ordering of writes */
922 val32 = lio_read_csr32(oct, oct->reg_list.pci_win_rd_addr_hi);
924 lio_write_csr32(oct, oct->reg_list.pci_win_rd_addr_lo,
926 val32 = lio_read_csr32(oct, oct->reg_list.pci_win_rd_addr_lo);
928 val64 = lio_read_csr64(oct, oct->reg_list.pci_win_rd_data);
930 mtx_unlock(&oct->pci_win_lock);
936 lio_pci_writeq(struct octeon_device *oct, uint64_t val, uint64_t addr)
938 volatile uint32_t val32;
940 mtx_lock(&oct->pci_win_lock);
942 lio_write_csr64(oct, oct->reg_list.pci_win_wr_addr, addr);
944 /* The write happens when the LSB is written. So write MSB first. */
945 lio_write_csr32(oct, oct->reg_list.pci_win_wr_data_hi, val >> 32);
946 /* Read the MSB to ensure ordering of writes. */
947 val32 = lio_read_csr32(oct, oct->reg_list.pci_win_wr_data_hi);
949 lio_write_csr32(oct, oct->reg_list.pci_win_wr_data_lo,
952 mtx_unlock(&oct->pci_win_lock);
956 lio_mem_access_ok(struct octeon_device *oct)
958 uint64_t access_okay = 0;
959 uint64_t lmc0_reset_ctl;
961 /* Check to make sure a DDR interface is enabled */
962 if (LIO_CN23XX_PF(oct)) {
963 lmc0_reset_ctl = lio_pci_readq(oct, LIO_CN23XX_LMC0_RESET_CTL);
965 (lmc0_reset_ctl & LIO_CN23XX_LMC0_RESET_CTL_DDR3RST_MASK);
968 return (access_okay ? 0 : 1);
972 lio_wait_for_ddr_init(struct octeon_device *oct, unsigned long *timeout)
980 for (ms = 0; ret && ((*timeout == 0) || (ms <= *timeout)); ms += 100) {
981 ret = lio_mem_access_ok(oct);
985 lio_sleep_timeout(100);
992 * Get the octeon id assigned to the octeon device passed as argument.
993 * This function is exported to other modules.
994 * @param dev - octeon device pointer passed as a void *.
995 * @return octeon device id
998 lio_get_device_id(void *dev)
1000 struct octeon_device *octeon_dev = (struct octeon_device *)dev;
1003 for (i = 0; i < LIO_MAX_DEVICES; i++)
1004 if (octeon_device[i] == octeon_dev)
1005 return (octeon_dev->octeon_id);
1011 lio_enable_irq(struct lio_droq *droq, struct lio_instr_queue *iq)
1013 struct octeon_device *oct = NULL;
1017 /* the whole thing needs to be atomic, ideally */
1019 oct = droq->oct_dev;
1020 pkts_pend = atomic_load_acq_int(&droq->pkts_pending);
1021 mtx_lock(&droq->lock);
1022 lio_write_csr32(oct, droq->pkts_sent_reg,
1023 droq->pkt_count - pkts_pend);
1024 droq->pkt_count = pkts_pend;
1025 /* this write needs to be flushed before we release the lock */
1026 __compiler_membar();
1027 mtx_unlock(&droq->lock);
1032 mtx_lock(&iq->lock);
1033 lio_write_csr32(oct, iq->inst_cnt_reg, iq->pkt_in_done);
1034 iq->pkt_in_done = 0;
1035 /* this write needs to be flushed before we release the lock */
1036 __compiler_membar();
1037 mtx_unlock(&iq->lock);
1041 * Implementation note:
1043 * SLI_PKT(x)_CNTS[RESEND] is written separately so that if an interrupt
1044 * DOES occur as a result of RESEND, the DROQ lock will NOT be held.
1046 * Write resend. Writing RESEND in SLI_PKTX_CNTS should be enough
1047 * to trigger tx interrupts as well, if they are pending.
1049 if ((oct != NULL) && (LIO_CN23XX_PF(oct))) {
1051 lio_write_csr64(oct, droq->pkts_sent_reg,
1052 LIO_CN23XX_INTR_RESEND);
1053 /* we race with firmrware here. */
1054 /* read and write the IN_DONE_CNTS */
1055 else if (iq != NULL) {
1056 instr_cnt = lio_read_csr64(oct, iq->inst_cnt_reg);
1057 lio_write_csr64(oct, iq->inst_cnt_reg,
1058 ((instr_cnt & 0xFFFFFFFF00000000ULL) |
1059 LIO_CN23XX_INTR_RESEND));