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37 * \brief Host Driver: Routines used to read/write Octeon memory.
40 #ifndef __LIO_MEM_OPS_H__
41 #define __LIO_MEM_OPS_H__
44 * Read a 64-bit value from a BAR1 mapped core memory address.
45 * @param oct - pointer to the octeon device.
46 * @param core_addr - the address to read from.
48 * The range_idx gives the BAR1 index register for the range of address
49 * in which core_addr is mapped.
51 * @return 64-bit value read from Core memory
53 uint64_t lio_read_device_mem64(struct octeon_device *oct,
57 * Read a 32-bit value from a BAR1 mapped core memory address.
58 * @param oct - pointer to the octeon device.
59 * @param core_addr - the address to read from.
61 * @return 32-bit value read from Core memory
63 uint32_t lio_read_device_mem32(struct octeon_device *oct,
67 * Write a 32-bit value to a BAR1 mapped core memory address.
68 * @param oct - pointer to the octeon device.
69 * @param core_addr - the address to write to.
70 * @param val - 32-bit value to write.
72 void lio_write_device_mem32(struct octeon_device *oct,
73 uint64_t core_addr, uint32_t val);
75 /* Read multiple bytes from Octeon memory. */
76 void lio_pci_read_core_mem(struct octeon_device *oct,
77 uint64_t coreaddr, uint8_t *buf,
80 /* Write multiple bytes into Octeon memory. */
81 void lio_pci_write_core_mem(struct octeon_device *oct,
82 uint64_t coreaddr, uint8_t *buf,
85 #endif /* __LIO_MEM_OPS_H__ */