4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Cavium, Inc. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * \brief Host Driver: This file is included by all host driver source files
38 * to include common definitions.
44 extern unsigned int lio_hwlro;
46 #define LIO_CAST64(v) ((long long)(long)(v))
48 #define LIO_DRV_NAME "lio"
52 lio_swap_8B_data(uint64_t *data, uint32_t blocks)
56 *data = htobe64(*data);
63 * \brief unmaps a PCI BAR
64 * @param oct Pointer to Octeon device
65 * @param baridx bar index
68 lio_unmap_pci_barx(struct octeon_device *oct, int baridx)
71 lio_dev_dbg(oct, "Freeing PCI mapped regions for Bar%d\n", baridx);
73 if (oct->mem_bus_space[baridx].pci_mem != NULL) {
74 bus_release_resource(oct->device, SYS_RES_MEMORY,
76 oct->mem_bus_space[baridx].pci_mem);
77 oct->mem_bus_space[baridx].pci_mem = NULL;
82 * \brief maps a PCI BAR
83 * @param oct Pointer to Octeon device
84 * @param baridx bar index
87 lio_map_pci_barx(struct octeon_device *oct, int baridx)
89 int rid = PCIR_BAR(baridx * 2);
91 oct->mem_bus_space[baridx].pci_mem =
92 bus_alloc_resource_any(oct->device, SYS_RES_MEMORY, &rid,
95 if (oct->mem_bus_space[baridx].pci_mem == NULL) {
96 lio_dev_err(oct, "Unable to allocate bus resource: memory\n");
100 /* Save bus_space values for READ/WRITE_REG macros */
101 oct->mem_bus_space[baridx].tag =
102 rman_get_bustag(oct->mem_bus_space[baridx].pci_mem);
103 oct->mem_bus_space[baridx].handle =
104 rman_get_bushandle(oct->mem_bus_space[baridx].pci_mem);
106 lio_dev_dbg(oct, "BAR%d Tag 0x%llx Handle 0x%llx\n",
107 baridx, LIO_CAST64(oct->mem_bus_space[baridx].tag),
108 LIO_CAST64(oct->mem_bus_space[baridx].handle));
114 lio_sleep_cond(struct octeon_device *oct, volatile int *condition)
117 while (!(*condition)) {
119 lio_flush_iq(oct, oct->instr_queue[0], 0);
120 lio_process_ordered_list(oct, 0);
124 int lio_console_debug_enabled(uint32_t console);
127 #define ROUNDUP4(val) (((val) + 3) & 0xfffffffc)
131 #define ROUNDUP8(val) (((val) + 7) & 0xfffffff8)
134 #define BIT_ULL(nr) (1ULL << (nr))
136 void lio_free_mbuf(struct lio_instr_queue *iq,
137 struct lio_mbuf_free_info *finfo);
138 void lio_free_sgmbuf(struct lio_instr_queue *iq,
139 struct lio_mbuf_free_info *finfo);
141 #endif /* _LIO_MAIN_H_ */