4 * Copyright (c) 2002-2004 David Boggs. <boggs@boggs.palo-alto.ca.us>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * GNU General Public License:
32 * This program is free software; you can redistribute it and/or modify it
33 * under the terms of the GNU General Public License as published by the Free
34 * Software Foundation; either version 2 of the License, or (at your option)
37 * This program is distributed in the hope that it will be useful, but WITHOUT
38 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
39 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
42 * You should have received a copy of the GNU General Public License along with
43 * this program; if not, write to the Free Software Foundation, Inc., 59
44 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
48 * This is an open-source Unix device driver for PCI-bus WAN interface cards.
49 * It sends and receives packets in HDLC frames over synchronous links.
50 * A generic PC plus Unix plus some SBE/LMC cards makes an OPEN router.
51 * This driver works with FreeBSD, NetBSD, OpenBSD, BSD/OS and Linux.
52 * It has been tested on i386 (32-bit little-end), Sparc (64-bit big-end),
53 * and Alpha (64-bit little-end) architectures.
55 * History and Authors:
57 * Ron Crane had the neat idea to use a Fast Ethernet chip as a PCI
58 * interface and add an Ethernet-to-HDLC gate array to make a WAN card.
59 * David Boggs designed the Ethernet-to-HDLC gate arrays and PC cards.
60 * We did this at our company, LAN Media Corporation (LMC).
61 * SBE Corp acquired LMC and continues to make the cards.
63 * Since the cards use Tulip Ethernet chips, we started with Matt Thomas'
64 * ubiquitous "de" driver. Michael Graff stripped out the Ethernet stuff
65 * and added HSSI stuff. Basil Gunn ported it to Solaris (lost) and
66 * Rob Braun ported it to Linux. Andrew Stanley-Jones added support
67 * for three more cards and wrote the first version of lmcconfig.
68 * During 2002-5 David Boggs rewrote it and now feels responsible for it.
70 * Responsible Individual:
72 * Send bug reports and improvements to <boggs@boggs.palo-alto.ca.us>.
74 # include <sys/param.h> /* OS version */
76 # include "opt_inet.h" /* INET */
77 # include "opt_inet6.h" /* INET6 */
78 # include "opt_netgraph.h" /* NETGRAPH */
79 # ifdef HAVE_KERNEL_OPTION_HEADERS
80 # include "opt_device_polling.h" /* DEVICE_POLLING */
91 # define P2P 0 /* not in FreeBSD */
92 # define NSPPP 1 /* No count devices in FreeBSD 5 */
93 # include "opt_bpf.h" /* DEV_BPF */
99 # define GEN_HDLC 0 /* not in FreeBSD */
101 # include <sys/systm.h>
102 # include <sys/kernel.h>
103 # include <sys/malloc.h>
104 # include <sys/mbuf.h>
105 # include <sys/socket.h>
106 # include <sys/sockio.h>
107 # include <sys/module.h>
108 # include <sys/bus.h>
109 # include <sys/lock.h>
111 # include <net/if_var.h>
112 # include <net/if_types.h>
113 # include <net/if_media.h>
114 # include <net/netisr.h>
115 # include <net/route.h>
116 # include <machine/bus.h>
117 # include <machine/resource.h>
118 # include <sys/rman.h>
120 # include <vm/pmap.h>
121 # include <sys/priv.h>
122 # include <sys/mutex.h>
123 # include <dev/pci/pcivar.h>
125 # include <netgraph/ng_message.h>
126 # include <netgraph/netgraph.h>
129 # include <netinet/in.h>
130 # include <netinet/in_var.h>
133 # include <net/if_sppp.h>
136 # include <net/bpf.h>
139 # include <dev/lmc/if_lmc.h>
145 /* The SROM is a generic 93C46 serial EEPROM (64 words by 16 bits). */
146 /* Data is set up before the RISING edge of CLK; CLK is parked low. */
148 shift_srom_bits(softc_t *sc, u_int32_t data, u_int32_t len)
150 u_int32_t csr = READ_CSR(TLP_SROM_MII);
153 if (data & (1<<(len-1)))
154 csr |= TLP_SROM_DIN; /* DIN setup */
156 csr &= ~TLP_SROM_DIN; /* DIN setup */
157 WRITE_CSR(TLP_SROM_MII, csr);
158 csr |= TLP_SROM_CLK; /* CLK rising edge */
159 WRITE_CSR(TLP_SROM_MII, csr);
160 csr &= ~TLP_SROM_CLK; /* CLK falling edge */
161 WRITE_CSR(TLP_SROM_MII, csr);
165 /* Data is sampled on the RISING edge of CLK; CLK is parked low. */
167 read_srom(softc_t *sc, u_int8_t addr)
173 /* Enable SROM access. */
174 csr = (TLP_SROM_SEL | TLP_SROM_RD | TLP_MII_MDOE);
175 WRITE_CSR(TLP_SROM_MII, csr);
176 /* CS rising edge prepares SROM for a new cycle. */
178 WRITE_CSR(TLP_SROM_MII, csr); /* assert CS */
179 shift_srom_bits(sc, 6, 4); /* issue read cmd */
180 shift_srom_bits(sc, addr, 6); /* issue address */
181 for (data=0, i=16; i>=0; i--) /* read ->17<- bits of data */
183 csr = READ_CSR(TLP_SROM_MII); /* DOUT sampled */
184 data = (data<<1) | ((csr & TLP_SROM_DOUT) ? 1:0);
185 csr |= TLP_SROM_CLK; /* CLK rising edge */
186 WRITE_CSR(TLP_SROM_MII, csr);
187 csr &= ~TLP_SROM_CLK; /* CLK falling edge */
188 WRITE_CSR(TLP_SROM_MII, csr);
190 /* Disable SROM access. */
191 WRITE_CSR(TLP_SROM_MII, TLP_MII_MDOE);
196 /* The SROM is formatted by the mfgr and should NOT be written! */
197 /* But lmcconfig can rewrite it in case it gets overwritten somehow. */
198 /* IOCTL SYSCALL: can sleep. */
200 write_srom(softc_t *sc, u_int8_t addr, u_int16_t data)
205 /* Enable SROM access. */
206 csr = (TLP_SROM_SEL | TLP_SROM_RD | TLP_MII_MDOE);
207 WRITE_CSR(TLP_SROM_MII, csr);
209 /* Issue write-enable command. */
211 WRITE_CSR(TLP_SROM_MII, csr); /* assert CS */
212 shift_srom_bits(sc, 4, 4); /* issue write enable cmd */
213 shift_srom_bits(sc, 63, 6); /* issue address */
215 WRITE_CSR(TLP_SROM_MII, csr); /* deassert CS */
217 /* Issue erase command. */
219 WRITE_CSR(TLP_SROM_MII, csr); /* assert CS */
220 shift_srom_bits(sc, 7, 4); /* issue erase cmd */
221 shift_srom_bits(sc, addr, 6); /* issue address */
223 WRITE_CSR(TLP_SROM_MII, csr); /* deassert CS */
225 /* Issue write command. */
227 WRITE_CSR(TLP_SROM_MII, csr); /* assert CS */
228 for (i=0; i<10; i++) /* 100 ms max wait */
229 if ((READ_CSR(TLP_SROM_MII) & TLP_SROM_DOUT)==0) SLEEP(10000);
230 shift_srom_bits(sc, 5, 4); /* issue write cmd */
231 shift_srom_bits(sc, addr, 6); /* issue address */
232 shift_srom_bits(sc, data, 16); /* issue data */
234 WRITE_CSR(TLP_SROM_MII, csr); /* deassert CS */
236 /* Issue write-disable command. */
238 WRITE_CSR(TLP_SROM_MII, csr); /* assert CS */
239 for (i=0; i<10; i++) /* 100 ms max wait */
240 if ((READ_CSR(TLP_SROM_MII) & TLP_SROM_DOUT)==0) SLEEP(10000);
241 shift_srom_bits(sc, 4, 4); /* issue write disable cmd */
242 shift_srom_bits(sc, 0, 6); /* issue address */
244 WRITE_CSR(TLP_SROM_MII, csr); /* deassert CS */
246 /* Disable SROM access. */
247 WRITE_CSR(TLP_SROM_MII, TLP_MII_MDOE);
250 /* Not all boards have BIOS roms. */
251 /* The BIOS ROM is an AMD 29F010 1Mbit (128K by 8) EEPROM. */
253 read_bios(softc_t *sc, u_int32_t addr)
257 /* Load the BIOS rom address register. */
258 WRITE_CSR(TLP_BIOS_ROM, addr);
260 /* Enable the BIOS rom. */
261 srom_mii = TLP_BIOS_SEL | TLP_BIOS_RD | TLP_MII_MDOE;
262 WRITE_CSR(TLP_SROM_MII, srom_mii);
264 /* Wait at least 20 PCI cycles. */
267 /* Read the BIOS rom data. */
268 srom_mii = READ_CSR(TLP_SROM_MII);
270 /* Disable the BIOS rom. */
271 WRITE_CSR(TLP_SROM_MII, TLP_MII_MDOE);
273 return (u_int8_t)srom_mii & 0xFF;
277 write_bios_phys(softc_t *sc, u_int32_t addr, u_int8_t data)
281 /* Load the BIOS rom address register. */
282 WRITE_CSR(TLP_BIOS_ROM, addr);
284 /* Enable the BIOS rom. */
285 srom_mii = TLP_BIOS_SEL | TLP_BIOS_WR | TLP_MII_MDOE;
287 /* Load the data into the data register. */
288 srom_mii = (srom_mii & 0xFFFFFF00) | (data & 0xFF);
289 WRITE_CSR(TLP_SROM_MII, srom_mii);
291 /* Wait at least 20 PCI cycles. */
294 /* Disable the BIOS rom. */
295 WRITE_CSR(TLP_SROM_MII, TLP_MII_MDOE);
298 /* IOCTL SYSCALL: can sleep. */
300 write_bios(softc_t *sc, u_int32_t addr, u_int8_t data)
304 /* this sequence enables writing */
305 write_bios_phys(sc, 0x5555, 0xAA);
306 write_bios_phys(sc, 0x2AAA, 0x55);
307 write_bios_phys(sc, 0x5555, 0xA0);
308 write_bios_phys(sc, addr, data);
310 /* Wait for the write operation to complete. */
311 for (;;) /* interruptable syscall */
315 read_data = read_bios(sc, addr);
316 if ((read_data & 0x80) == (data & 0x80)) break;
317 if (read_data & 0x20)
318 { /* Data sheet says read it again. */
319 read_data = read_bios(sc, addr);
320 if ((read_data & 0x80) == (data & 0x80)) break;
322 printf("%s: write_bios() failed; rom addr=0x%x\n",
327 read_data = read_bios(sc, addr);
328 if (read_data == data) break;
332 /* IOCTL SYSCALL: can sleep. */
334 erase_bios(softc_t *sc)
336 unsigned char read_data;
338 /* This sequence enables erasing: */
339 write_bios_phys(sc, 0x5555, 0xAA);
340 write_bios_phys(sc, 0x2AAA, 0x55);
341 write_bios_phys(sc, 0x5555, 0x80);
342 write_bios_phys(sc, 0x5555, 0xAA);
343 write_bios_phys(sc, 0x2AAA, 0x55);
344 write_bios_phys(sc, 0x5555, 0x10);
346 /* Wait for the erase operation to complete. */
347 for (;;) /* interruptable syscall */
351 read_data = read_bios(sc, 0);
352 if (read_data & 0x80) break;
353 if (read_data & 0x20)
354 { /* Data sheet says read it again. */
355 read_data = read_bios(sc, 0);
356 if (read_data & 0x80) break;
358 printf("%s: erase_bios() failed\n", NAME_UNIT);
362 read_data = read_bios(sc, 0);
363 if (read_data == 0xFF) break;
367 /* MDIO is 3-stated between tranactions. */
368 /* MDIO is set up before the RISING edge of MDC; MDC is parked low. */
370 shift_mii_bits(softc_t *sc, u_int32_t data, u_int32_t len)
372 u_int32_t csr = READ_CSR(TLP_SROM_MII);
375 if (data & (1<<(len-1)))
376 csr |= TLP_MII_MDOUT; /* MDOUT setup */
378 csr &= ~TLP_MII_MDOUT; /* MDOUT setup */
379 WRITE_CSR(TLP_SROM_MII, csr);
380 csr |= TLP_MII_MDC; /* MDC rising edge */
381 WRITE_CSR(TLP_SROM_MII, csr);
382 csr &= ~TLP_MII_MDC; /* MDC falling edge */
383 WRITE_CSR(TLP_SROM_MII, csr);
387 /* The specification for the MII is IEEE Std 802.3 clause 22. */
388 /* MDIO is sampled on the RISING edge of MDC; MDC is parked low. */
390 read_mii(softc_t *sc, u_int8_t regad)
396 WRITE_CSR(TLP_SROM_MII, TLP_MII_MDOUT);
398 shift_mii_bits(sc, 0xFFFFF, 20); /* preamble */
399 shift_mii_bits(sc, 0xFFFFF, 20); /* preamble */
400 shift_mii_bits(sc, 1, 2); /* start symbol */
401 shift_mii_bits(sc, 2, 2); /* read op */
402 shift_mii_bits(sc, 0, 5); /* phyad=0 */
403 shift_mii_bits(sc, regad, 5); /* regad */
404 csr = READ_CSR(TLP_SROM_MII);
406 WRITE_CSR(TLP_SROM_MII, csr);
407 shift_mii_bits(sc, 0, 2); /* turn-around */
408 for (i=15; i>=0; i--) /* data */
410 csr = READ_CSR(TLP_SROM_MII); /* MDIN sampled */
411 data = (data<<1) | ((csr & TLP_MII_MDIN) ? 1:0);
412 csr |= TLP_MII_MDC; /* MDC rising edge */
413 WRITE_CSR(TLP_SROM_MII, csr);
414 csr &= ~TLP_MII_MDC; /* MDC falling edge */
415 WRITE_CSR(TLP_SROM_MII, csr);
421 write_mii(softc_t *sc, u_int8_t regad, u_int16_t data)
423 WRITE_CSR(TLP_SROM_MII, TLP_MII_MDOUT);
424 shift_mii_bits(sc, 0xFFFFF, 20); /* preamble */
425 shift_mii_bits(sc, 0xFFFFF, 20); /* preamble */
426 shift_mii_bits(sc, 1, 2); /* start symbol */
427 shift_mii_bits(sc, 1, 2); /* write op */
428 shift_mii_bits(sc, 0, 5); /* phyad=0 */
429 shift_mii_bits(sc, regad, 5); /* regad */
430 shift_mii_bits(sc, 2, 2); /* turn-around */
431 shift_mii_bits(sc, data, 16); /* data */
432 WRITE_CSR(TLP_SROM_MII, TLP_MII_MDOE);
433 if (regad == 16) sc->led_state = data; /* a small optimization */
437 set_mii16_bits(softc_t *sc, u_int16_t bits)
439 u_int16_t mii16 = read_mii(sc, 16);
441 write_mii(sc, 16, mii16);
445 clr_mii16_bits(softc_t *sc, u_int16_t bits)
447 u_int16_t mii16 = read_mii(sc, 16);
449 write_mii(sc, 16, mii16);
453 set_mii17_bits(softc_t *sc, u_int16_t bits)
455 u_int16_t mii17 = read_mii(sc, 17);
457 write_mii(sc, 17, mii17);
461 clr_mii17_bits(softc_t *sc, u_int16_t bits)
463 u_int16_t mii17 = read_mii(sc, 17);
465 write_mii(sc, 17, mii17);
469 * Watchdog code is more readable if it refreshes LEDs
470 * once a second whether they need it or not.
471 * But MII refs take 150 uSecs each, so remember the last value
472 * written to MII16 and avoid LED writes that do nothing.
476 led_off(softc_t *sc, u_int16_t led)
478 if ((led & sc->led_state) == led) return;
479 set_mii16_bits(sc, led);
483 led_on(softc_t *sc, u_int16_t led)
485 if ((led & sc->led_state) == 0) return;
486 clr_mii16_bits(sc, led);
490 led_inv(softc_t *sc, u_int16_t led)
492 u_int16_t mii16 = read_mii(sc, 16);
494 write_mii(sc, 16, mii16);
498 * T1 & T3 framer registers are accessed through MII regs 17 & 18.
499 * Write the address to MII reg 17 then R/W data through MII reg 18.
500 * The hardware interface is an Intel-style 8-bit muxed A/D bus.
503 write_framer(softc_t *sc, u_int16_t addr, u_int8_t data)
505 write_mii(sc, 17, addr);
506 write_mii(sc, 18, data);
510 read_framer(softc_t *sc, u_int16_t addr)
512 write_mii(sc, 17, addr);
513 return (u_int8_t)read_mii(sc, 18);
516 /* Tulip's hardware implementation of General Purpose IO
517 * (GPIO) pins makes life difficult for software.
518 * Bits 7-0 in the Tulip GPIO CSR are used for two purposes
519 * depending on the state of bit 8.
520 * If bit 8 is 0 then bits 7-0 are "data" bits.
521 * If bit 8 is 1 then bits 7-0 are "direction" bits.
522 * If a direction bit is one, the data bit is an output.
523 * The problem is that the direction bits are WRITE-ONLY.
524 * Software must remember the direction bits in a shadow copy.
525 * (sc->gpio_dir) in order to change some but not all of the bits.
526 * All accesses to the Tulip GPIO register use these five procedures.
530 make_gpio_input(softc_t *sc, u_int32_t bits)
532 sc->gpio_dir &= ~bits;
533 WRITE_CSR(TLP_GPIO, TLP_GPIO_DIR | (sc->gpio_dir));
537 make_gpio_output(softc_t *sc, u_int32_t bits)
539 sc->gpio_dir |= bits;
540 WRITE_CSR(TLP_GPIO, TLP_GPIO_DIR | (sc->gpio_dir));
544 read_gpio(softc_t *sc)
546 return READ_CSR(TLP_GPIO);
550 set_gpio_bits(softc_t *sc, u_int32_t bits)
552 WRITE_CSR(TLP_GPIO, (read_gpio(sc) | bits) & 0xFF);
556 clr_gpio_bits(softc_t *sc, u_int32_t bits)
558 WRITE_CSR(TLP_GPIO, (read_gpio(sc) & ~bits) & 0xFF);
561 /* Reset ALL of the flip-flops in the gate array to zero. */
562 /* This does NOT change the gate array programming. */
563 /* Called during initialization so it must not sleep. */
565 reset_xilinx(softc_t *sc)
567 /* Drive RESET low to force initialization. */
568 clr_gpio_bits(sc, GPIO_RESET);
569 make_gpio_output(sc, GPIO_RESET);
571 /* Hold RESET low for more than 10 uSec. */
574 /* Done with RESET; make it an input. */
575 make_gpio_input(sc, GPIO_RESET);
578 /* Load Xilinx gate array program from on-board rom. */
579 /* This changes the gate array programming. */
580 /* IOCTL SYSCALL: can sleep. */
582 load_xilinx_from_rom(softc_t *sc)
586 /* Drive MODE low to load from ROM rather than GPIO. */
587 clr_gpio_bits(sc, GPIO_MODE);
588 make_gpio_output(sc, GPIO_MODE);
590 /* Drive DP & RESET low to force configuration. */
591 clr_gpio_bits(sc, GPIO_RESET | GPIO_DP);
592 make_gpio_output(sc, GPIO_RESET | GPIO_DP);
594 /* Hold RESET & DP low for more than 10 uSec. */
597 /* Done with RESET & DP; make them inputs. */
598 make_gpio_input(sc, GPIO_DP | GPIO_RESET);
600 /* BUSY-WAIT for Xilinx chip to configure itself from ROM bits. */
601 for (i=0; i<100; i++) /* 1 sec max delay */
602 if ((read_gpio(sc) & GPIO_DP) == 0) SLEEP(10000);
604 /* Done with MODE; make it an input. */
605 make_gpio_input(sc, GPIO_MODE);
608 /* Load the Xilinx gate array program from userland bits. */
609 /* This changes the gate array programming. */
610 /* IOCTL SYSCALL: can sleep. */
612 load_xilinx_from_file(softc_t *sc, char *addr, u_int32_t len)
617 /* Get some pages to hold the Xilinx bits; biggest file is < 6 KB. */
618 if (len > 8192) return EFBIG; /* too big */
619 data = malloc(len, M_DEVBUF, M_WAITOK);
620 if (data == NULL) return ENOMEM;
622 /* Copy the Xilinx bits from userland. */
623 if ((error = copyin(addr, data, len)))
625 free(data, M_DEVBUF);
629 /* Drive MODE high to load from GPIO rather than ROM. */
630 set_gpio_bits(sc, GPIO_MODE);
631 make_gpio_output(sc, GPIO_MODE);
633 /* Drive DP & RESET low to force configuration. */
634 clr_gpio_bits(sc, GPIO_RESET | GPIO_DP);
635 make_gpio_output(sc, GPIO_RESET | GPIO_DP);
637 /* Hold RESET & DP low for more than 10 uSec. */
640 /* Done with RESET & DP; make them inputs. */
641 make_gpio_input(sc, GPIO_RESET | GPIO_DP);
643 /* BUSY-WAIT for Xilinx chip to clear its config memory. */
644 make_gpio_input(sc, GPIO_INIT);
645 for (i=0; i<10000; i++) /* 1 sec max delay */
646 if ((read_gpio(sc) & GPIO_INIT)==0) SLEEP(10000);
648 /* Configure CLK and DATA as outputs. */
649 set_gpio_bits(sc, GPIO_CLK); /* park CLK high */
650 make_gpio_output(sc, GPIO_CLK | GPIO_DATA);
652 /* Write bits to Xilinx; CLK is parked HIGH. */
653 /* DATA is set up before the RISING edge of CLK. */
654 for (i=0; i<len; i++)
657 if ((data[i] & (1<<j)) != 0)
658 set_gpio_bits(sc, GPIO_DATA); /* DATA setup */
660 clr_gpio_bits(sc, GPIO_DATA); /* DATA setup */
661 clr_gpio_bits(sc, GPIO_CLK); /* CLK falling edge */
662 set_gpio_bits(sc, GPIO_CLK); /* CLK rising edge */
665 /* Stop driving all Xilinx-related signals. */
666 /* Pullup and pulldown resistors take over. */
667 make_gpio_input(sc, GPIO_CLK | GPIO_DATA | GPIO_MODE);
669 free(data, M_DEVBUF);
673 /* Write fragments of a command into the synthesized oscillator. */
674 /* DATA is set up before the RISING edge of CLK. CLK is parked low. */
676 shift_synth_bits(softc_t *sc, u_int32_t data, u_int32_t len)
680 for (i=0; i<len; i++)
682 if ((data & (1<<i)) != 0)
683 set_gpio_bits(sc, GPIO_DATA); /* DATA setup */
685 clr_gpio_bits(sc, GPIO_DATA); /* DATA setup */
686 set_gpio_bits(sc, GPIO_CLK); /* CLK rising edge */
687 clr_gpio_bits(sc, GPIO_CLK); /* CLK falling edge */
691 /* Write a command to the synthesized oscillator on SSI and HSSIc. */
693 write_synth(softc_t *sc, struct synth *synth)
695 /* SSI cards have a programmable prescaler */
696 if (sc->status.card_type == TLP_CSID_SSI)
698 if (synth->prescale == 9) /* divide by 512 */
699 set_mii17_bits(sc, MII17_SSI_PRESCALE);
700 else /* divide by 32 */
701 clr_mii17_bits(sc, MII17_SSI_PRESCALE);
704 clr_gpio_bits(sc, GPIO_DATA | GPIO_CLK);
705 make_gpio_output(sc, GPIO_DATA | GPIO_CLK);
707 /* SYNTH is a low-true chip enable for the AV9110 chip. */
708 set_gpio_bits(sc, GPIO_SSI_SYNTH);
709 make_gpio_output(sc, GPIO_SSI_SYNTH);
710 clr_gpio_bits(sc, GPIO_SSI_SYNTH);
712 /* Serially shift the command into the AV9110 chip. */
713 shift_synth_bits(sc, synth->n, 7);
714 shift_synth_bits(sc, synth->m, 7);
715 shift_synth_bits(sc, synth->v, 1);
716 shift_synth_bits(sc, synth->x, 2);
717 shift_synth_bits(sc, synth->r, 2);
718 shift_synth_bits(sc, 0x16, 5); /* enable clk/x output */
720 /* SYNTH (chip enable) going high ends the command. */
721 set_gpio_bits(sc, GPIO_SSI_SYNTH);
722 make_gpio_input(sc, GPIO_SSI_SYNTH);
724 /* Stop driving serial-related signals; pullups/pulldowns take over. */
725 make_gpio_input(sc, GPIO_DATA | GPIO_CLK);
727 /* remember the new synthesizer parameters */
728 if (&sc->config.synth != synth) sc->config.synth = *synth;
731 /* Write a command to the DAC controlling the VCXO on some T3 adapters. */
732 /* The DAC is a TI-TLV5636: 12-bit resolution and a serial interface. */
733 /* DATA is set up before the FALLING edge of CLK. CLK is parked HIGH. */
735 write_dac(softc_t *sc, u_int16_t data)
739 /* Prepare to use DATA and CLK. */
740 set_gpio_bits(sc, GPIO_DATA | GPIO_CLK);
741 make_gpio_output(sc, GPIO_DATA | GPIO_CLK);
743 /* High-to-low transition prepares DAC for new value. */
744 set_gpio_bits(sc, GPIO_T3_DAC);
745 make_gpio_output(sc, GPIO_T3_DAC);
746 clr_gpio_bits(sc, GPIO_T3_DAC);
748 /* Serially shift command bits into DAC. */
751 if ((data & (1<<(15-i))) != 0)
752 set_gpio_bits(sc, GPIO_DATA); /* DATA setup */
754 clr_gpio_bits(sc, GPIO_DATA); /* DATA setup */
755 clr_gpio_bits(sc, GPIO_CLK); /* CLK falling edge */
756 set_gpio_bits(sc, GPIO_CLK); /* CLK rising edge */
759 /* Done with DAC; make it an input; loads new value into DAC. */
760 set_gpio_bits(sc, GPIO_T3_DAC);
761 make_gpio_input(sc, GPIO_T3_DAC);
763 /* Stop driving serial-related signals; pullups/pulldowns take over. */
764 make_gpio_input(sc, GPIO_DATA | GPIO_CLK);
767 /* begin HSSI card code */
769 /* Must not sleep. */
771 hssi_config(softc_t *sc)
773 if (sc->status.card_type == 0)
775 sc->status.card_type = READ_PCI_CFG(sc, TLP_CSID);
776 sc->config.crc_len = CFG_CRC_16;
777 sc->config.loop_back = CFG_LOOP_NONE;
778 sc->config.tx_clk_src = CFG_CLKMUX_ST;
779 sc->config.dte_dce = CFG_DTE;
780 sc->config.synth.n = 52; /* 52.000 Mbs */
781 sc->config.synth.m = 5;
782 sc->config.synth.v = 0;
783 sc->config.synth.x = 0;
784 sc->config.synth.r = 0;
785 sc->config.synth.prescale = 2;
789 if (sc->config.crc_len == CFG_CRC_32)
790 set_mii16_bits(sc, MII16_HSSI_CRC32);
792 clr_mii16_bits(sc, MII16_HSSI_CRC32);
794 /* Assert pin LA in HSSI conn: ask modem for local loop. */
795 if (sc->config.loop_back == CFG_LOOP_LL)
796 set_mii16_bits(sc, MII16_HSSI_LA);
798 clr_mii16_bits(sc, MII16_HSSI_LA);
800 /* Assert pin LB in HSSI conn: ask modem for remote loop. */
801 if (sc->config.loop_back == CFG_LOOP_RL)
802 set_mii16_bits(sc, MII16_HSSI_LB);
804 clr_mii16_bits(sc, MII16_HSSI_LB);
806 if (sc->status.card_type == TLP_CSID_HSSI)
809 if (sc->config.tx_clk_src == CFG_CLKMUX_ST)
810 set_gpio_bits(sc, GPIO_HSSI_TXCLK);
812 clr_gpio_bits(sc, GPIO_HSSI_TXCLK);
813 make_gpio_output(sc, GPIO_HSSI_TXCLK);
815 else if (sc->status.card_type == TLP_CSID_HSSIc)
816 { /* cPCI HSSI rev C has extra features */
817 /* Set TXCLK source. */
818 u_int16_t mii16 = read_mii(sc, 16);
819 mii16 &= ~MII16_HSSI_CLKMUX;
820 mii16 |= (sc->config.tx_clk_src&3)<<13;
821 write_mii(sc, 16, mii16);
823 /* cPCI HSSI implements loopback towards the net. */
824 if (sc->config.loop_back == CFG_LOOP_LINE)
825 set_mii16_bits(sc, MII16_HSSI_LOOP);
827 clr_mii16_bits(sc, MII16_HSSI_LOOP);
829 /* Set DTE/DCE mode. */
830 if (sc->config.dte_dce == CFG_DCE)
831 set_gpio_bits(sc, GPIO_HSSI_DCE);
833 clr_gpio_bits(sc, GPIO_HSSI_DCE);
834 make_gpio_output(sc, GPIO_HSSI_DCE);
836 /* Program the synthesized oscillator. */
837 write_synth(sc, &sc->config.synth);
842 hssi_ident(softc_t *sc)
846 /* Called once a second; must not sleep. */
848 hssi_watchdog(softc_t *sc)
850 u_int16_t mii16 = read_mii(sc, 16) & MII16_HSSI_MODEM;
851 int link_status = STATUS_UP;
853 led_inv(sc, MII16_HSSI_LED_UL); /* Software is alive. */
854 led_on(sc, MII16_HSSI_LED_LL); /* always on (SSI cable) */
856 /* Check the transmit clock. */
857 if (sc->status.tx_speed == 0)
859 led_on(sc, MII16_HSSI_LED_UR);
860 link_status = STATUS_DOWN;
863 led_off(sc, MII16_HSSI_LED_UR);
865 /* Is the modem ready? */
866 if ((mii16 & MII16_HSSI_CA) == 0)
868 led_off(sc, MII16_HSSI_LED_LR);
869 link_status = STATUS_DOWN;
872 led_on(sc, MII16_HSSI_LED_LR);
874 /* Print the modem control signals if they changed. */
875 if ((DRIVER_DEBUG) && (mii16 != sc->last_mii16))
877 char *on = "ON ", *off = "OFF";
878 printf("%s: TA=%s CA=%s LA=%s LB=%s LC=%s TM=%s\n", NAME_UNIT,
879 (mii16 & MII16_HSSI_TA) ? on : off,
880 (mii16 & MII16_HSSI_CA) ? on : off,
881 (mii16 & MII16_HSSI_LA) ? on : off,
882 (mii16 & MII16_HSSI_LB) ? on : off,
883 (mii16 & MII16_HSSI_LC) ? on : off,
884 (mii16 & MII16_HSSI_TM) ? on : off);
887 /* SNMP one-second-report */
888 sc->status.snmp.hssi.sigs = mii16 & MII16_HSSI_MODEM;
890 /* Remember this state until next time. */
891 sc->last_mii16 = mii16;
893 /* If a loop back is in effect, link status is UP */
894 if (sc->config.loop_back != CFG_LOOP_NONE)
895 link_status = STATUS_UP;
900 /* IOCTL SYSCALL: can sleep (but doesn't). */
902 hssi_ioctl(softc_t *sc, struct ioctl *ioctl)
906 if (ioctl->cmd == IOCTL_SNMP_SIGS)
908 u_int16_t mii16 = read_mii(sc, 16);
909 mii16 &= ~MII16_HSSI_MODEM;
910 mii16 |= (MII16_HSSI_MODEM & ioctl->data);
911 write_mii(sc, 16, mii16);
913 else if (ioctl->cmd == IOCTL_SET_STATUS)
915 if (ioctl->data != 0)
916 set_mii16_bits(sc, MII16_HSSI_TA);
918 clr_mii16_bits(sc, MII16_HSSI_TA);
926 /* begin DS3 card code */
928 /* Must not sleep. */
930 t3_config(softc_t *sc)
935 if (sc->status.card_type == 0)
937 sc->status.card_type = TLP_CSID_T3;
938 sc->config.crc_len = CFG_CRC_16;
939 sc->config.loop_back = CFG_LOOP_NONE;
940 sc->config.format = CFG_FORMAT_T3CPAR;
941 sc->config.cable_len = 10; /* meters */
942 sc->config.scrambler = CFG_SCRAM_DL_KEN;
943 sc->config.tx_clk_src = CFG_CLKMUX_INT;
945 /* Center the VCXO -- get within 20 PPM of 44736000. */
946 write_dac(sc, 0x9002); /* set Vref = 2.048 volts */
947 write_dac(sc, 2048); /* range is 0..4095 */
950 /* Set cable length. */
951 if (sc->config.cable_len > 30)
952 clr_mii16_bits(sc, MII16_DS3_ZERO);
954 set_mii16_bits(sc, MII16_DS3_ZERO);
956 /* Set payload scrambler polynomial. */
957 if (sc->config.scrambler == CFG_SCRAM_LARS)
958 set_mii16_bits(sc, MII16_DS3_POLY);
960 clr_mii16_bits(sc, MII16_DS3_POLY);
962 /* Set payload scrambler on/off. */
963 if (sc->config.scrambler == CFG_SCRAM_OFF)
964 clr_mii16_bits(sc, MII16_DS3_SCRAM);
966 set_mii16_bits(sc, MII16_DS3_SCRAM);
968 /* Set CRC length. */
969 if (sc->config.crc_len == CFG_CRC_32)
970 set_mii16_bits(sc, MII16_DS3_CRC32);
972 clr_mii16_bits(sc, MII16_DS3_CRC32);
974 /* Loopback towards host thru the line interface. */
975 if (sc->config.loop_back == CFG_LOOP_OTHER)
976 set_mii16_bits(sc, MII16_DS3_TRLBK);
978 clr_mii16_bits(sc, MII16_DS3_TRLBK);
980 /* Loopback towards network thru the line interface. */
981 if (sc->config.loop_back == CFG_LOOP_LINE)
982 set_mii16_bits(sc, MII16_DS3_LNLBK);
983 else if (sc->config.loop_back == CFG_LOOP_DUAL)
984 set_mii16_bits(sc, MII16_DS3_LNLBK);
986 clr_mii16_bits(sc, MII16_DS3_LNLBK);
988 /* Configure T3 framer chip; write EVERY writeable register. */
989 ctl1 = CTL1_SER | CTL1_XTX;
990 if (sc->config.loop_back == CFG_LOOP_INWARD) ctl1 |= CTL1_3LOOP;
991 if (sc->config.loop_back == CFG_LOOP_DUAL) ctl1 |= CTL1_3LOOP;
992 if (sc->config.format == CFG_FORMAT_T3M13) ctl1 |= CTL1_M13MODE;
993 write_framer(sc, T3CSR_CTL1, ctl1);
994 write_framer(sc, T3CSR_TX_FEAC, CTL5_EMODE);
995 write_framer(sc, T3CSR_CTL8, CTL8_FBEC);
996 write_framer(sc, T3CSR_CTL12, CTL12_DLCB1 | CTL12_C21 | CTL12_MCB1);
997 write_framer(sc, T3CSR_DBL_FEAC, 0);
998 write_framer(sc, T3CSR_CTL14, CTL14_RGCEN | CTL14_TGCEN);
999 write_framer(sc, T3CSR_INTEN, 0);
1000 write_framer(sc, T3CSR_CTL20, CTL20_CVEN);
1002 /* Clear error counters and latched error bits */
1003 /* that may have happened while initializing. */
1004 for (i=0; i<21; i++) read_framer(sc, i);
1008 t3_ident(softc_t *sc)
1010 printf(", TXC03401 rev B");
1013 /* Called once a second; must not sleep. */
1015 t3_watchdog(softc_t *sc)
1018 u_int8_t CERR, PERR, MERR, FERR, FEBE;
1019 u_int8_t ctl1, stat16, feac;
1020 int link_status = STATUS_UP;
1023 /* Read the alarm registers. */
1024 ctl1 = read_framer(sc, T3CSR_CTL1);
1025 stat16 = read_framer(sc, T3CSR_STAT16);
1026 mii16 = read_mii(sc, 16);
1028 /* Always ignore the RTLOC alarm bit. */
1029 stat16 &= ~STAT16_RTLOC;
1031 /* Software is alive. */
1032 led_inv(sc, MII16_DS3_LED_GRN);
1034 /* Receiving Alarm Indication Signal (AIS). */
1035 if ((stat16 & STAT16_RAIS) != 0) /* receiving ais */
1036 led_on(sc, MII16_DS3_LED_BLU);
1037 else if (ctl1 & CTL1_TXAIS) /* sending ais */
1038 led_inv(sc, MII16_DS3_LED_BLU);
1040 led_off(sc, MII16_DS3_LED_BLU);
1042 /* Receiving Remote Alarm Indication (RAI). */
1043 if ((stat16 & STAT16_XERR) != 0) /* receiving rai */
1044 led_on(sc, MII16_DS3_LED_YEL);
1045 else if ((ctl1 & CTL1_XTX) == 0) /* sending rai */
1046 led_inv(sc, MII16_DS3_LED_YEL);
1048 led_off(sc, MII16_DS3_LED_YEL);
1050 /* If certain status bits are set then the link is 'down'. */
1051 /* The bad bits are: rxlos rxoof rxais rxidl xerr. */
1052 if ((stat16 & ~(STAT16_FEAC | STAT16_SEF)) != 0)
1053 link_status = STATUS_DOWN;
1055 /* Declare local Red Alarm if the link is down. */
1056 if (link_status == STATUS_DOWN)
1057 led_on(sc, MII16_DS3_LED_RED);
1058 else if (sc->loop_timer != 0) /* loopback is active */
1059 led_inv(sc, MII16_DS3_LED_RED);
1061 led_off(sc, MII16_DS3_LED_RED);
1063 /* Print latched error bits if they changed. */
1064 if ((DRIVER_DEBUG) && ((stat16 & ~STAT16_FEAC) != sc->last_stat16))
1066 char *on = "ON ", *off = "OFF";
1067 printf("%s: RLOS=%s ROOF=%s RAIS=%s RIDL=%s SEF=%s XERR=%s\n",
1069 (stat16 & STAT16_RLOS) ? on : off,
1070 (stat16 & STAT16_ROOF) ? on : off,
1071 (stat16 & STAT16_RAIS) ? on : off,
1072 (stat16 & STAT16_RIDL) ? on : off,
1073 (stat16 & STAT16_SEF) ? on : off,
1074 (stat16 & STAT16_XERR) ? on : off);
1077 /* Check and print error counters if non-zero. */
1078 CV = read_framer(sc, T3CSR_CVHI)<<8;
1079 CV += read_framer(sc, T3CSR_CVLO);
1080 PERR = read_framer(sc, T3CSR_PERR);
1081 CERR = read_framer(sc, T3CSR_CERR);
1082 FERR = read_framer(sc, T3CSR_FERR);
1083 MERR = read_framer(sc, T3CSR_MERR);
1084 FEBE = read_framer(sc, T3CSR_FEBE);
1086 /* CV is invalid during LOS. */
1087 if ((stat16 & STAT16_RLOS)!=0) CV = 0;
1088 /* CERR & FEBE are invalid in M13 mode */
1089 if (sc->config.format == CFG_FORMAT_T3M13) CERR = FEBE = 0;
1090 /* FEBE is invalid during AIS. */
1091 if ((stat16 & STAT16_RAIS)!=0) FEBE = 0;
1092 if (DRIVER_DEBUG && (CV || PERR || CERR || FERR || MERR || FEBE))
1093 printf("%s: CV=%u PERR=%u CERR=%u FERR=%u MERR=%u FEBE=%u\n",
1094 NAME_UNIT, CV, PERR, CERR, FERR, MERR, FEBE);
1096 /* Driver keeps crude link-level error counters (SNMP is better). */
1097 sc->status.cntrs.lcv_errs += CV;
1098 sc->status.cntrs.par_errs += PERR;
1099 sc->status.cntrs.cpar_errs += CERR;
1100 sc->status.cntrs.frm_errs += FERR;
1101 sc->status.cntrs.mfrm_errs += MERR;
1102 sc->status.cntrs.febe_errs += FEBE;
1104 /* Check for FEAC messages (FEAC not defined in M13 mode). */
1105 if (FORMAT_T3CPAR && (stat16 & STAT16_FEAC)) do
1107 feac = read_framer(sc, T3CSR_FEAC_STK);
1108 if ((feac & FEAC_STK_VALID)==0) break;
1109 /* Ignore RxFEACs while a far end loopback has been requested. */
1110 if ((sc->status.snmp.t3.line & TLOOP_FAR_LINE)!=0) continue;
1111 switch (feac & FEAC_STK_FEAC)
1113 case T3BOP_LINE_UP: break;
1114 case T3BOP_LINE_DOWN: break;
1115 case T3BOP_LOOP_DS3:
1117 if (sc->last_FEAC == T3BOP_LINE_DOWN)
1120 printf("%s: Received a 'line loopback deactivate' FEAC msg\n", NAME_UNIT);
1121 clr_mii16_bits(sc, MII16_DS3_LNLBK);
1124 if (sc->last_FEAC == T3BOP_LINE_UP)
1127 printf("%s: Received a 'line loopback activate' FEAC msg\n", NAME_UNIT);
1128 set_mii16_bits(sc, MII16_DS3_LNLBK);
1129 sc->loop_timer = 300;
1136 printf("%s: Received a 'far end LOF' FEAC msg\n", NAME_UNIT);
1142 printf("%s: Received a 'far end IDL' FEAC msg\n", NAME_UNIT);
1148 printf("%s: Received a 'far end AIS' FEAC msg\n", NAME_UNIT);
1154 printf("%s: Received a 'far end LOS' FEAC msg\n", NAME_UNIT);
1160 printf("%s: Received a 'type 0x%02X' FEAC msg\n", NAME_UNIT, feac & FEAC_STK_FEAC);
1164 sc->last_FEAC = feac & FEAC_STK_FEAC;
1165 } while ((feac & FEAC_STK_MORE) != 0);
1166 stat16 &= ~STAT16_FEAC;
1168 /* Send Service-Affecting priority FEAC messages */
1169 if (((sc->last_stat16 ^ stat16) & 0xF0) && (FORMAT_T3CPAR))
1171 /* Transmit continuous FEACs */
1172 write_framer(sc, T3CSR_CTL14,
1173 read_framer(sc, T3CSR_CTL14) & ~CTL14_FEAC10);
1174 if ((stat16 & STAT16_RLOS)!=0)
1175 write_framer(sc, T3CSR_TX_FEAC, 0xC0 + T3BOP_LOS);
1176 else if ((stat16 & STAT16_ROOF)!=0)
1177 write_framer(sc, T3CSR_TX_FEAC, 0xC0 + T3BOP_OOF);
1178 else if ((stat16 & STAT16_RAIS)!=0)
1179 write_framer(sc, T3CSR_TX_FEAC, 0xC0 + T3BOP_AIS);
1180 else if ((stat16 & STAT16_RIDL)!=0)
1181 write_framer(sc, T3CSR_TX_FEAC, 0xC0 + T3BOP_IDLE);
1183 write_framer(sc, T3CSR_TX_FEAC, CTL5_EMODE);
1186 /* Start sending RAI, Remote Alarm Indication. */
1187 if (((stat16 & STAT16_ROOF)!=0) && ((stat16 & STAT16_RLOS)==0) &&
1188 ((sc->last_stat16 & STAT16_ROOF)==0))
1189 write_framer(sc, T3CSR_CTL1, ctl1 &= ~CTL1_XTX);
1190 /* Stop sending RAI, Remote Alarm Indication. */
1191 else if (((stat16 & STAT16_ROOF)==0) && ((sc->last_stat16 & STAT16_ROOF)!=0))
1192 write_framer(sc, T3CSR_CTL1, ctl1 |= CTL1_XTX);
1194 /* Start sending AIS, Alarm Indication Signal */
1195 if (((stat16 & STAT16_RLOS)!=0) && ((sc->last_stat16 & STAT16_RLOS)==0))
1197 set_mii16_bits(sc, MII16_DS3_FRAME);
1198 write_framer(sc, T3CSR_CTL1, ctl1 | CTL1_TXAIS);
1200 /* Stop sending AIS, Alarm Indication Signal */
1201 else if (((stat16 & STAT16_RLOS)==0) && ((sc->last_stat16 & STAT16_RLOS)!=0))
1203 clr_mii16_bits(sc, MII16_DS3_FRAME);
1204 write_framer(sc, T3CSR_CTL1, ctl1 & ~CTL1_TXAIS);
1207 /* Time out loopback requests. */
1208 if (sc->loop_timer != 0)
1209 if (--sc->loop_timer == 0)
1210 if ((mii16 & MII16_DS3_LNLBK)!=0)
1213 printf("%s: Timeout: Loop Down after 300 seconds\n", NAME_UNIT);
1214 clr_mii16_bits(sc, MII16_DS3_LNLBK); /* line loopback off */
1217 /* SNMP error counters */
1218 sc->status.snmp.t3.lcv = CV;
1219 sc->status.snmp.t3.pcv = PERR;
1220 sc->status.snmp.t3.ccv = CERR;
1221 sc->status.snmp.t3.febe = FEBE;
1223 /* SNMP Line Status */
1224 sc->status.snmp.t3.line = 0;
1225 if ((ctl1 & CTL1_XTX)==0) sc->status.snmp.t3.line |= TLINE_TX_RAI;
1226 if (stat16 & STAT16_XERR) sc->status.snmp.t3.line |= TLINE_RX_RAI;
1227 if (ctl1 & CTL1_TXAIS) sc->status.snmp.t3.line |= TLINE_TX_AIS;
1228 if (stat16 & STAT16_RAIS) sc->status.snmp.t3.line |= TLINE_RX_AIS;
1229 if (stat16 & STAT16_ROOF) sc->status.snmp.t3.line |= TLINE_LOF;
1230 if (stat16 & STAT16_RLOS) sc->status.snmp.t3.line |= TLINE_LOS;
1231 if (stat16 & STAT16_SEF) sc->status.snmp.t3.line |= T3LINE_SEF;
1233 /* SNMP Loopback Status */
1234 sc->status.snmp.t3.loop &= ~TLOOP_FAR_LINE;
1235 if (sc->config.loop_back == CFG_LOOP_TULIP)
1236 sc->status.snmp.t3.loop |= TLOOP_NEAR_OTHER;
1237 if (ctl1 & CTL1_3LOOP) sc->status.snmp.t3.loop |= TLOOP_NEAR_INWARD;
1238 if (mii16 & MII16_DS3_TRLBK) sc->status.snmp.t3.loop |= TLOOP_NEAR_OTHER;
1239 if (mii16 & MII16_DS3_LNLBK) sc->status.snmp.t3.loop |= TLOOP_NEAR_LINE;
1240 /*if (ctl12 & CTL12_RTPLOOP) sc->status.snmp.t3.loop |= TLOOP_NEAR_PAYLOAD; */
1242 /* Remember this state until next time. */
1243 sc->last_stat16 = stat16;
1245 /* If an INWARD loopback is in effect, link status is UP */
1246 if (sc->config.loop_back != CFG_LOOP_NONE) /* XXX INWARD ONLY */
1247 link_status = STATUS_UP;
1252 /* IOCTL SYSCALL: can sleep. */
1254 t3_send_dbl_feac(softc_t *sc, int feac1, int feac2)
1259 /* The FEAC transmitter could be sending a continuous */
1260 /* FEAC msg when told to send a double FEAC message. */
1261 /* So save the current state of the FEAC transmitter. */
1262 tx_feac = read_framer(sc, T3CSR_TX_FEAC);
1263 /* Load second FEAC code and stop FEAC transmitter. */
1264 write_framer(sc, T3CSR_TX_FEAC, CTL5_EMODE + feac2);
1265 /* FEAC transmitter sends 10 more FEACs and then stops. */
1266 SLEEP(20000); /* sending one FEAC takes 1700 uSecs */
1267 /* Load first FEAC code and start FEAC transmitter. */
1268 write_framer(sc, T3CSR_DBL_FEAC, CTL13_DFEXEC + feac1);
1269 /* Wait for double FEAC sequence to complete -- about 70 ms. */
1270 for (i=0; i<10; i++) /* max delay 100 ms */
1271 if (read_framer(sc, T3CSR_DBL_FEAC) & CTL13_DFEXEC) SLEEP(10000);
1272 /* Flush received FEACS; don't respond to our own loop cmd! */
1273 while (read_framer(sc, T3CSR_FEAC_STK) & FEAC_STK_VALID) DELAY(1); /* XXX HANG */
1274 /* Restore previous state of the FEAC transmitter. */
1275 /* If it was sending a continuous FEAC, it will resume. */
1276 write_framer(sc, T3CSR_TX_FEAC, tx_feac);
1279 /* IOCTL SYSCALL: can sleep. */
1281 t3_ioctl(softc_t *sc, struct ioctl *ioctl)
1287 case IOCTL_SNMP_SEND: /* set opstatus? */
1289 if (sc->config.format != CFG_FORMAT_T3CPAR)
1291 else if (ioctl->data == TSEND_LINE)
1293 sc->status.snmp.t3.loop |= TLOOP_FAR_LINE;
1294 t3_send_dbl_feac(sc, T3BOP_LINE_UP, T3BOP_LOOP_DS3);
1296 else if (ioctl->data == TSEND_RESET)
1298 t3_send_dbl_feac(sc, T3BOP_LINE_DOWN, T3BOP_LOOP_DS3);
1299 sc->status.snmp.t3.loop &= ~TLOOP_FAR_LINE;
1305 case IOCTL_SNMP_LOOP: /* set opstatus = test? */
1307 if (ioctl->data == CFG_LOOP_NONE)
1309 clr_mii16_bits(sc, MII16_DS3_FRAME);
1310 clr_mii16_bits(sc, MII16_DS3_TRLBK);
1311 clr_mii16_bits(sc, MII16_DS3_LNLBK);
1312 write_framer(sc, T3CSR_CTL1,
1313 read_framer(sc, T3CSR_CTL1) & ~CTL1_3LOOP);
1314 write_framer(sc, T3CSR_CTL12,
1315 read_framer(sc, T3CSR_CTL12) & ~(CTL12_RTPLOOP | CTL12_RTPLLEN));
1317 else if (ioctl->data == CFG_LOOP_LINE)
1318 set_mii16_bits(sc, MII16_DS3_LNLBK);
1319 else if (ioctl->data == CFG_LOOP_OTHER)
1320 set_mii16_bits(sc, MII16_DS3_TRLBK);
1321 else if (ioctl->data == CFG_LOOP_INWARD)
1322 write_framer(sc, T3CSR_CTL1,
1323 read_framer(sc, T3CSR_CTL1) | CTL1_3LOOP);
1324 else if (ioctl->data == CFG_LOOP_DUAL)
1326 set_mii16_bits(sc, MII16_DS3_LNLBK);
1327 write_framer(sc, T3CSR_CTL1,
1328 read_framer(sc, T3CSR_CTL1) | CTL1_3LOOP);
1330 else if (ioctl->data == CFG_LOOP_PAYLOAD)
1332 set_mii16_bits(sc, MII16_DS3_FRAME);
1333 write_framer(sc, T3CSR_CTL12,
1334 read_framer(sc, T3CSR_CTL12) | CTL12_RTPLOOP);
1335 write_framer(sc, T3CSR_CTL12,
1336 read_framer(sc, T3CSR_CTL12) | CTL12_RTPLLEN);
1337 DELAY(25); /* at least two frames (22 uS) */
1338 write_framer(sc, T3CSR_CTL12,
1339 read_framer(sc, T3CSR_CTL12) & ~CTL12_RTPLLEN);
1353 /* begin SSI card code */
1355 /* Must not sleep. */
1357 ssi_config(softc_t *sc)
1359 if (sc->status.card_type == 0)
1361 sc->status.card_type = TLP_CSID_SSI;
1362 sc->config.crc_len = CFG_CRC_16;
1363 sc->config.loop_back = CFG_LOOP_NONE;
1364 sc->config.tx_clk_src = CFG_CLKMUX_ST;
1365 sc->config.dte_dce = CFG_DTE;
1366 sc->config.synth.n = 51; /* 1.536 MHz */
1367 sc->config.synth.m = 83;
1368 sc->config.synth.v = 1;
1369 sc->config.synth.x = 1;
1370 sc->config.synth.r = 1;
1371 sc->config.synth.prescale = 4;
1374 /* Disable the TX clock driver while programming the oscillator. */
1375 clr_gpio_bits(sc, GPIO_SSI_DCE);
1376 make_gpio_output(sc, GPIO_SSI_DCE);
1378 /* Program the synthesized oscillator. */
1379 write_synth(sc, &sc->config.synth);
1381 /* Set DTE/DCE mode. */
1382 /* If DTE mode then DCD & TXC are received. */
1383 /* If DCE mode then DCD & TXC are driven. */
1384 /* Boards with MII rev=4.0 don't drive DCD. */
1385 if (sc->config.dte_dce == CFG_DCE)
1386 set_gpio_bits(sc, GPIO_SSI_DCE);
1388 clr_gpio_bits(sc, GPIO_SSI_DCE);
1389 make_gpio_output(sc, GPIO_SSI_DCE);
1391 /* Set CRC length. */
1392 if (sc->config.crc_len == CFG_CRC_32)
1393 set_mii16_bits(sc, MII16_SSI_CRC32);
1395 clr_mii16_bits(sc, MII16_SSI_CRC32);
1397 /* Loop towards host thru cable drivers and receivers. */
1398 /* Asserts DCD at the far end of a null modem cable. */
1399 if (sc->config.loop_back == CFG_LOOP_PINS)
1400 set_mii16_bits(sc, MII16_SSI_LOOP);
1402 clr_mii16_bits(sc, MII16_SSI_LOOP);
1404 /* Assert pin LL in modem conn: ask modem for local loop. */
1405 /* Asserts TM at the far end of a null modem cable. */
1406 if (sc->config.loop_back == CFG_LOOP_LL)
1407 set_mii16_bits(sc, MII16_SSI_LL);
1409 clr_mii16_bits(sc, MII16_SSI_LL);
1411 /* Assert pin RL in modem conn: ask modem for remote loop. */
1412 if (sc->config.loop_back == CFG_LOOP_RL)
1413 set_mii16_bits(sc, MII16_SSI_RL);
1415 clr_mii16_bits(sc, MII16_SSI_RL);
1419 ssi_ident(softc_t *sc)
1421 printf(", LTC1343/44");
1424 /* Called once a second; must not sleep. */
1426 ssi_watchdog(softc_t *sc)
1429 u_int16_t mii16 = read_mii(sc, 16) & MII16_SSI_MODEM;
1430 int link_status = STATUS_UP;
1432 /* Software is alive. */
1433 led_inv(sc, MII16_SSI_LED_UL);
1435 /* Check the transmit clock. */
1436 if (sc->status.tx_speed == 0)
1438 led_on(sc, MII16_SSI_LED_UR);
1439 link_status = STATUS_DOWN;
1442 led_off(sc, MII16_SSI_LED_UR);
1444 /* Check the external cable. */
1445 cable = read_mii(sc, 17);
1446 cable = cable & MII17_SSI_CABLE_MASK;
1447 cable = cable >> MII17_SSI_CABLE_SHIFT;
1450 led_off(sc, MII16_SSI_LED_LL); /* no cable */
1451 link_status = STATUS_DOWN;
1454 led_on(sc, MII16_SSI_LED_LL);
1456 /* The unit at the other end of the cable is ready if: */
1457 /* DTE mode and DCD pin is asserted */
1458 /* DCE mode and DSR pin is asserted */
1459 if (((sc->config.dte_dce == CFG_DTE) && ((mii16 & MII16_SSI_DCD)==0)) ||
1460 ((sc->config.dte_dce == CFG_DCE) && ((mii16 & MII16_SSI_DSR)==0)))
1462 led_off(sc, MII16_SSI_LED_LR);
1463 link_status = STATUS_DOWN;
1466 led_on(sc, MII16_SSI_LED_LR);
1468 if (DRIVER_DEBUG && (cable != sc->status.cable_type))
1469 printf("%s: SSI cable type changed to '%s'\n",
1470 NAME_UNIT, ssi_cables[cable]);
1471 sc->status.cable_type = cable;
1473 /* Print the modem control signals if they changed. */
1474 if ((DRIVER_DEBUG) && (mii16 != sc->last_mii16))
1476 char *on = "ON ", *off = "OFF";
1477 printf("%s: DTR=%s DSR=%s RTS=%s CTS=%s DCD=%s RI=%s LL=%s RL=%s TM=%s\n",
1479 (mii16 & MII16_SSI_DTR) ? on : off,
1480 (mii16 & MII16_SSI_DSR) ? on : off,
1481 (mii16 & MII16_SSI_RTS) ? on : off,
1482 (mii16 & MII16_SSI_CTS) ? on : off,
1483 (mii16 & MII16_SSI_DCD) ? on : off,
1484 (mii16 & MII16_SSI_RI) ? on : off,
1485 (mii16 & MII16_SSI_LL) ? on : off,
1486 (mii16 & MII16_SSI_RL) ? on : off,
1487 (mii16 & MII16_SSI_TM) ? on : off);
1490 /* SNMP one-second report */
1491 sc->status.snmp.ssi.sigs = mii16 & MII16_SSI_MODEM;
1493 /* Remember this state until next time. */
1494 sc->last_mii16 = mii16;
1496 /* If a loop back is in effect, link status is UP */
1497 if (sc->config.loop_back != CFG_LOOP_NONE)
1498 link_status = STATUS_UP;
1503 /* IOCTL SYSCALL: can sleep (but doesn't). */
1505 ssi_ioctl(softc_t *sc, struct ioctl *ioctl)
1509 if (ioctl->cmd == IOCTL_SNMP_SIGS)
1511 u_int16_t mii16 = read_mii(sc, 16);
1512 mii16 &= ~MII16_SSI_MODEM;
1513 mii16 |= (MII16_SSI_MODEM & ioctl->data);
1514 write_mii(sc, 16, mii16);
1516 else if (ioctl->cmd == IOCTL_SET_STATUS)
1518 if (ioctl->data != 0)
1519 set_mii16_bits(sc, (MII16_SSI_DTR | MII16_SSI_RTS | MII16_SSI_DCD));
1521 clr_mii16_bits(sc, (MII16_SSI_DTR | MII16_SSI_RTS | MII16_SSI_DCD));
1529 /* begin T1E1 card code */
1531 /* Must not sleep. */
1533 t1_config(softc_t *sc)
1536 u_int8_t pulse, lbo, gain;
1538 if (sc->status.card_type == 0)
1540 sc->status.card_type = TLP_CSID_T1E1;
1541 sc->config.crc_len = CFG_CRC_16;
1542 sc->config.loop_back = CFG_LOOP_NONE;
1543 sc->config.tx_clk_src = CFG_CLKMUX_INT;
1544 sc->config.format = CFG_FORMAT_T1ESF;
1545 sc->config.cable_len = 10;
1546 sc->config.time_slots = 0x01FFFFFE;
1547 sc->config.tx_pulse = CFG_PULSE_AUTO;
1548 sc->config.rx_gain = CFG_GAIN_AUTO;
1549 sc->config.tx_lbo = CFG_LBO_AUTO;
1551 /* Bt8370 occasionally powers up in a loopback mode. */
1552 /* Data sheet says zero LOOP reg and do a s/w reset. */
1553 write_framer(sc, Bt8370_LOOP, 0x00); /* no loopback */
1554 write_framer(sc, Bt8370_CR0, 0x80); /* s/w reset */
1555 for (i=0; i<10; i++) /* max delay 10 ms */
1556 if (read_framer(sc, Bt8370_CR0) & 0x80) DELAY(1000);
1559 /* Set CRC length. */
1560 if (sc->config.crc_len == CFG_CRC_32)
1561 set_mii16_bits(sc, MII16_T1_CRC32);
1563 clr_mii16_bits(sc, MII16_T1_CRC32);
1565 /* Invert HDLC payload data in SF/AMI mode. */
1566 /* HDLC stuff bits satisfy T1 pulse density. */
1568 set_mii16_bits(sc, MII16_T1_INVERT);
1570 clr_mii16_bits(sc, MII16_T1_INVERT);
1572 /* Set the transmitter output impedance. */
1573 if (FORMAT_E1ANY) set_mii16_bits(sc, MII16_T1_Z);
1575 /* 001:CR0 -- Control Register 0 - T1/E1 and frame format */
1576 write_framer(sc, Bt8370_CR0, sc->config.format);
1578 /* 002:JAT_CR -- Jitter Attenuator Control Register */
1579 if (sc->config.tx_clk_src == CFG_CLKMUX_RT) /* loop timing */
1580 write_framer(sc, Bt8370_JAT_CR, 0xA3); /* JAT in RX path */
1582 { /* 64-bit elastic store; free-running JCLK and CLADO */
1583 write_framer(sc, Bt8370_JAT_CR, 0x4B); /* assert jcenter */
1584 write_framer(sc, Bt8370_JAT_CR, 0x43); /* release jcenter */
1587 /* 00C-013:IERn -- Interrupt Enable Registers */
1588 for (i=Bt8370_IER7; i<=Bt8370_IER0; i++)
1589 write_framer(sc, i, 0); /* no interrupts; polled */
1591 /* 014:LOOP -- loopbacks */
1592 if (sc->config.loop_back == CFG_LOOP_PAYLOAD)
1593 write_framer(sc, Bt8370_LOOP, LOOP_PAYLOAD);
1594 else if (sc->config.loop_back == CFG_LOOP_LINE)
1595 write_framer(sc, Bt8370_LOOP, LOOP_LINE);
1596 else if (sc->config.loop_back == CFG_LOOP_OTHER)
1597 write_framer(sc, Bt8370_LOOP, LOOP_ANALOG);
1598 else if (sc->config.loop_back == CFG_LOOP_INWARD)
1599 write_framer(sc, Bt8370_LOOP, LOOP_FRAMER);
1600 else if (sc->config.loop_back == CFG_LOOP_DUAL)
1601 write_framer(sc, Bt8370_LOOP, LOOP_DUAL);
1603 write_framer(sc, Bt8370_LOOP, 0x00); /* no loopback */
1605 /* 015:DL3_TS -- Data Link 3 */
1606 write_framer(sc, Bt8370_DL3_TS, 0x00); /* disabled */
1608 /* 018:PIO -- Programmable I/O */
1609 write_framer(sc, Bt8370_PIO, 0xFF); /* all pins are outputs */
1611 /* 019:POE -- Programmable Output Enable */
1612 write_framer(sc, Bt8370_POE, 0x00); /* all outputs are enabled */
1614 /* 01A;CMUX -- Clock Input Mux */
1615 if (sc->config.tx_clk_src == CFG_CLKMUX_EXT)
1616 write_framer(sc, Bt8370_CMUX, 0x0C); /* external timing */
1618 write_framer(sc, Bt8370_CMUX, 0x0F); /* internal timing */
1620 /* 020:LIU_CR -- Line Interface Unit Config Register */
1621 write_framer(sc, Bt8370_LIU_CR, 0xC1); /* reset LIU, squelch */
1623 /* 022:RLIU_CR -- RX Line Interface Unit Config Reg */
1624 /* Errata sheet says don't use freeze-short, but we do anyway! */
1625 write_framer(sc, Bt8370_RLIU_CR, 0xB1); /* AGC=2048, Long Eye */
1627 /* Select Rx sensitivity based on cable length. */
1628 if ((gain = sc->config.rx_gain) == CFG_GAIN_AUTO)
1630 if (sc->config.cable_len > 2000)
1631 gain = CFG_GAIN_EXTEND;
1632 else if (sc->config.cable_len > 1000)
1633 gain = CFG_GAIN_LONG;
1634 else if (sc->config.cable_len > 100)
1635 gain = CFG_GAIN_MEDIUM;
1637 gain = CFG_GAIN_SHORT;
1640 /* 024:VGA_MAX -- Variable Gain Amplifier Max gain */
1641 write_framer(sc, Bt8370_VGA_MAX, gain);
1643 /* 028:PRE_EQ -- Pre Equalizer */
1644 if (gain == CFG_GAIN_EXTEND)
1645 write_framer(sc, Bt8370_PRE_EQ, 0xE6); /* ON; thresh 6 */
1647 write_framer(sc, Bt8370_PRE_EQ, 0xA6); /* OFF; thresh 6 */
1649 /* 038-03C:GAINn -- RX Equalizer gain thresholds */
1650 write_framer(sc, Bt8370_GAIN0, 0x24);
1651 write_framer(sc, Bt8370_GAIN1, 0x28);
1652 write_framer(sc, Bt8370_GAIN2, 0x2C);
1653 write_framer(sc, Bt8370_GAIN3, 0x30);
1654 write_framer(sc, Bt8370_GAIN4, 0x34);
1656 /* 040:RCR0 -- Receiver Control Register 0 */
1658 write_framer(sc, Bt8370_RCR0, 0x05); /* B8ZS, 2/5 FErrs */
1659 else if (FORMAT_T1SF)
1660 write_framer(sc, Bt8370_RCR0, 0x84); /* AMI, 2/5 FErrs */
1661 else if (FORMAT_E1NONE)
1662 write_framer(sc, Bt8370_RCR0, 0x41); /* HDB3, rabort */
1663 else if (FORMAT_E1CRC)
1664 write_framer(sc, Bt8370_RCR0, 0x09); /* HDB3, 3 FErrs or 915 CErrs */
1665 else /* E1 no CRC */
1666 write_framer(sc, Bt8370_RCR0, 0x19); /* HDB3, 3 FErrs */
1668 /* 041:RPATT -- Receive Test Pattern configuration */
1669 write_framer(sc, Bt8370_RPATT, 0x3E); /* looking for framed QRSS */
1671 /* 042:RLB -- Receive Loop Back code detector config */
1672 write_framer(sc, Bt8370_RLB, 0x09); /* 6 bits down; 5 bits up */
1674 /* 043:LBA -- Loop Back Activate code */
1675 write_framer(sc, Bt8370_LBA, 0x08); /* 10000 10000 10000 ... */
1677 /* 044:LBD -- Loop Back Deactivate code */
1678 write_framer(sc, Bt8370_LBD, 0x24); /* 100100 100100 100100 ... */
1680 /* 045:RALM -- Receive Alarm signal configuration */
1681 write_framer(sc, Bt8370_RALM, 0x0C); /* yel_intg rlof_intg */
1683 /* 046:LATCH -- Alarm/Error/Counter Latch register */
1684 write_framer(sc, Bt8370_LATCH, 0x1F); /* stop_cnt latch_{cnt,err,alm} */
1686 /* Select Pulse Shape based on cable length (T1 only). */
1687 if ((pulse = sc->config.tx_pulse) == CFG_PULSE_AUTO)
1691 if (sc->config.cable_len > 200)
1692 pulse = CFG_PULSE_T1CSU;
1693 else if (sc->config.cable_len > 160)
1694 pulse = CFG_PULSE_T1DSX4;
1695 else if (sc->config.cable_len > 120)
1696 pulse = CFG_PULSE_T1DSX3;
1697 else if (sc->config.cable_len > 80)
1698 pulse = CFG_PULSE_T1DSX2;
1699 else if (sc->config.cable_len > 40)
1700 pulse = CFG_PULSE_T1DSX1;
1702 pulse = CFG_PULSE_T1DSX0;
1705 pulse = CFG_PULSE_E1TWIST;
1708 /* Select Line Build Out based on cable length (T1CSU only). */
1709 if ((lbo = sc->config.tx_lbo) == CFG_LBO_AUTO)
1711 if (pulse == CFG_PULSE_T1CSU)
1713 if (sc->config.cable_len > 1500)
1715 else if (sc->config.cable_len > 1000)
1717 else if (sc->config.cable_len > 500)
1726 /* 068:TLIU_CR -- Transmit LIU Control Register */
1727 write_framer(sc, Bt8370_TLIU_CR, (0x40 | (lbo & 0x30) | (pulse & 0x0E)));
1729 /* 070:TCR0 -- Transmit Framer Configuration */
1730 write_framer(sc, Bt8370_TCR0, sc->config.format>>1);
1732 /* 071:TCR1 -- Transmitter Configuration */
1734 write_framer(sc, Bt8370_TCR1, 0x43); /* tabort, AMI PDV enforced */
1736 write_framer(sc, Bt8370_TCR1, 0x41); /* tabort, B8ZS or HDB3 */
1738 /* 072:TFRM -- Transmit Frame format MYEL YEL MF FE CRC FBIT */
1739 if (sc->config.format == CFG_FORMAT_T1ESF)
1740 write_framer(sc, Bt8370_TFRM, 0x0B); /* - YEL MF - CRC FBIT */
1741 else if (sc->config.format == CFG_FORMAT_T1SF)
1742 write_framer(sc, Bt8370_TFRM, 0x19); /* - YEL MF - - FBIT */
1743 else if (sc->config.format == CFG_FORMAT_E1FAS)
1744 write_framer(sc, Bt8370_TFRM, 0x11); /* - YEL - - - FBIT */
1745 else if (sc->config.format == CFG_FORMAT_E1FASCRC)
1746 write_framer(sc, Bt8370_TFRM, 0x1F); /* - YEL MF FE CRC FBIT */
1747 else if (sc->config.format == CFG_FORMAT_E1FASCAS)
1748 write_framer(sc, Bt8370_TFRM, 0x31); /* MYEL YEL - - - FBIT */
1749 else if (sc->config.format == CFG_FORMAT_E1FASCRCCAS)
1750 write_framer(sc, Bt8370_TFRM, 0x3F); /* MYEL YEL MF FE CRC FBIT */
1751 else if (sc->config.format == CFG_FORMAT_E1NONE)
1752 write_framer(sc, Bt8370_TFRM, 0x00); /* NO FRAMING BITS AT ALL! */
1754 /* 073:TERROR -- Transmit Error Insert */
1755 write_framer(sc, Bt8370_TERROR, 0x00); /* no errors, please! */
1757 /* 074:TMAN -- Transmit Manual Sa-byte/FEBE configuration */
1758 write_framer(sc, Bt8370_TMAN, 0x00); /* none */
1760 /* 075:TALM -- Transmit Alarm Signal Configuration */
1762 write_framer(sc, Bt8370_TALM, 0x38); /* auto_myel auto_yel auto_ais */
1763 else if (FORMAT_T1ANY)
1764 write_framer(sc, Bt8370_TALM, 0x18); /* auto_yel auto_ais */
1766 /* 076:TPATT -- Transmit Test Pattern Configuration */
1767 write_framer(sc, Bt8370_TPATT, 0x00); /* disabled */
1769 /* 077:TLB -- Transmit Inband Loopback Code Configuration */
1770 write_framer(sc, Bt8370_TLB, 0x00); /* disabled */
1772 /* 090:CLAD_CR -- Clack Rate Adapter Configuration */
1774 write_framer(sc, Bt8370_CLAD_CR, 0x06); /* loop filter gain 1/2^6 */
1776 write_framer(sc, Bt8370_CLAD_CR, 0x08); /* loop filter gain 1/2^8 */
1778 /* 091:CSEL -- CLAD frequency Select */
1780 write_framer(sc, Bt8370_CSEL, 0x55); /* 1544 kHz */
1782 write_framer(sc, Bt8370_CSEL, 0x11); /* 2048 kHz */
1784 /* 092:CPHASE -- CLAD Phase detector */
1786 write_framer(sc, Bt8370_CPHASE, 0x22); /* phase compare @ 386 kHz */
1788 write_framer(sc, Bt8370_CPHASE, 0x00); /* phase compare @ 2048 kHz */
1790 if (FORMAT_T1ESF) /* BOP & PRM are enabled in T1ESF mode only. */
1792 /* 0A0:BOP -- Bit Oriented Protocol messages */
1793 write_framer(sc, Bt8370_BOP, RBOP_25 | TBOP_OFF);
1794 /* 0A4:DL1_TS -- Data Link 1 Time Slot Enable */
1795 write_framer(sc, Bt8370_DL1_TS, 0x40); /* FDL bits in odd frames */
1796 /* 0A6:DL1_CTL -- Data Link 1 Control */
1797 write_framer(sc, Bt8370_DL1_CTL, 0x03); /* FCS mode, TX on, RX on */
1798 /* 0A7:RDL1_FFC -- Rx Data Link 1 Fifo Fill Control */
1799 write_framer(sc, Bt8370_RDL1_FFC, 0x30); /* assert "near full" at 48 */
1800 /* 0AA:PRM -- Performance Report Messages */
1801 write_framer(sc, Bt8370_PRM, 0x80);
1804 /* 0D0:SBI_CR -- System Bus Interface Configuration Register */
1806 write_framer(sc, Bt8370_SBI_CR, 0x47); /* 1.544 with 24 TS +Fbits */
1808 write_framer(sc, Bt8370_SBI_CR, 0x46); /* 2.048 with 32 TS */
1810 /* 0D1:RSB_CR -- Receive System Bus Configuration Register */
1811 /* Change RINDO & RFSYNC on falling edge of RSBCLKI. */
1812 write_framer(sc, Bt8370_RSB_CR, 0x70);
1814 /* 0D2,0D3:RSYNC_{TS,BIT} -- Receive frame Sync offset */
1815 write_framer(sc, Bt8370_RSYNC_BIT, 0x00);
1816 write_framer(sc, Bt8370_RSYNC_TS, 0x00);
1818 /* 0D4:TSB_CR -- Transmit System Bus Configuration Register */
1819 /* Change TINDO & TFSYNC on falling edge of TSBCLKI. */
1820 write_framer(sc, Bt8370_TSB_CR, 0x30);
1822 /* 0D5,0D6:TSYNC_{TS,BIT} -- Transmit frame Sync offset */
1823 write_framer(sc, Bt8370_TSYNC_BIT, 0x00);
1824 write_framer(sc, Bt8370_TSYNC_TS, 0x00);
1826 /* 0D7:RSIG_CR -- Receive SIGnalling Configuratin Register */
1827 write_framer(sc, Bt8370_RSIG_CR, 0x00);
1829 /* Assign and configure 64Kb TIME SLOTS. */
1830 /* TS24..TS1 must be assigned for T1, TS31..TS0 for E1. */
1831 /* Timeslots with no user data have RINDO and TINDO off. */
1832 for (i=0; i<32; i++)
1834 /* 0E0-0FF:SBCn -- System Bus Per-Channel Control */
1835 if (FORMAT_T1ANY && (i==0 || i>24))
1836 write_framer(sc, Bt8370_SBCn +i, 0x00); /* not assigned in T1 mode */
1837 else if (FORMAT_E1ANY && (i==0) && !FORMAT_E1NONE)
1838 write_framer(sc, Bt8370_SBCn +i, 0x01); /* assigned, TS0 o/h bits */
1839 else if (FORMAT_E1CAS && (i==16) && !FORMAT_E1NONE)
1840 write_framer(sc, Bt8370_SBCn +i, 0x01); /* assigned, TS16 o/h bits */
1841 else if ((sc->config.time_slots & (1<<i)) != 0)
1842 write_framer(sc, Bt8370_SBCn +i, 0x0D); /* assigned, RINDO, TINDO */
1844 write_framer(sc, Bt8370_SBCn +i, 0x01); /* assigned, idle */
1846 /* 100-11F:TPCn -- Transmit Per-Channel Control */
1847 if (FORMAT_E1CAS && (i==0))
1848 write_framer(sc, Bt8370_TPCn +i, 0x30); /* tidle, sig=0000 (MAS) */
1849 else if (FORMAT_E1CAS && (i==16))
1850 write_framer(sc, Bt8370_TPCn +i, 0x3B); /* tidle, sig=1011 (XYXX) */
1851 else if ((sc->config.time_slots & (1<<i)) == 0)
1852 write_framer(sc, Bt8370_TPCn +i, 0x20); /* tidle: use TSLIP_LOn */
1854 write_framer(sc, Bt8370_TPCn +i, 0x00); /* nothing special */
1856 /* 140-15F:TSLIP_LOn -- Transmit PCM Slip Buffer */
1857 write_framer(sc, Bt8370_TSLIP_LOn +i, 0x7F); /* idle chan data */
1858 /* 180-19F:RPCn -- Receive Per-Channel Control */
1859 write_framer(sc, Bt8370_RPCn +i, 0x00); /* nothing special */
1862 /* Enable transmitter output drivers. */
1863 set_mii16_bits(sc, MII16_T1_XOE);
1867 t1_ident(softc_t *sc)
1869 printf(", Bt837%x rev %x",
1870 read_framer(sc, Bt8370_DID)>>4,
1871 read_framer(sc, Bt8370_DID)&0x0F);
1874 /* Called once a second; must not sleep. */
1876 t1_watchdog(softc_t *sc)
1878 u_int16_t LCV = 0, FERR = 0, CRC = 0, FEBE = 0;
1879 u_int8_t alm1, alm3, loop, isr0;
1880 int link_status = STATUS_UP;
1883 /* Read the alarm registers */
1884 alm1 = read_framer(sc, Bt8370_ALM1);
1885 alm3 = read_framer(sc, Bt8370_ALM3);
1886 loop = read_framer(sc, Bt8370_LOOP);
1887 isr0 = read_framer(sc, Bt8370_ISR0);
1889 /* Always ignore the SIGFRZ alarm bit, */
1890 alm1 &= ~ALM1_SIGFRZ;
1891 if (FORMAT_T1ANY) /* ignore RYEL in T1 modes */
1893 else if (FORMAT_E1NONE) /* ignore all alarms except LOS */
1896 /* Software is alive. */
1897 led_inv(sc, MII16_T1_LED_GRN);
1899 /* Receiving Alarm Indication Signal (AIS). */
1900 if ((alm1 & ALM1_RAIS)!=0) /* receiving ais */
1901 led_on(sc, MII16_T1_LED_BLU);
1902 else if ((alm1 & ALM1_RLOS)!=0) /* sending ais */
1903 led_inv(sc, MII16_T1_LED_BLU);
1905 led_off(sc, MII16_T1_LED_BLU);
1907 /* Receiving Remote Alarm Indication (RAI). */
1908 if ((alm1 & (ALM1_RMYEL | ALM1_RYEL))!=0) /* receiving rai */
1909 led_on(sc, MII16_T1_LED_YEL);
1910 else if ((alm1 & ALM1_RLOF)!=0) /* sending rai */
1911 led_inv(sc, MII16_T1_LED_YEL);
1913 led_off(sc, MII16_T1_LED_YEL);
1915 /* If any alarm bits are set then the link is 'down'. */
1916 /* The bad bits are: rmyel ryel rais ralos rlos rlof. */
1917 /* Some alarm bits have been masked by this point. */
1918 if (alm1 != 0) link_status = STATUS_DOWN;
1920 /* Declare local Red Alarm if the link is down. */
1921 if (link_status == STATUS_DOWN)
1922 led_on(sc, MII16_T1_LED_RED);
1923 else if (sc->loop_timer != 0) /* loopback is active */
1924 led_inv(sc, MII16_T1_LED_RED);
1926 led_off(sc, MII16_T1_LED_RED);
1928 /* Print latched error bits if they changed. */
1929 if ((DRIVER_DEBUG) && (alm1 != sc->last_alm1))
1931 char *on = "ON ", *off = "OFF";
1932 printf("%s: RLOF=%s RLOS=%s RALOS=%s RAIS=%s RYEL=%s RMYEL=%s\n",
1934 (alm1 & ALM1_RLOF) ? on : off,
1935 (alm1 & ALM1_RLOS) ? on : off,
1936 (alm1 & ALM1_RALOS) ? on : off,
1937 (alm1 & ALM1_RAIS) ? on : off,
1938 (alm1 & ALM1_RYEL) ? on : off,
1939 (alm1 & ALM1_RMYEL) ? on : off);
1942 /* Check and print error counters if non-zero. */
1943 LCV = read_framer(sc, Bt8370_LCV_LO) +
1944 (read_framer(sc, Bt8370_LCV_HI)<<8);
1946 FERR = read_framer(sc, Bt8370_FERR_LO) +
1947 (read_framer(sc, Bt8370_FERR_HI)<<8);
1948 if (FORMAT_E1CRC || FORMAT_T1ESF)
1949 CRC = read_framer(sc, Bt8370_CRC_LO) +
1950 (read_framer(sc, Bt8370_CRC_HI)<<8);
1952 FEBE = read_framer(sc, Bt8370_FEBE_LO) +
1953 (read_framer(sc, Bt8370_FEBE_HI)<<8);
1954 /* Only LCV is valid if Out-Of-Frame */
1955 if (FORMAT_E1NONE) FERR = CRC = FEBE = 0;
1956 if ((DRIVER_DEBUG) && (LCV || FERR || CRC || FEBE))
1957 printf("%s: LCV=%u FERR=%u CRC=%u FEBE=%u\n",
1958 NAME_UNIT, LCV, FERR, CRC, FEBE);
1960 /* Driver keeps crude link-level error counters (SNMP is better). */
1961 sc->status.cntrs.lcv_errs += LCV;
1962 sc->status.cntrs.frm_errs += FERR;
1963 sc->status.cntrs.crc_errs += CRC;
1964 sc->status.cntrs.febe_errs += FEBE;
1966 /* Check for BOP messages in the ESF Facility Data Link. */
1967 if ((FORMAT_T1ESF) && (read_framer(sc, Bt8370_ISR1) & 0x80))
1969 u_int8_t bop_code = read_framer(sc, Bt8370_RBOP) & 0x3F;
1975 if ((DRIVER_DEBUG) && ((sc->last_alm1 & ALM1_RMYEL)==0))
1976 printf("%s: Receiving a 'yellow alarm' BOP msg\n", NAME_UNIT);
1982 printf("%s: Received a 'line loopback activate' BOP msg\n", NAME_UNIT);
1983 write_framer(sc, Bt8370_LOOP, LOOP_LINE);
1984 sc->loop_timer = 305;
1987 case T1BOP_LINE_DOWN:
1990 printf("%s: Received a 'line loopback deactivate' BOP msg\n", NAME_UNIT);
1991 write_framer(sc, Bt8370_LOOP,
1992 read_framer(sc, Bt8370_LOOP) & ~LOOP_LINE);
1999 printf("%s: Received a 'payload loopback activate' BOP msg\n", NAME_UNIT);
2000 write_framer(sc, Bt8370_LOOP, LOOP_PAYLOAD);
2001 sc->loop_timer = 305;
2004 case T1BOP_PAY_DOWN:
2007 printf("%s: Received a 'payload loopback deactivate' BOP msg\n", NAME_UNIT);
2008 write_framer(sc, Bt8370_LOOP,
2009 read_framer(sc, Bt8370_LOOP) & ~LOOP_PAYLOAD);
2016 printf("%s: Received a type 0x%02X BOP msg\n", NAME_UNIT, bop_code);
2022 /* Check for HDLC pkts in the ESF Facility Data Link. */
2023 if ((FORMAT_T1ESF) && (read_framer(sc, Bt8370_ISR2) & 0x70))
2025 /* while (not fifo-empty && not start-of-msg) flush fifo */
2026 while ((read_framer(sc, Bt8370_RDL1_STAT) & 0x0C) == 0)
2027 read_framer(sc, Bt8370_RDL1);
2028 /* If (not fifo-empty), then begin processing fifo contents. */
2029 if ((read_framer(sc, Bt8370_RDL1_STAT) & 0x0C) == 0x08)
2032 u_int8_t stat = read_framer(sc, Bt8370_RDL1);
2033 sc->status.cntrs.fdl_pkts++;
2034 for (i=0; i<(stat & 0x3F); i++)
2035 msg[i] = read_framer(sc, Bt8370_RDL1);
2036 /* Is this FDL message a T1.403 performance report? */
2037 if (((stat & 0x3F)==11) &&
2038 ((msg[0]==0x38) || (msg[0]==0x3A)) &&
2039 (msg[1]==1) && (msg[2]==3))
2040 /* Copy 4 PRs from FDL pkt to SNMP struct. */
2041 memcpy(sc->status.snmp.t1.prm, msg+3, 8);
2045 /* Check for inband loop up/down commands. */
2048 u_int8_t isr6 = read_framer(sc, Bt8370_ISR6);
2049 u_int8_t alarm2 = read_framer(sc, Bt8370_ALM2);
2050 u_int8_t tlb = read_framer(sc, Bt8370_TLB);
2052 /* Inband Code == Loop Up && On Transition && Inband Tx Inactive */
2053 if ((isr6 & 0x40) && (alarm2 & 0x40) && ((tlb & 1)==0))
2054 { /* CSU loop up is 10000 10000 ... */
2056 printf("%s: Received a 'CSU Loop Up' inband msg\n", NAME_UNIT);
2057 write_framer(sc, Bt8370_LOOP, LOOP_LINE); /* Loop up */
2058 sc->loop_timer = 305;
2060 /* Inband Code == Loop Down && On Transition && Inband Tx Inactive */
2061 if ((isr6 & 0x80) && (alarm2 & 0x80) && ((tlb & 1)==0))
2062 { /* CSU loop down is 100 100 100 ... */
2064 printf("%s: Received a 'CSU Loop Down' inband msg\n", NAME_UNIT);
2065 write_framer(sc, Bt8370_LOOP,
2066 read_framer(sc, Bt8370_LOOP) & ~LOOP_LINE); /* loop down */
2071 /* Manually send Yellow Alarm BOP msgs. */
2074 u_int8_t isr7 = read_framer(sc, Bt8370_ISR7);
2076 if ((isr7 & 0x02) && (alm1 & 0x02)) /* RLOF on-transition */
2077 { /* Start sending continuous Yellow Alarm BOP messages. */
2078 write_framer(sc, Bt8370_BOP, RBOP_25 | TBOP_CONT);
2079 write_framer(sc, Bt8370_TBOP, 0x00); /* send BOP; order matters */
2081 else if ((isr7 & 0x02) && ((alm1 & 0x02)==0)) /* RLOF off-transition */
2082 { /* Stop sending continuous Yellow Alarm BOP messages. */
2083 write_framer(sc, Bt8370_BOP, RBOP_25 | TBOP_OFF);
2087 /* Time out loopback requests. */
2088 if (sc->loop_timer != 0)
2089 if (--sc->loop_timer == 0)
2093 printf("%s: Timeout: Loop Down after 300 seconds\n", NAME_UNIT);
2094 write_framer(sc, Bt8370_LOOP, loop & ~(LOOP_PAYLOAD | LOOP_LINE));
2097 /* RX Test Pattern status */
2098 if ((DRIVER_DEBUG) && (isr0 & 0x10))
2099 printf("%s: RX Test Pattern Sync\n", NAME_UNIT);
2101 /* SNMP Error Counters */
2102 sc->status.snmp.t1.lcv = LCV;
2103 sc->status.snmp.t1.fe = FERR;
2104 sc->status.snmp.t1.crc = CRC;
2105 sc->status.snmp.t1.febe = FEBE;
2107 /* SNMP Line Status */
2108 sc->status.snmp.t1.line = 0;
2109 if (alm1 & ALM1_RMYEL) sc->status.snmp.t1.line |= TLINE_RX_RAI;
2110 if (alm1 & ALM1_RYEL) sc->status.snmp.t1.line |= TLINE_RX_RAI;
2111 if (alm1 & ALM1_RLOF) sc->status.snmp.t1.line |= TLINE_TX_RAI;
2112 if (alm1 & ALM1_RAIS) sc->status.snmp.t1.line |= TLINE_RX_AIS;
2113 if (alm1 & ALM1_RLOS) sc->status.snmp.t1.line |= TLINE_TX_AIS;
2114 if (alm1 & ALM1_RLOF) sc->status.snmp.t1.line |= TLINE_LOF;
2115 if (alm1 & ALM1_RLOS) sc->status.snmp.t1.line |= TLINE_LOS;
2116 if (alm3 & ALM3_RMAIS) sc->status.snmp.t1.line |= T1LINE_RX_TS16_AIS;
2117 if (alm3 & ALM3_SRED) sc->status.snmp.t1.line |= T1LINE_TX_TS16_LOMF;
2118 if (alm3 & ALM3_SEF) sc->status.snmp.t1.line |= T1LINE_SEF;
2119 if (isr0 & 0x10) sc->status.snmp.t1.line |= T1LINE_RX_TEST;
2120 if ((alm1 & ALM1_RMYEL) && (FORMAT_E1CAS))
2121 sc->status.snmp.t1.line |= T1LINE_RX_TS16_LOMF;
2123 /* SNMP Loopback Status */
2124 sc->status.snmp.t1.loop &= ~(TLOOP_FAR_LINE | TLOOP_FAR_PAYLOAD);
2125 if (sc->config.loop_back == CFG_LOOP_TULIP)
2126 sc->status.snmp.t1.loop |= TLOOP_NEAR_OTHER;
2127 if (loop & LOOP_PAYLOAD) sc->status.snmp.t1.loop |= TLOOP_NEAR_PAYLOAD;
2128 if (loop & LOOP_LINE) sc->status.snmp.t1.loop |= TLOOP_NEAR_LINE;
2129 if (loop & LOOP_ANALOG) sc->status.snmp.t1.loop |= TLOOP_NEAR_OTHER;
2130 if (loop & LOOP_FRAMER) sc->status.snmp.t1.loop |= TLOOP_NEAR_INWARD;
2132 /* Remember this state until next time. */
2133 sc->last_alm1 = alm1;
2135 /* If an INWARD loopback is in effect, link status is UP */
2136 if (sc->config.loop_back != CFG_LOOP_NONE) /* XXX INWARD ONLY */
2137 link_status = STATUS_UP;
2142 /* IOCTL SYSCALL: can sleep. */
2144 t1_send_bop(softc_t *sc, int bop_code)
2149 /* The BOP transmitter could be sending a continuous */
2150 /* BOP msg when told to send this BOP_25 message. */
2151 /* So save and restore the state of the BOP machine. */
2152 bop = read_framer(sc, Bt8370_BOP);
2153 write_framer(sc, Bt8370_BOP, RBOP_OFF | TBOP_OFF);
2154 for (i=0; i<40; i++) /* max delay 400 ms. */
2155 if (read_framer(sc, Bt8370_BOP_STAT) & 0x80) SLEEP(10000);
2156 /* send 25 repetitions of bop_code */
2157 write_framer(sc, Bt8370_BOP, RBOP_OFF | TBOP_25);
2158 write_framer(sc, Bt8370_TBOP, bop_code); /* order matters */
2159 /* wait for tx to stop */
2160 for (i=0; i<40; i++) /* max delay 400 ms. */
2161 if (read_framer(sc, Bt8370_BOP_STAT) & 0x80) SLEEP(10000);
2162 /* Restore previous state of the BOP machine. */
2163 write_framer(sc, Bt8370_BOP, bop);
2166 /* IOCTL SYSCALL: can sleep. */
2168 t1_ioctl(softc_t *sc, struct ioctl *ioctl)
2174 case IOCTL_SNMP_SEND: /* set opstatus? */
2176 switch (ioctl->data)
2180 write_framer(sc, Bt8370_TPATT, 0x00); /* tx pattern generator off */
2181 write_framer(sc, Bt8370_RPATT, 0x00); /* rx pattern detector off */
2182 write_framer(sc, Bt8370_TLB, 0x00); /* tx inband generator off */
2188 t1_send_bop(sc, T1BOP_LINE_UP);
2189 else if (FORMAT_T1SF)
2191 write_framer(sc, Bt8370_LBP, 0x08); /* 10000 10000 ... */
2192 write_framer(sc, Bt8370_TLB, 0x05); /* 5 bits, framed, start */
2194 sc->status.snmp.t1.loop |= TLOOP_FAR_LINE;
2199 t1_send_bop(sc, T1BOP_PAY_UP);
2200 sc->status.snmp.t1.loop |= TLOOP_FAR_PAYLOAD;
2205 if (sc->status.snmp.t1.loop == TLOOP_FAR_LINE)
2208 t1_send_bop(sc, T1BOP_LINE_DOWN);
2209 else if (FORMAT_T1SF)
2211 write_framer(sc, Bt8370_LBP, 0x24); /* 100100 100100 ... */
2212 write_framer(sc, Bt8370_TLB, 0x09); /* 6 bits, framed, start */
2214 sc->status.snmp.t1.loop &= ~TLOOP_FAR_LINE;
2216 if (sc->status.snmp.t1.loop == TLOOP_FAR_PAYLOAD)
2218 t1_send_bop(sc, T1BOP_PAY_DOWN);
2219 sc->status.snmp.t1.loop &= ~TLOOP_FAR_PAYLOAD;
2225 write_framer(sc, Bt8370_TPATT, 0x1E); /* framed QRSS */
2236 case IOCTL_SNMP_LOOP: /* set opstatus = test? */
2238 u_int8_t new_loop = 0;
2240 if (ioctl->data == CFG_LOOP_NONE)
2242 else if (ioctl->data == CFG_LOOP_PAYLOAD)
2243 new_loop = LOOP_PAYLOAD;
2244 else if (ioctl->data == CFG_LOOP_LINE)
2245 new_loop = LOOP_LINE;
2246 else if (ioctl->data == CFG_LOOP_OTHER)
2247 new_loop = LOOP_ANALOG;
2248 else if (ioctl->data == CFG_LOOP_INWARD)
2249 new_loop = LOOP_FRAMER;
2250 else if (ioctl->data == CFG_LOOP_DUAL)
2251 new_loop = LOOP_DUAL;
2256 write_framer(sc, Bt8370_LOOP, new_loop);
2257 sc->config.loop_back = ioctl->data;
2270 struct card hssi_card =
2272 .config = hssi_config,
2273 .ident = hssi_ident,
2274 .watchdog = hssi_watchdog,
2275 .ioctl = hssi_ioctl,
2279 struct card t3_card =
2281 .config = t3_config,
2283 .watchdog = t3_watchdog,
2288 struct card ssi_card =
2290 .config = ssi_config,
2292 .watchdog = ssi_watchdog,
2297 struct card t1_card =
2299 .config = t1_config,
2301 .watchdog = t1_watchdog,
2305 /* RAWIP is raw IP packets (v4 or v6) in HDLC frames with NO HEADERS. */
2306 /* No HDLC Address/Control fields! No line control protocol at all! */
2308 /* rxintr_cleanup calls this to give a newly arrived pkt to higher levels. */
2310 lmc_raw_input(struct ifnet *ifp, struct mbuf *mbuf)
2312 softc_t *sc = IFP2SC(ifp);
2314 M_SETFIB(mbuf, ifp->if_fib);
2316 if (mbuf->m_data[0]>>4 == 4)
2317 netisr_dispatch(NETISR_IP, mbuf);
2321 if (mbuf->m_data[0]>>4 == 6)
2322 netisr_dispatch(NETISR_IPV6, mbuf);
2327 sc->status.cntrs.idiscards++;
2329 printf("%s: lmc_raw_input: rx pkt discarded: not IPv4 or IPv6\n",
2335 * We are "standing on the head of a pin" in these routines.
2336 * Tulip CSRs can be accessed, but nothing else is interrupt-safe!
2337 * Do NOT access: MII, GPIO, SROM, BIOSROM, XILINX, SYNTH, or DAC.
2341 /* Singly-linked tail-queues hold mbufs with active DMA.
2342 * For RX, single mbuf clusters; for TX, mbuf chains are queued.
2343 * NB: mbufs are linked through their m_nextpkt field.
2344 * Callers must hold sc->bottom_lock; not otherwise locked.
2347 /* Put an mbuf (chain) on the tail of the descriptor ring queue. */
2348 static void /* BSD version */
2349 mbuf_enqueue(struct desc_ring *ring, struct mbuf *m)
2351 m->m_nextpkt = NULL;
2352 if (ring->tail == NULL)
2355 ring->tail->m_nextpkt = m;
2359 /* Get an mbuf (chain) from the head of the descriptor ring queue. */
2360 static struct mbuf* /* BSD version */
2361 mbuf_dequeue(struct desc_ring *ring)
2363 struct mbuf *m = ring->head;
2365 if ((ring->head = m->m_nextpkt) == NULL)
2370 static void /* *** FreeBSD ONLY *** Callout from bus_dmamap_load() */
2371 fbsd_dmamap_load(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2373 struct desc_ring *ring = arg;
2374 ring->nsegs = error ? 0 : nsegs;
2375 ring->segs[0] = segs[0];
2376 ring->segs[1] = segs[1];
2379 /* Initialize a DMA descriptor ring. */
2380 static int /* BSD version */
2381 create_ring(softc_t *sc, struct desc_ring *ring, int num_descs)
2383 struct dma_desc *descs;
2384 int size_descs = sizeof(struct dma_desc)*num_descs;
2387 /* The DMA descriptor array must not cross a page boundary. */
2388 if (size_descs > PAGE_SIZE)
2390 printf("%s: DMA descriptor array > PAGE_SIZE (%d)\n", NAME_UNIT,
2396 /* Create a DMA tag for descriptors and buffers. */
2397 if ((error = bus_dma_tag_create(bus_get_dma_tag(sc->dev),
2398 4, 0, BUS_SPACE_MAXADDR_32BIT,
2399 BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE, 2, PAGE_SIZE, BUS_DMA_ALLOCNOW,
2403 printf("%s: bus_dma_tag_create() failed: error %d\n", NAME_UNIT, error);
2407 /* Allocate wired physical memory for DMA descriptor array */
2408 /* and map physical address to kernel virtual address. */
2409 if ((error = bus_dmamem_alloc(ring->tag, (void**)&ring->first,
2410 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->map)))
2412 printf("%s: bus_dmamem_alloc() failed; error %d\n", NAME_UNIT, error);
2415 descs = ring->first;
2417 /* Map kernel virtual address to PCI address for DMA descriptor array. */
2418 if ((error = bus_dmamap_load(ring->tag, ring->map, descs, size_descs,
2419 fbsd_dmamap_load, ring, 0)))
2421 printf("%s: bus_dmamap_load() failed; error %d\n", NAME_UNIT, error);
2424 ring->dma_addr = ring->segs[0].ds_addr;
2426 /* Allocate dmamaps for each DMA descriptor. */
2427 for (i=0; i<num_descs; i++)
2428 if ((error = bus_dmamap_create(ring->tag, 0, &descs[i].map)))
2430 printf("%s: bus_dmamap_create() failed; error %d\n", NAME_UNIT, error);
2436 ring->write = descs;
2437 ring->first = descs;
2438 ring->last = descs + num_descs -1;
2439 ring->last->control = TLP_DCTL_END_RING;
2440 ring->num_descs = num_descs;
2441 ring->size_descs = size_descs;
2448 /* Destroy a DMA descriptor ring */
2449 static void /* BSD version */
2450 destroy_ring(softc_t *sc, struct desc_ring *ring)
2452 struct dma_desc *desc;
2455 /* Free queued mbufs. */
2456 while ((m = mbuf_dequeue(ring)) != NULL)
2459 /* TX may have one pkt that is not on any queue. */
2460 if (sc->tx_mbuf != NULL)
2462 m_freem(sc->tx_mbuf);
2466 /* Unmap active DMA descriptors. */
2467 while (ring->read != ring->write)
2469 bus_dmamap_unload(ring->tag, ring->read->map);
2470 if (ring->read++ == ring->last) ring->read = ring->first;
2474 /* Free the dmamaps of all DMA descriptors. */
2475 for (desc=ring->first; desc!=ring->last+1; desc++)
2476 if (desc->map != NULL)
2477 bus_dmamap_destroy(ring->tag, desc->map);
2479 /* Unmap PCI address for DMA descriptor array. */
2480 if (ring->dma_addr != 0)
2481 bus_dmamap_unload(ring->tag, ring->map);
2482 /* Free kernel memory for DMA descriptor array. */
2483 if (ring->first != NULL)
2484 bus_dmamem_free(ring->tag, ring->first, ring->map);
2485 /* Free the DMA tag created for this ring. */
2486 if (ring->tag != NULL)
2487 bus_dma_tag_destroy(ring->tag);
2491 /* Clean up after a packet has been received. */
2492 static int /* BSD version */
2493 rxintr_cleanup(softc_t *sc)
2495 struct desc_ring *ring = &sc->rxring;
2496 struct dma_desc *first_desc, *last_desc;
2497 struct mbuf *first_mbuf=NULL, *last_mbuf=NULL;
2498 struct mbuf *new_mbuf;
2499 int pkt_len, desc_len;
2501 #if defined(DEVICE_POLLING)
2502 /* Input packet flow control (livelock prevention): */
2503 /* Give pkts to higher levels only if quota is > 0. */
2504 if (sc->quota <= 0) return 0;
2507 /* This looks complicated, but remember: typically packets up */
2508 /* to 2048 bytes long fit in one mbuf and use one descriptor. */
2510 first_desc = last_desc = ring->read;
2512 /* ASSERTION: If there is a descriptor in the ring and the hardware has */
2513 /* finished with it, then that descriptor will have RX_FIRST_DESC set. */
2514 if ((ring->read != ring->write) && /* descriptor ring not empty */
2515 ((ring->read->status & TLP_DSTS_OWNER) == 0) && /* hardware done */
2516 ((ring->read->status & TLP_DSTS_RX_FIRST_DESC) == 0)) /* should be set */
2517 panic("%s: rxintr_cleanup: rx-first-descriptor not set.\n", NAME_UNIT);
2519 /* First decide if a complete packet has arrived. */
2520 /* Run down DMA descriptors looking for one marked "last". */
2521 /* Bail out if an active descriptor is encountered. */
2522 /* Accumulate most significant bits of packet length. */
2526 if (last_desc == ring->write) return 0; /* no more descs */
2527 if (last_desc->status & TLP_DSTS_OWNER) return 0; /* still active */
2528 if (last_desc->status & TLP_DSTS_RX_LAST_DESC) break; /* end of packet */
2529 pkt_len += last_desc->length1 + last_desc->length2; /* entire desc filled */
2530 if (last_desc++->control & TLP_DCTL_END_RING) last_desc = ring->first; /* ring wrap */
2533 /* A complete packet has arrived; how long is it? */
2534 /* H/w ref man shows RX pkt length as a 14-bit field. */
2535 /* An experiment found that only the 12 LSBs work. */
2536 if (((last_desc->status>>16)&0xFFF) == 0) pkt_len += 4096; /* carry-bit */
2537 pkt_len = (pkt_len & 0xF000) + ((last_desc->status>>16) & 0x0FFF);
2538 /* Subtract the CRC length unless doing so would underflow. */
2539 if (pkt_len >= sc->config.crc_len) pkt_len -= sc->config.crc_len;
2541 /* Run down DMA descriptors again doing the following:
2542 * 1) put pkt info in pkthdr of first mbuf,
2544 * 3) set mbuf lengths.
2546 first_desc = ring->read;
2549 /* Read a DMA descriptor from the ring. */
2550 last_desc = ring->read;
2551 /* Advance the ring read pointer. */
2552 if (ring->read++ == ring->last) ring->read = ring->first;
2554 /* Dequeue the corresponding cluster mbuf. */
2555 new_mbuf = mbuf_dequeue(ring);
2556 if (new_mbuf == NULL)
2557 panic("%s: rxintr_cleanup: expected an mbuf\n", NAME_UNIT);
2559 desc_len = last_desc->length1 + last_desc->length2;
2560 /* If bouncing, copy bounce buf to mbuf. */
2561 DMA_SYNC(last_desc->map, desc_len, BUS_DMASYNC_POSTREAD);
2562 /* Unmap kernel virtual address to PCI address. */
2563 bus_dmamap_unload(ring->tag, last_desc->map);
2565 /* 1) Put pkt info in pkthdr of first mbuf. */
2566 if (last_desc == first_desc)
2568 first_mbuf = new_mbuf;
2569 first_mbuf->m_pkthdr.len = pkt_len; /* total pkt length */
2570 first_mbuf->m_pkthdr.rcvif = sc->ifp; /* how it got here */
2572 else /* 2) link mbufs. */
2574 last_mbuf->m_next = new_mbuf;
2575 /* M_PKTHDR should be set in the first mbuf only. */
2576 new_mbuf->m_flags &= ~M_PKTHDR;
2578 last_mbuf = new_mbuf;
2580 /* 3) Set mbuf lengths. */
2581 new_mbuf->m_len = (pkt_len >= desc_len) ? desc_len : pkt_len;
2582 pkt_len -= new_mbuf->m_len;
2583 } while ((last_desc->status & TLP_DSTS_RX_LAST_DESC) == 0);
2585 /* Decide whether to accept or to discard this packet. */
2586 /* RxHDLC sets MIIERR for bad CRC, abort and partial byte at pkt end. */
2587 if (((last_desc->status & TLP_DSTS_RX_BAD) == 0) &&
2588 (sc->status.oper_status == STATUS_UP) &&
2589 (first_mbuf->m_pkthdr.len > 0))
2591 /* Optimization: copy a small pkt into a small mbuf. */
2592 if (first_mbuf->m_pkthdr.len <= COPY_BREAK)
2594 MGETHDR(new_mbuf, M_NOWAIT, MT_DATA);
2595 if (new_mbuf != NULL)
2597 new_mbuf->m_pkthdr.rcvif = first_mbuf->m_pkthdr.rcvif;
2598 new_mbuf->m_pkthdr.len = first_mbuf->m_pkthdr.len;
2599 new_mbuf->m_len = first_mbuf->m_len;
2600 memcpy(new_mbuf->m_data, first_mbuf->m_data,
2601 first_mbuf->m_pkthdr.len);
2602 m_freem(first_mbuf);
2603 first_mbuf = new_mbuf;
2606 /* Include CRC and one flag byte in input byte count. */
2607 sc->status.cntrs.ibytes += first_mbuf->m_pkthdr.len + sc->config.crc_len +1;
2608 sc->status.cntrs.ipackets++;
2609 if_inc_counter(sc->ifp, IFCOUNTER_IPACKETS, 1);
2610 LMC_BPF_MTAP(first_mbuf);
2611 #if defined(DEVICE_POLLING)
2615 /* Give this good packet to the network stacks. */
2617 if (sc->ng_hook != NULL) /* is hook connected? */
2619 int error; /* ignore error */
2620 NG_SEND_DATA_ONLY(error, sc->ng_hook, first_mbuf);
2621 return 1; /* did something */
2623 #endif /* NETGRAPH */
2624 if (sc->config.line_pkg == PKG_RAWIP)
2625 lmc_raw_input(sc->ifp, first_mbuf);
2629 sppp_input(sc->ifp, first_mbuf);
2631 new_mbuf = first_mbuf;
2632 while (new_mbuf != NULL)
2634 sc->p2p->p2p_hdrinput(sc->p2p, new_mbuf->m_data, new_mbuf->m_len);
2635 new_mbuf = new_mbuf->m_next;
2637 sc->p2p->p2p_input(sc->p2p, NULL);
2638 m_freem(first_mbuf);
2640 m_freem(first_mbuf);
2641 sc->status.cntrs.idiscards++;
2645 else if (sc->status.oper_status != STATUS_UP)
2647 /* If the link is down, this packet is probably noise. */
2648 m_freem(first_mbuf);
2649 sc->status.cntrs.idiscards++;
2651 printf("%s: rxintr_cleanup: rx pkt discarded: link down\n", NAME_UNIT);
2653 else /* Log and discard this bad packet. */
2656 printf("%s: RX bad pkt; len=%d %s%s%s%s\n",
2657 NAME_UNIT, first_mbuf->m_pkthdr.len,
2658 (last_desc->status & TLP_DSTS_RX_MII_ERR) ? " miierr" : "",
2659 (last_desc->status & TLP_DSTS_RX_DRIBBLE) ? " dribble" : "",
2660 (last_desc->status & TLP_DSTS_RX_DESC_ERR) ? " descerr" : "",
2661 (last_desc->status & TLP_DSTS_RX_OVERRUN) ? " overrun" : "");
2662 if (last_desc->status & TLP_DSTS_RX_OVERRUN)
2663 sc->status.cntrs.fifo_over++;
2665 sc->status.cntrs.ierrors++;
2666 m_freem(first_mbuf);
2669 return 1; /* did something */
2672 /* Setup (prepare) to receive a packet. */
2673 /* Try to keep the RX descriptor ring full of empty buffers. */
2674 static int /* BSD version */
2675 rxintr_setup(softc_t *sc)
2677 struct desc_ring *ring = &sc->rxring;
2678 struct dma_desc *desc;
2683 /* Ring is full if (wrap(write+1)==read) */
2684 if (((ring->write == ring->last) ? ring->first : ring->write+1) == ring->read)
2685 return 0; /* ring is full; nothing to do */
2687 /* Allocate a small mbuf and attach an mbuf cluster. */
2688 MGETHDR(m, M_NOWAIT, MT_DATA);
2691 sc->status.cntrs.rxdma++;
2693 printf("%s: rxintr_setup: MGETHDR() failed\n", NAME_UNIT);
2696 if (!(MCLGET(m, M_NOWAIT)))
2699 sc->status.cntrs.rxdma++;
2701 printf("%s: rxintr_setup: MCLGET() failed\n", NAME_UNIT);
2705 /* Queue the mbuf for later processing by rxintr_cleanup. */
2706 mbuf_enqueue(ring, m);
2708 /* Write a DMA descriptor into the ring. */
2709 /* Hardware won't see it until the OWNER bit is set. */
2711 /* Advance the ring write pointer. */
2712 if (ring->write++ == ring->last) ring->write = ring->first;
2714 desc_len = (MCLBYTES < MAX_DESC_LEN) ? MCLBYTES : MAX_DESC_LEN;
2715 /* Map kernel virtual address to PCI address. */
2716 if ((error = DMA_LOAD(desc->map, m->m_data, desc_len)))
2717 printf("%s: bus_dmamap_load(rx) failed; error %d\n", NAME_UNIT, error);
2718 /* Invalidate the cache for this mbuf. */
2719 DMA_SYNC(desc->map, desc_len, BUS_DMASYNC_PREREAD);
2721 /* Set up the DMA descriptor. */
2722 desc->address1 = ring->segs[0].ds_addr;
2723 desc->length1 = desc_len>>1;
2724 desc->address2 = desc->address1 + desc->length1;
2725 desc->length2 = desc_len>>1;
2727 /* Before setting the OWNER bit, flush the cache (memory barrier). */
2728 DMA_SYNC(ring->map, ring->size_descs, BUS_DMASYNC_PREWRITE);
2730 /* Commit the DMA descriptor to the hardware. */
2731 desc->status = TLP_DSTS_OWNER;
2733 /* Notify the receiver that there is another buffer available. */
2734 WRITE_CSR(TLP_RX_POLL, 1);
2736 return 1; /* did something */
2739 /* Clean up after a packet has been transmitted. */
2740 /* Free the mbuf chain and update the DMA descriptor ring. */
2741 static int /* BSD version */
2742 txintr_cleanup(softc_t *sc)
2744 struct desc_ring *ring = &sc->txring;
2745 struct dma_desc *desc;
2747 while ((ring->read != ring->write) && /* while ring is not empty */
2748 ((ring->read->status & TLP_DSTS_OWNER) == 0))
2750 /* Read a DMA descriptor from the ring. */
2752 /* Advance the ring read pointer. */
2753 if (ring->read++ == ring->last) ring->read = ring->first;
2755 /* This is a no-op on most architectures. */
2756 DMA_SYNC(desc->map, desc->length1 + desc->length2, BUS_DMASYNC_POSTWRITE);
2757 /* Unmap kernel virtual address to PCI address. */
2758 bus_dmamap_unload(ring->tag, desc->map);
2760 /* If this descriptor is the last segment of a packet, */
2761 /* then dequeue and free the corresponding mbuf chain. */
2762 if ((desc->control & TLP_DCTL_TX_LAST_SEG) != 0)
2765 if ((m = mbuf_dequeue(ring)) == NULL)
2766 panic("%s: txintr_cleanup: expected an mbuf\n", NAME_UNIT);
2768 /* Include CRC and one flag byte in output byte count. */
2769 sc->status.cntrs.obytes += m->m_pkthdr.len + sc->config.crc_len +1;
2770 sc->status.cntrs.opackets++;
2771 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, 1);
2773 /* The only bad TX status is fifo underrun. */
2774 if ((desc->status & TLP_DSTS_TX_UNDERRUN) != 0)
2775 sc->status.cntrs.fifo_under++;
2778 return 1; /* did something */
2785 /* Build DMA descriptors for a transmit packet mbuf chain. */
2786 static int /* 0=success; 1=error */ /* BSD version */
2787 txintr_setup_mbuf(softc_t *sc, struct mbuf *m)
2789 struct desc_ring *ring = &sc->txring;
2790 struct dma_desc *desc;
2791 unsigned int desc_len;
2793 /* build DMA descriptors for a chain of mbufs. */
2796 char *data = m->m_data;
2797 int length = m->m_len; /* zero length mbufs happen! */
2799 /* Build DMA descriptors for one mbuf. */
2804 /* Ring is full if (wrap(write+1)==read) */
2805 if (((ring->temp==ring->last) ? ring->first : ring->temp+1) == ring->read)
2806 { /* Not enough DMA descriptors; try later. */
2807 for (; ring->temp!=ring->write;
2808 ring->temp = (ring->temp==ring->first)? ring->last : ring->temp-1)
2809 bus_dmamap_unload(ring->tag, ring->temp->map);
2810 sc->status.cntrs.txdma++;
2814 /* Provisionally, write a descriptor into the ring. */
2815 /* But don't change the REAL ring write pointer. */
2816 /* Hardware won't see it until the OWNER bit is set. */
2818 /* Advance the temporary ring write pointer. */
2819 if (ring->temp++ == ring->last) ring->temp = ring->first;
2821 /* Clear all control bits except the END_RING bit. */
2822 desc->control &= TLP_DCTL_END_RING;
2823 /* Don't pad short packets up to 64 bytes. */
2824 desc->control |= TLP_DCTL_TX_NO_PAD;
2825 /* Use Tulip's CRC-32 generator, if appropriate. */
2826 if (sc->config.crc_len != CFG_CRC_32)
2827 desc->control |= TLP_DCTL_TX_NO_CRC;
2828 /* Set the OWNER bit, except in the first descriptor. */
2829 if (desc != ring->write)
2830 desc->status = TLP_DSTS_OWNER;
2832 desc_len = (length > MAX_CHUNK_LEN) ? MAX_CHUNK_LEN : length;
2833 /* Map kernel virtual address to PCI address. */
2834 if ((error = DMA_LOAD(desc->map, data, desc_len)))
2835 printf("%s: bus_dmamap_load(tx) failed; error %d\n", NAME_UNIT, error);
2836 /* Flush the cache and if bouncing, copy mbuf to bounce buf. */
2837 DMA_SYNC(desc->map, desc_len, BUS_DMASYNC_PREWRITE);
2839 /* Prevent wild fetches if mapping fails (nsegs==0). */
2840 desc->length1 = desc->length2 = 0;
2841 desc->address1 = desc->address2 = 0;
2843 bus_dma_segment_t *segs = ring->segs;
2844 int nsegs = ring->nsegs;
2847 desc->address1 = segs[0].ds_addr;
2848 desc->length1 = segs[0].ds_len;
2852 desc->address2 = segs[1].ds_addr;
2853 desc->length2 = segs[1].ds_len;
2859 } /* while (length > 0) */
2862 } /* while (m != NULL) */
2864 return 0; /* success */
2867 /* Setup (prepare) to transmit a packet. */
2868 /* Select a packet, build DMA descriptors and give packet to hardware. */
2869 /* If DMA descriptors run out, abandon the attempt and return 0. */
2870 static int /* BSD version */
2871 txintr_setup(softc_t *sc)
2873 struct desc_ring *ring = &sc->txring;
2874 struct dma_desc *first_desc, *last_desc;
2876 /* Protect against half-up links: Don't transmit */
2877 /* if the receiver can't hear the far end. */
2878 if (sc->status.oper_status != STATUS_UP) return 0;
2880 /* Pick a packet to transmit. */
2882 if ((sc->ng_hook != NULL) && (sc->tx_mbuf == NULL))
2884 if (!IFQ_IS_EMPTY(&sc->ng_fastq))
2885 IFQ_DEQUEUE(&sc->ng_fastq, sc->tx_mbuf);
2887 IFQ_DEQUEUE(&sc->ng_sndq, sc->tx_mbuf);
2891 if (sc->tx_mbuf == NULL)
2893 if (sc->config.line_pkg == PKG_RAWIP)
2894 IFQ_DEQUEUE(&sc->ifp->if_snd, sc->tx_mbuf);
2898 sc->tx_mbuf = sppp_dequeue(sc->ifp);
2900 if (!IFQ_IS_EMPTY(&sc->p2p->p2p_isnd))
2901 IFQ_DEQUEUE(&sc->p2p->p2p_isnd, sc->tx_mbuf);
2903 IFQ_DEQUEUE(&sc->ifp->if_snd, sc->tx_mbuf);
2907 if (sc->tx_mbuf == NULL) return 0; /* no pkt to transmit */
2909 /* Build DMA descriptors for an outgoing mbuf chain. */
2910 ring->temp = ring->write; /* temporary ring write pointer */
2911 if (txintr_setup_mbuf(sc, sc->tx_mbuf) != 0) return 0;
2913 /* Enqueue the mbuf; txintr_cleanup will free it. */
2914 mbuf_enqueue(ring, sc->tx_mbuf);
2916 /* The transmitter has room for another packet. */
2919 /* Set first & last segment bits. */
2920 /* last_desc is the desc BEFORE the one pointed to by ring->temp. */
2921 first_desc = ring->write;
2922 first_desc->control |= TLP_DCTL_TX_FIRST_SEG;
2923 last_desc = (ring->temp==ring->first)? ring->last : ring->temp-1;
2924 last_desc->control |= TLP_DCTL_TX_LAST_SEG;
2925 /* Interrupt at end-of-transmission? Why bother the poor computer! */
2926 /* last_desc->control |= TLP_DCTL_TX_INTERRUPT; */
2928 /* Make sure the OWNER bit is not set in the next descriptor. */
2929 /* The OWNER bit may have been set if a previous call aborted. */
2930 ring->temp->status = 0;
2932 /* Commit the DMA descriptors to the software. */
2933 ring->write = ring->temp;
2935 /* Before setting the OWNER bit, flush the cache (memory barrier). */
2936 DMA_SYNC(ring->map, ring->size_descs, BUS_DMASYNC_PREWRITE);
2938 /* Commit the DMA descriptors to the hardware. */
2939 first_desc->status = TLP_DSTS_OWNER;
2941 /* Notify the transmitter that there is another packet to send. */
2942 WRITE_CSR(TLP_TX_POLL, 1);
2944 return 1; /* did something */
2950 check_intr_status(softc_t *sc)
2952 u_int32_t status, cfcs, op_mode;
2953 u_int32_t missed, overruns;
2955 /* Check for four unusual events:
2956 * 1) fatal PCI bus errors - some are recoverable
2957 * 2) transmitter FIFO underruns - increase fifo threshold
2958 * 3) receiver FIFO overruns - clear potential hangup
2959 * 4) no receive descs or bufs - count missed packets
2962 /* 1) A fatal bus error causes a Tulip to stop initiating bus cycles. */
2963 /* Module unload/load or boot are the only fixes for Parity Errors. */
2964 /* Master and Target Aborts can be cleared and life may continue. */
2965 status = READ_CSR(TLP_STATUS);
2966 if ((status & TLP_STAT_FATAL_ERROR) != 0)
2968 u_int32_t fatal = (status & TLP_STAT_FATAL_BITS)>>TLP_STAT_FATAL_SHIFT;
2969 printf("%s: FATAL PCI BUS ERROR: %s%s%s%s\n", NAME_UNIT,
2970 (fatal == 0) ? "PARITY ERROR" : "",
2971 (fatal == 1) ? "MASTER ABORT" : "",
2972 (fatal == 2) ? "TARGET ABORT" : "",
2973 (fatal >= 3) ? "RESERVED (?)" : "");
2974 cfcs = READ_PCI_CFG(sc, TLP_CFCS); /* try to clear it */
2975 cfcs &= ~(TLP_CFCS_MSTR_ABORT | TLP_CFCS_TARG_ABORT);
2976 WRITE_PCI_CFG(sc, TLP_CFCS, cfcs);
2979 /* 2) If the transmitter fifo underruns, increase the transmit fifo */
2980 /* threshold: the number of bytes required to be in the fifo */
2981 /* before starting the transmitter (cost: increased tx delay). */
2982 /* The TX_FSM must be stopped to change this parameter. */
2983 if ((status & TLP_STAT_TX_UNDERRUN) != 0)
2985 op_mode = READ_CSR(TLP_OP_MODE);
2986 /* enable store-and-forward mode if tx_threshold tops out? */
2987 if ((op_mode & TLP_OP_TX_THRESH) < TLP_OP_TX_THRESH)
2989 op_mode += 0x4000; /* increment TX_THRESH field; can't overflow */
2990 WRITE_CSR(TLP_OP_MODE, op_mode & ~TLP_OP_TX_RUN);
2991 /* Wait for the TX FSM to stop; it might be processing a pkt. */
2992 while (READ_CSR(TLP_STATUS) & TLP_STAT_TX_FSM); /* XXX HANG */
2993 WRITE_CSR(TLP_OP_MODE, op_mode); /* restart tx */
2995 printf("%s: tx underrun; tx fifo threshold now %d bytes\n",
2996 NAME_UNIT, 128<<((op_mode>>TLP_OP_TR_SHIFT)&3));
3000 /* 3) Errata memo from Digital Equipment Corp warns that 21140A */
3001 /* receivers through rev 2.2 can hang if the fifo overruns. */
3002 /* Recommended fix: stop and start the RX FSM after an overrun. */
3003 missed = READ_CSR(TLP_MISSED);
3004 if ((overruns = ((missed & TLP_MISS_OVERRUN)>>TLP_OVERRUN_SHIFT)) != 0)
3007 printf("%s: rx overrun cntr=%d\n", NAME_UNIT, overruns);
3008 sc->status.cntrs.overruns += overruns;
3009 if ((READ_PCI_CFG(sc, TLP_CFRV) & 0xFF) <= 0x22)
3011 op_mode = READ_CSR(TLP_OP_MODE);
3012 WRITE_CSR(TLP_OP_MODE, op_mode & ~TLP_OP_RX_RUN);
3013 /* Wait for the RX FSM to stop; it might be processing a pkt. */
3014 while (READ_CSR(TLP_STATUS) & TLP_STAT_RX_FSM); /* XXX HANG */
3015 WRITE_CSR(TLP_OP_MODE, op_mode); /* restart rx */
3019 /* 4) When the receiver is enabled and a packet arrives, but no DMA */
3020 /* descriptor is available, the packet is counted as 'missed'. */
3021 /* The receiver should never miss packets; warn if it happens. */
3022 if ((missed = (missed & TLP_MISS_MISSED)) != 0)
3025 printf("%s: rx missed %d pkts\n", NAME_UNIT, missed);
3026 sc->status.cntrs.missed += missed;
3030 static void /* This is where the work gets done. */
3031 core_interrupt(void *arg, int check_status)
3036 /* If any CPU is inside this critical section, then */
3037 /* other CPUs should go away without doing anything. */
3038 if (BOTTOM_TRYLOCK == 0)
3040 sc->status.cntrs.lck_intr++;
3044 /* Clear pending card interrupts. */
3045 WRITE_CSR(TLP_STATUS, READ_CSR(TLP_STATUS));
3047 /* In Linux, pci_alloc_consistent() means DMA descriptors */
3048 /* don't need explicit syncing. */
3050 struct desc_ring *ring = &sc->txring;
3051 DMA_SYNC(sc->txring.map, sc->txring.size_descs,
3052 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3054 DMA_SYNC(sc->rxring.map, sc->rxring.size_descs,
3055 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3058 do /* This is the main loop for interrupt processing. */
3060 activity = txintr_cleanup(sc);
3061 activity += txintr_setup(sc);
3062 activity += rxintr_cleanup(sc);
3063 activity += rxintr_setup(sc);
3067 struct desc_ring *ring = &sc->txring;
3068 DMA_SYNC(sc->txring.map, sc->txring.size_descs,
3069 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3071 DMA_SYNC(sc->rxring.map, sc->rxring.size_descs,
3072 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3075 /* As the interrupt is dismissed, check for four unusual events. */
3076 if (check_status) check_intr_status(sc);
3081 /* user_interrupt() may be called from a syscall or a softirq */
3083 user_interrupt(softc_t *sc, int check_status)
3085 DISABLE_INTR; /* noop on FreeBSD-5 and Linux */
3086 core_interrupt(sc, check_status);
3087 ENABLE_INTR; /* noop on FreeBSD-5 and Linux */
3091 # if defined(DEVICE_POLLING)
3093 /* Service the card from the kernel idle loop without interrupts. */
3095 fbsd_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3097 softc_t *sc = IFP2SC(ifp);
3101 core_interrupt(sc, (cmd==POLL_AND_CHECK_STATUS));
3105 # endif /* DEVICE_POLLING */
3107 /* BSD kernels call this procedure when an interrupt happens. */
3108 static intr_return_t
3109 bsd_interrupt(void *arg)
3113 /* Cut losses early if this is not our interrupt. */
3114 if ((READ_CSR(TLP_STATUS) & TLP_INT_TXRX) == 0)
3117 # if defined(DEVICE_POLLING)
3118 if (sc->ifp->if_capenable & IFCAP_POLLING)
3121 if ((sc->ifp->if_capabilities & IFCAP_POLLING) &&
3122 (ether_poll_register(fbsd_poll, sc->ifp)))
3124 WRITE_CSR(TLP_INT_ENBL, TLP_INT_DISABLE);
3128 sc->quota = sc->rxring.num_descs; /* input flow control */
3129 # endif /* DEVICE_POLLING */
3131 /* Disable card interrupts. */
3132 WRITE_CSR(TLP_INT_ENBL, TLP_INT_DISABLE);
3134 core_interrupt(sc, 0);
3136 /* Enable card interrupts. */
3137 WRITE_CSR(TLP_INT_ENBL, TLP_INT_TXRX);
3143 /* Administrative status of the driver (UP or DOWN) has changed. */
3144 /* A card-specific action may be required: T1 and T3 cards: no-op. */
3145 /* HSSI and SSI cards change the state of modem ready signals. */
3147 set_status(softc_t *sc, int status)
3151 ioctl.cmd = IOCTL_SET_STATUS;
3152 ioctl.data = status;
3154 sc->card->ioctl(sc, &ioctl);
3159 /* Callout from P2P: */
3160 /* Get the state of DCD (Data Carrier Detect). */
3162 p2p_getmdm(struct p2pcom *p2p, caddr_t result)
3164 softc_t *sc = IFP2SC(&p2p->p2p_if);
3166 /* Non-zero isn't good enough; TIOCM_CAR is 0x40. */
3167 *(int *)result = (sc->status.oper_status==STATUS_UP) ? TIOCM_CAR : 0;
3172 /* Callout from P2P: */
3173 /* Set the state of DTR (Data Terminal Ready). */
3175 p2p_mdmctl(struct p2pcom *p2p, int flag)
3177 softc_t *sc = IFP2SC(&p2p->p2p_if);
3179 set_status(sc, flag);
3192 /* Callout from SPPP: */
3194 sppp_tls(struct sppp *sppp)
3196 if (!(sppp->pp_mode & IFF_LINK2) &&
3197 !(sppp->pp_flags & PP_FR))
3201 /* Callout from SPPP: */
3203 sppp_tlf(struct sppp *sppp)
3205 if (!(sppp->pp_mode & IFF_LINK2) &&
3206 !(sppp->pp_flags & PP_FR))
3207 sppp->pp_down(sppp);
3212 /* Configure line protocol stuff.
3213 * Called by attach_card() during module init.
3214 * Called by core_ioctl() when lmcconfig writes sc->config.
3215 * Called by detach_card() during module shutdown.
3218 config_proto(softc_t *sc, struct config *config)
3220 /* Use line protocol stack instead of RAWIP mode. */
3221 if ((sc->config.line_pkg == PKG_RAWIP) &&
3222 (config->line_pkg != PKG_RAWIP))
3226 sppp_attach(sc->ifp);
3227 LMC_BPF_ATTACH(DLT_PPP, 4);
3228 sc->sppp->pp_tls = sppp_tls;
3229 sc->sppp->pp_tlf = sppp_tlf;
3230 /* Force reconfiguration of SPPP params. */
3231 sc->config.line_prot = 0;
3232 sc->config.keep_alive = config->keep_alive ? 0:1;
3235 sc->p2p->p2p_proto = 0; /* force p2p_attach */
3236 if ((error = p2p_attach(sc->p2p))) /* calls bpfattach() */
3238 printf("%s: p2p_attach() failed; error %d\n", NAME_UNIT, error);
3239 config->line_pkg = PKG_RAWIP; /* still in RAWIP mode */
3243 sc->p2p->p2p_mdmctl = p2p_mdmctl; /* set DTR */
3244 sc->p2p->p2p_getmdm = p2p_getmdm; /* get DCD */
3248 sc->net_dev->mtu = HDLC_MAX_MTU;
3249 if ((error = hdlc_open(sc->net_dev)))
3251 printf("%s: hdlc_open() failed; error %d\n", NAME_UNIT, error);
3252 printf("%s: Try 'sethdlc %s ppp'\n", NAME_UNIT, NAME_UNIT);
3253 config->line_pkg = PKG_RAWIP; /* still in RAWIP mode */
3255 #else /* no line protocol stack was configured */
3256 config->line_pkg = PKG_RAWIP; /* still in RAWIP mode */
3260 /* Bypass line protocol stack and return to RAWIP mode. */
3261 if ((sc->config.line_pkg != PKG_RAWIP) &&
3262 (config->line_pkg == PKG_RAWIP))
3266 sppp_flush(sc->ifp);
3267 sppp_detach(sc->ifp);
3268 setup_ifnet(sc->ifp);
3269 LMC_BPF_ATTACH(DLT_RAW, 0);
3272 if_qflush(&sc->p2p->p2p_isnd);
3273 if ((error = p2p_detach(sc->p2p)))
3275 printf("%s: p2p_detach() failed; error %d\n", NAME_UNIT, error);
3276 printf("%s: Try 'ifconfig %s down -remove'\n", NAME_UNIT, NAME_UNIT);
3277 config->line_pkg = PKG_P2P; /* not in RAWIP mode; still attached to P2P */
3281 setup_ifnet(sc->ifp);
3282 LMC_BPF_ATTACH(DLT_RAW, 0);
3285 hdlc_proto_detach(sc->hdlc_dev);
3286 hdlc_close(sc->net_dev);
3287 setup_netdev(sc->net_dev);
3293 if (config->line_pkg != PKG_RAWIP)
3295 /* Check for change to PPP protocol. */
3296 if ((sc->config.line_prot != PROT_PPP) &&
3297 (config->line_prot == PROT_PPP))
3300 sc->ifp->if_flags &= ~IFF_LINK2;
3301 sc->sppp->pp_flags &= ~PP_FR;
3302 LMC_BPF_ATTACH(DLT_PPP, 4);
3303 sppp_ioctl(sc->ifp, SIOCSIFFLAGS, NULL);
3307 # define DLT_C_HDLC DLT_PPP
3310 /* Check for change to C_HDLC protocol. */
3311 if ((sc->config.line_prot != PROT_C_HDLC) &&
3312 (config->line_prot == PROT_C_HDLC))
3315 sc->ifp->if_flags |= IFF_LINK2;
3316 sc->sppp->pp_flags &= ~PP_FR;
3317 LMC_BPF_ATTACH(DLT_C_HDLC, 4);
3318 sppp_ioctl(sc->ifp, SIOCSIFFLAGS, NULL);
3321 /* Check for change to Frame Relay protocol. */
3322 if ((sc->config.line_prot != PROT_FRM_RLY) &&
3323 (config->line_prot == PROT_FRM_RLY))
3326 sc->ifp->if_flags &= ~IFF_LINK2;
3327 sc->sppp->pp_flags |= PP_FR;
3328 LMC_BPF_ATTACH(DLT_FRELAY, 4);
3329 sppp_ioctl(sc->ifp, SIOCSIFFLAGS, NULL);
3332 /* Check for disabling keep-alives. */
3333 if ((sc->config.keep_alive != 0) &&
3334 (config->keep_alive == 0))
3335 sc->sppp->pp_flags &= ~PP_KEEPALIVE;
3337 /* Check for enabling keep-alives. */
3338 if ((sc->config.keep_alive == 0) &&
3339 (config->keep_alive != 0))
3340 sc->sppp->pp_flags |= PP_KEEPALIVE;
3345 /* Loop back through the TULIP Ethernet chip; (no CRC). */
3346 /* Data sheet says stop DMA before changing OPMODE register. */
3347 /* But that's not as simple as it sounds; works anyway. */
3348 /* Check for enabling loopback thru Tulip chip. */
3349 if ((sc->config.loop_back != CFG_LOOP_TULIP) &&
3350 (config->loop_back == CFG_LOOP_TULIP))
3352 u_int32_t op_mode = READ_CSR(TLP_OP_MODE);
3353 op_mode |= TLP_OP_INT_LOOP;
3354 WRITE_CSR(TLP_OP_MODE, op_mode);
3355 config->crc_len = CFG_CRC_0;
3358 /* Check for disabling loopback thru Tulip chip. */
3359 if ((sc->config.loop_back == CFG_LOOP_TULIP) &&
3360 (config->loop_back != CFG_LOOP_TULIP))
3362 u_int32_t op_mode = READ_CSR(TLP_OP_MODE);
3363 op_mode &= ~TLP_OP_LOOP_MODE;
3364 WRITE_CSR(TLP_OP_MODE, op_mode);
3365 config->crc_len = CFG_CRC_16;
3369 /* This is the core ioctl procedure. */
3370 /* It handles IOCTLs from lmcconfig(8). */
3371 /* It must not run when card watchdogs run. */
3372 /* Called from a syscall (user context; no spinlocks). */
3373 /* This procedure can SLEEP. */
3375 core_ioctl(softc_t *sc, u_long cmd, caddr_t data)
3377 struct iohdr *iohdr = (struct iohdr *) data;
3378 struct ioctl *ioctl = (struct ioctl *) data;
3379 struct status *status = (struct status *) data;
3380 struct config *config = (struct config *) data;
3383 /* All structs start with a string and a cookie. */
3384 if (((struct iohdr *)data)->cookie != NGM_LMC_COOKIE)
3387 while (TOP_TRYLOCK == 0)
3389 sc->status.cntrs.lck_ioctl++;
3390 SLEEP(10000); /* yield? */
3396 *status = sc->status;
3397 iohdr->cookie = NGM_LMC_COOKIE;
3402 *config = sc->config;
3403 iohdr->cookie = NGM_LMC_COOKIE;
3408 if ((error = CHECK_CAP)) break;
3409 config_proto(sc, config);
3410 sc->config = *config;
3411 sc->card->config(sc);
3416 if (ioctl->cmd == IOCTL_RW_PCI)
3418 if (ioctl->address > 252) { error = EFAULT; break; }
3419 ioctl->data = READ_PCI_CFG(sc, ioctl->address);
3421 else if (ioctl->cmd == IOCTL_RW_CSR)
3423 if (ioctl->address > 15) { error = EFAULT; break; }
3424 ioctl->data = READ_CSR(ioctl->address*TLP_CSR_STRIDE);
3426 else if (ioctl->cmd == IOCTL_RW_SROM)
3428 if (ioctl->address > 63) { error = EFAULT; break; }
3429 ioctl->data = read_srom(sc, ioctl->address);
3431 else if (ioctl->cmd == IOCTL_RW_BIOS)
3432 ioctl->data = read_bios(sc, ioctl->address);
3433 else if (ioctl->cmd == IOCTL_RW_MII)
3434 ioctl->data = read_mii(sc, ioctl->address);
3435 else if (ioctl->cmd == IOCTL_RW_FRAME)
3436 ioctl->data = read_framer(sc, ioctl->address);
3443 if ((error = CHECK_CAP)) break;
3444 if (ioctl->cmd == IOCTL_RW_PCI)
3446 if (ioctl->address > 252) { error = EFAULT; break; }
3447 WRITE_PCI_CFG(sc, ioctl->address, ioctl->data);
3449 else if (ioctl->cmd == IOCTL_RW_CSR)
3451 if (ioctl->address > 15) { error = EFAULT; break; }
3452 WRITE_CSR(ioctl->address*TLP_CSR_STRIDE, ioctl->data);
3454 else if (ioctl->cmd == IOCTL_RW_SROM)
3456 if (ioctl->address > 63) { error = EFAULT; break; }
3457 write_srom(sc, ioctl->address, ioctl->data); /* can sleep */
3459 else if (ioctl->cmd == IOCTL_RW_BIOS)
3461 if (ioctl->address == 0) erase_bios(sc);
3462 write_bios(sc, ioctl->address, ioctl->data); /* can sleep */
3464 else if (ioctl->cmd == IOCTL_RW_MII)
3465 write_mii(sc, ioctl->address, ioctl->data);
3466 else if (ioctl->cmd == IOCTL_RW_FRAME)
3467 write_framer(sc, ioctl->address, ioctl->data);
3468 else if (ioctl->cmd == IOCTL_WO_SYNTH)
3469 write_synth(sc, (struct synth *)&ioctl->data);
3470 else if (ioctl->cmd == IOCTL_WO_DAC)
3472 write_dac(sc, 0x9002); /* set Vref = 2.048 volts */
3473 write_dac(sc, ioctl->data & 0xFFF);
3481 if ((error = CHECK_CAP)) break;
3482 if (ioctl->cmd == IOCTL_XILINX_RESET)
3485 sc->card->config(sc);
3487 else if (ioctl->cmd == IOCTL_XILINX_ROM)
3489 load_xilinx_from_rom(sc); /* can sleep */
3490 sc->card->config(sc);
3492 else if (ioctl->cmd == IOCTL_XILINX_FILE)
3494 /* load_xilinx_from_file() can sleep. */
3495 error = load_xilinx_from_file(sc, ioctl->ucode, ioctl->data);
3496 if (error != 0) load_xilinx_from_rom(sc); /* try the rom */
3497 sc->card->config(sc);
3498 set_status(sc, (error==0)); /* XXX */
3500 else if (ioctl->cmd == IOCTL_RESET_CNTRS)
3502 memset(&sc->status.cntrs, 0, sizeof(struct event_cntrs));
3503 microtime(&sc->status.cntrs.reset_time);
3506 error = sc->card->ioctl(sc, ioctl); /* can sleep */
3518 /* This is the core watchdog procedure. */
3519 /* It calculates link speed, and calls the card-specific watchdog code. */
3520 /* Calls interrupt() in case one got lost; also kick-starts the device. */
3521 /* ioctl syscalls and card watchdog routines must be interlocked. */
3522 /* This procedure must not sleep. */
3524 core_watchdog(softc_t *sc)
3526 /* Read and restart the Tulip timer. */
3527 u_int32_t tx_speed = READ_CSR(TLP_TIMER);
3528 WRITE_CSR(TLP_TIMER, 0xFFFF);
3530 /* Measure MII clock using a timer in the Tulip chip.
3531 * This timer counts transmitter bits divided by 4096.
3532 * Since this is called once a second the math is easy.
3533 * This is only correct when the link is NOT sending pkts.
3534 * On a fully-loaded link, answer will be HALF actual rate.
3535 * Clock rate during pkt is HALF clk rate between pkts.
3536 * Measuring clock rate really measures link utilization!
3538 sc->status.tx_speed = (0xFFFF - (tx_speed & 0xFFFF)) << 12;
3540 /* The first status reset time is when the calendar clock is set. */
3541 if (sc->status.cntrs.reset_time.tv_sec < 1000)
3542 microtime(&sc->status.cntrs.reset_time);
3544 /* Update hardware (operational) status. */
3545 /* Call the card-specific watchdog routines. */
3546 if (TOP_TRYLOCK != 0)
3548 sc->status.oper_status = sc->card->watchdog(sc);
3550 /* Increment a counter which tells user-land */
3551 /* observers that SNMP state has been updated. */
3557 sc->status.cntrs.lck_watch++;
3559 /* In case an interrupt gets lost... */
3560 user_interrupt(sc, 1);
3564 /* Called from a syscall (user context; no spinlocks). */
3566 lmc_raw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
3568 struct ifreq *ifr = (struct ifreq *) data;
3576 ifp->if_flags |= IFF_UP; /* a Unix tradition */
3579 ifp->if_mtu = ifr->ifr_mtu;
3588 /* Called from a syscall (user context; no spinlocks). */
3590 lmc_ifnet_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
3592 softc_t *sc = IFP2SC(ifp);
3597 /* Catch the IOCTLs used by lmcconfig. */
3604 error = core_ioctl(sc, cmd, data);
3606 /* Pass the rest to the line protocol. */
3608 if (sc->config.line_pkg == PKG_RAWIP)
3609 error = lmc_raw_ioctl(ifp, cmd, data);
3612 error = sppp_ioctl(ifp, cmd, data);
3614 error = p2p_ioctl(ifp, cmd, data);
3621 if (DRIVER_DEBUG && (error!=0))
3622 printf("%s: lmc_ifnet_ioctl; cmd=0x%08lx error=%d\n",
3623 NAME_UNIT, cmd, error);
3628 /* Called from a syscall (user context; no spinlocks). */
3630 lmc_ifnet_start(struct ifnet *ifp)
3632 softc_t *sc = IFP2SC(ifp);
3634 /* Start the transmitter; incoming pkts are NOT processed. */
3635 user_interrupt(sc, 0);
3638 /* sppp and p2p replace this with their own proc. */
3639 /* RAWIP mode is the only time this is used. */
3640 /* Called from a syscall (user context; no spinlocks). */
3642 lmc_raw_output(struct ifnet *ifp, struct mbuf *m,
3643 const struct sockaddr *dst, struct route *ro)
3645 softc_t *sc = IFP2SC(ifp);
3648 /* Fail if the link is down. */
3649 if (sc->status.oper_status != STATUS_UP)
3652 sc->status.cntrs.odiscards++;
3654 printf("%s: lmc_raw_output: tx pkt discarded: link down\n", NAME_UNIT);
3659 /* Netgraph has priority over the ifnet kernel interface. */
3660 if (sc->ng_hook != NULL)
3663 sc->status.cntrs.odiscards++;
3665 printf("%s: lmc_raw_output: tx pkt discarded: netgraph active\n",
3671 /* lmc_raw_output() ENQUEUEs in a syscall or softirq. */
3672 /* txintr_setup() DEQUEUEs in a hard interrupt. */
3673 /* Some BSD QUEUE routines are not interrupt-safe. */
3676 IFQ_ENQUEUE(&ifp->if_snd, m, error);
3681 user_interrupt(sc, 0); /* start the transmitter */
3685 sc->status.cntrs.odiscards++;
3686 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1);
3688 printf("%s: lmc_raw_output: IFQ_ENQUEUE() failed; error %d\n",
3695 /* Called from a softirq once a second. */
3697 lmc_watchdog(void *arg)
3699 struct ifnet *ifp = arg;
3700 softc_t *sc = IFP2SC(ifp);
3701 u_int8_t old_oper_status = sc->status.oper_status;
3703 core_watchdog(sc); /* updates oper_status */
3706 if (sc->ng_hook != NULL)
3708 sc->status.line_pkg = PKG_NG;
3709 sc->status.line_prot = 0;
3713 if (sc->config.line_pkg == PKG_RAWIP)
3715 sc->status.line_pkg = PKG_RAWIP;
3716 sc->status.line_prot = PROT_IP_HDLC;
3721 /* Notice change in link status. */
3722 if ((old_oper_status != sc->status.oper_status) && (sc->p2p->p2p_modem))
3723 (*sc->p2p->p2p_modem)(sc->p2p, sc->status.oper_status==STATUS_UP);
3725 /* Notice change in line protocol. */
3726 sc->status.line_pkg = PKG_P2P;
3727 switch (sc->ifp->if_type)
3730 sc->status.line_prot = PROT_PPP;
3733 sc->status.line_prot = PROT_C_HDLC;
3736 sc->status.line_prot = PROT_FRM_RLY;
3739 sc->status.line_prot = 0;
3744 /* Notice change in link status. */
3745 if ((old_oper_status != STATUS_UP) &&
3746 (sc->status.oper_status == STATUS_UP)) /* link came up */
3748 if ((old_oper_status == STATUS_UP) &&
3749 (sc->status.oper_status != STATUS_UP)) /* link went down */
3752 /* Notice change in line protocol. */
3753 sc->status.line_pkg = PKG_SPPP;
3754 if (sc->sppp->pp_flags & PP_FR)
3755 sc->status.line_prot = PROT_FRM_RLY;
3756 else if (sc->ifp->if_flags & IFF_LINK2)
3757 sc->status.line_prot = PROT_C_HDLC;
3759 sc->status.line_prot = PROT_PPP;
3762 /* Suppress compiler warning. */
3763 if (old_oper_status == STATUS_UP);
3767 ifp->if_baudrate = sc->status.tx_speed;
3768 if (sc->status.oper_status == STATUS_UP)
3769 ifp->if_link_state = LINK_STATE_UP;
3771 ifp->if_link_state = LINK_STATE_DOWN;
3773 /* Call this procedure again after one second. */
3774 callout_reset(&sc->callout, hz, lmc_watchdog, ifp);
3778 lmc_get_counter(struct ifnet *ifp, ift_counter cnt)
3781 struct event_cntrs *cntrs;
3783 sc = if_getsoftc(ifp);
3784 cntrs = &sc->status.cntrs;
3787 case IFCOUNTER_IPACKETS:
3788 return (cntrs->ipackets);
3789 case IFCOUNTER_OPACKETS:
3790 return (cntrs->opackets);
3791 case IFCOUNTER_IBYTES:
3792 return (cntrs->ibytes);
3793 case IFCOUNTER_OBYTES:
3794 return (cntrs->obytes);
3795 case IFCOUNTER_IERRORS:
3796 return (cntrs->ierrors);
3797 case IFCOUNTER_OERRORS:
3798 return (cntrs->oerrors);
3799 case IFCOUNTER_IQDROPS:
3800 return (cntrs->idiscards);
3802 return (if_get_counter_default(ifp, cnt));
3807 setup_ifnet(struct ifnet *ifp)
3809 softc_t *sc = ifp->if_softc;
3811 /* Initialize the generic network interface. */
3812 ifp->if_flags = IFF_POINTOPOINT;
3813 ifp->if_flags |= IFF_RUNNING;
3814 ifp->if_ioctl = lmc_ifnet_ioctl;
3815 ifp->if_start = lmc_ifnet_start; /* sppp changes this */
3816 ifp->if_output = lmc_raw_output; /* sppp & p2p change this */
3817 ifp->if_input = lmc_raw_input;
3818 ifp->if_get_counter = lmc_get_counter;
3819 ifp->if_mtu = MAX_DESC_LEN; /* sppp & p2p change this */
3820 ifp->if_type = IFT_PTPSERIAL; /* p2p changes this */
3822 # if defined(DEVICE_POLLING)
3823 ifp->if_capabilities |= IFCAP_POLLING;
3824 ifp->if_capenable |= IFCAP_POLLING_NOCOUNT;
3827 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
3831 lmc_ifnet_attach(softc_t *sc)
3833 sc->ifp = if_alloc(NSPPP ? IFT_PPP : IFT_OTHER);
3834 if (sc->ifp == NULL) return ENOMEM;
3836 sc->sppp = sc->ifp->if_l2com;
3838 sc->ifp = &sc->p2pcom.p2p_if;
3839 sc->p2p = &sc->p2pcom;
3842 /* Initialize the network interface struct. */
3843 sc->ifp->if_softc = sc;
3844 setup_ifnet(sc->ifp);
3846 /* ALTQ output queue initialization. */
3847 IFQ_SET_MAXLEN(&sc->ifp->if_snd, SNDQ_MAXLEN);
3848 IFQ_SET_READY(&sc->ifp->if_snd);
3850 /* Attach to the ifnet kernel interface. */
3853 /* Attach Berkeley Packet Filter. */
3854 LMC_BPF_ATTACH(DLT_RAW, 0);
3856 callout_reset(&sc->callout, hz, lmc_watchdog, sc);
3862 lmc_ifnet_detach(softc_t *sc)
3865 # if defined(DEVICE_POLLING)
3866 if (sc->ifp->if_capenable & IFCAP_POLLING)
3867 ether_poll_deregister(sc->ifp);
3870 /* Detach Berkeley Packet Filter. */
3873 /* Detach from the ifnet kernel interface. */
3882 /* These next two macros should be added to netgraph */
3883 # define NG_TYPE_REF(type) atomic_add_int(&(type)->refs, 1)
3884 # define NG_TYPE_UNREF(type) \
3886 if ((type)->refs == 1) \
3889 atomic_subtract_int(&(type)->refs, 1); \
3892 /* It is an error to construct new copies of this Netgraph node. */
3893 /* All instances are constructed by ng_attach and are persistent. */
3894 static int ng_constructor(node_p node) { return EINVAL; }
3896 /* Incoming Netgraph control message. */
3898 ng_rcvmsg(node_p node, item_p item, hook_p lasthook)
3900 struct ng_mesg *msg;
3901 struct ng_mesg *resp = NULL;
3902 softc_t *sc = NG_NODE_PRIVATE(node);
3905 NGI_GET_MSG(item, msg);
3906 if (msg->header.typecookie == NGM_LMC_COOKIE)
3908 switch (msg->header.cmd)
3917 /* Call the core ioctl procedure. */
3918 error = core_ioctl(sc, msg->header.cmd, msg->data);
3919 if ((msg->header.cmd & IOC_OUT) != 0)
3920 { /* synchronous response */
3921 NG_MKRESPONSE(resp, msg, sizeof(struct ng_mesg) +
3922 IOCPARM_LEN(msg->header.cmd), M_NOWAIT);
3926 memcpy(resp->data, msg->data, IOCPARM_LEN(msg->header.cmd));
3935 else if ((msg->header.typecookie == NGM_GENERIC_COOKIE) &&
3936 (msg->header.cmd == NGM_TEXT_STATUS))
3937 { /* synchronous response */
3938 NG_MKRESPONSE(resp, msg, sizeof(struct ng_mesg) +
3939 NG_TEXTRESPONSE, M_NOWAIT);
3944 char *s = resp->data;
3945 sprintf(s, "Card type = <%s>\n"
3946 "This driver considers the link to be %s.\n"
3947 "Use lmcconfig to configure this interface.\n",
3948 sc->dev_desc, (sc->status.oper_status==STATUS_UP) ? "UP" : "DOWN");
3949 resp->header.arglen = strlen(s) +1;
3953 /* Netgraph should be able to read and write these
3954 * parameters with text-format control messages:
3957 * loop loop loop loop
3959 * dte dte format format
3960 * synth synth cablen cablen
3961 * cable timeslot scram
3965 * Someday I'll implement this...
3969 /* Handle synchronous response. */
3970 NG_RESPOND_MSG(error, node, item, resp);
3976 /* This is a persistent netgraph node. */
3978 ng_shutdown(node_p node)
3980 /* unless told to really die, bounce back to life */
3981 if ((node->nd_flags & NG_REALLY_DIE)==0)
3982 node->nd_flags &= ~NG_INVALID; /* bounce back to life */
3987 /* ng_disconnect is the opposite of this procedure. */
3989 ng_newhook(node_p node, hook_p hook, const char *name)
3991 softc_t *sc = NG_NODE_PRIVATE(node);
3993 /* Hook name must be 'rawdata'. */
3994 if (strncmp(name, "rawdata", 7) != 0) return EINVAL;
3996 /* Is our hook connected? */
3997 if (sc->ng_hook != NULL) return EBUSY;
3999 /* Accept the hook. */
4005 /* Both ends have accepted their hooks and the links have been made. */
4006 /* This is the last chance to reject the connection request. */
4008 ng_connect(hook_p hook)
4010 /* Probably not at splnet, force outward queueing. (huh?) */
4011 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook));
4012 return 0; /* always accept */
4015 /* Receive data in mbufs from another Netgraph node. */
4016 /* Transmit an mbuf-chain on the communication link. */
4017 /* This procedure is very similar to lmc_raw_output(). */
4018 /* Called from a syscall (user context; no spinlocks). */
4020 ng_rcvdata(hook_p hook, item_p item)
4022 softc_t *sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
4028 NGI_GET_META(item, meta);
4031 /* This macro must not store into meta! */
4034 /* Fail if the link is down. */
4035 if (sc->status.oper_status != STATUS_UP)
4038 sc->status.cntrs.odiscards++;
4040 printf("%s: ng_rcvdata: tx pkt discarded: link down\n", NAME_UNIT);
4044 /* ng_rcvdata() ENQUEUEs in a syscall or softirq. */
4045 /* txintr_setup() DEQUEUEs in a hard interrupt. */
4046 /* Some BSD QUEUE routines are not interrupt-safe. */
4050 IFQ_ENQUEUE(&sc->ng_sndq, m, error);
4052 IFQ_ENQUEUE(&sc->ng_fastq, m, error);
4057 user_interrupt(sc, 0); /* start the transmitter */
4061 sc->status.cntrs.odiscards++;
4063 printf("%s: ng_rcvdata: IFQ_ENQUEUE() failed; error %d\n",
4070 /* ng_newhook is the opposite of this procedure, not */
4071 /* ng_connect, as you might expect from the names. */
4073 ng_disconnect(hook_p hook)
4075 softc_t *sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
4077 /* Disconnect the hook. */
4084 struct ng_type ng_type =
4086 .version = NG_ABI_VERSION,
4087 .name = NG_LMC_NODE_TYPE,
4089 .constructor = ng_constructor,
4090 .rcvmsg = ng_rcvmsg,
4092 .shutdown = ng_shutdown,
4093 .newhook = ng_newhook,
4095 .connect = ng_connect,
4096 .rcvdata = ng_rcvdata,
4097 .disconnect = ng_disconnect,
4101 /* Attach to the Netgraph kernel interface (/sys/netgraph).
4102 * It is called once for each physical card during device attach.
4103 * This is effectively ng_constructor.
4106 ng_attach(softc_t *sc)
4110 /* If this node type is not known to Netgraph then register it. */
4111 if (ng_type.refs == 0) /* or: if (ng_findtype(&ng_type) == NULL) */
4113 if ((error = ng_newtype(&ng_type)))
4115 printf("%s: ng_newtype() failed; error %d\n", NAME_UNIT, error);
4120 NG_TYPE_REF(&ng_type);
4122 /* Call the superclass node constructor. */
4123 if ((error = ng_make_node_common(&ng_type, &sc->ng_node)))
4125 NG_TYPE_UNREF(&ng_type);
4126 printf("%s: ng_make_node_common() failed; error %d\n", NAME_UNIT, error);
4130 /* Associate a name with this netgraph node. */
4131 if ((error = ng_name_node(sc->ng_node, NAME_UNIT)))
4133 NG_NODE_UNREF(sc->ng_node);
4134 NG_TYPE_UNREF(&ng_type);
4135 printf("%s: ng_name_node() failed; error %d\n", NAME_UNIT, error);
4139 /* Initialize the send queue mutexes. */
4140 mtx_init(&sc->ng_sndq.ifq_mtx, NAME_UNIT, "sndq", MTX_DEF);
4141 mtx_init(&sc->ng_fastq.ifq_mtx, NAME_UNIT, "fastq", MTX_DEF);
4143 /* Put a backpointer to the softc in the netgraph node. */
4144 NG_NODE_SET_PRIVATE(sc->ng_node, sc);
4146 /* ALTQ output queue initialization. */
4147 IFQ_SET_MAXLEN(&sc->ng_fastq, SNDQ_MAXLEN);
4148 IFQ_SET_READY(&sc->ng_fastq);
4149 IFQ_SET_MAXLEN(&sc->ng_sndq, SNDQ_MAXLEN);
4150 IFQ_SET_READY(&sc->ng_sndq);
4157 ng_detach(softc_t *sc)
4159 callout_drain(&sc->callout);
4160 mtx_destroy(&sc->ng_sndq.ifq_mtx);
4161 mtx_destroy(&sc->ng_fastq.ifq_mtx);
4162 ng_rmnode_self(sc->ng_node); /* free hook */
4163 NG_NODE_UNREF(sc->ng_node); /* free node */
4164 NG_TYPE_UNREF(&ng_type);
4167 #endif /* NETGRAPH */
4169 /* The next few procedures initialize the card. */
4171 /* Returns 0 on success; error code on failure. */
4173 startup_card(softc_t *sc)
4175 int num_rx_descs, error = 0;
4176 u_int32_t tlp_bus_pbl, tlp_bus_cal, tlp_op_tr;
4177 u_int32_t tlp_cfdd, tlp_cfcs;
4178 u_int32_t tlp_cflt, tlp_csid, tlp_cfit;
4180 /* Make sure the COMMAND bits are reasonable. */
4181 tlp_cfcs = READ_PCI_CFG(sc, TLP_CFCS);
4182 tlp_cfcs &= ~TLP_CFCS_MWI_ENABLE;
4183 tlp_cfcs |= TLP_CFCS_BUS_MASTER;
4184 tlp_cfcs |= TLP_CFCS_MEM_ENABLE;
4185 tlp_cfcs |= TLP_CFCS_IO_ENABLE;
4186 tlp_cfcs |= TLP_CFCS_PAR_ERROR;
4187 tlp_cfcs |= TLP_CFCS_SYS_ERROR;
4188 WRITE_PCI_CFG(sc, TLP_CFCS, tlp_cfcs);
4190 /* Set the LATENCY TIMER to the recommended value, */
4191 /* and make sure the CACHE LINE SIZE is reasonable. */
4192 tlp_cfit = READ_PCI_CFG(sc, TLP_CFIT);
4193 tlp_cflt = READ_PCI_CFG(sc, TLP_CFLT);
4194 tlp_cflt &= ~TLP_CFLT_LATENCY;
4195 tlp_cflt |= (tlp_cfit & TLP_CFIT_MAX_LAT)>>16;
4196 /* "prgmbl burst length" and "cache alignment" used below. */
4197 switch(tlp_cflt & TLP_CFLT_CACHE)
4199 case 8: /* 8 bytes per cache line */
4200 { tlp_bus_pbl = 32; tlp_bus_cal = 1; break; }
4202 { tlp_bus_pbl = 32; tlp_bus_cal = 2; break; }
4204 { tlp_bus_pbl = 32; tlp_bus_cal = 3; break; }
4207 tlp_bus_pbl = 32; tlp_bus_cal = 1;
4208 tlp_cflt &= ~TLP_CFLT_CACHE;
4213 WRITE_PCI_CFG(sc, TLP_CFLT, tlp_cflt);
4215 /* Make sure SNOOZE and SLEEP modes are disabled. */
4216 tlp_cfdd = READ_PCI_CFG(sc, TLP_CFDD);
4217 tlp_cfdd &= ~TLP_CFDD_SLEEP;
4218 tlp_cfdd &= ~TLP_CFDD_SNOOZE;
4219 WRITE_PCI_CFG(sc, TLP_CFDD, tlp_cfdd);
4220 DELAY(11*1000); /* Tulip wakes up in 10 ms max */
4222 /* Software Reset the Tulip chip; stops DMA and Interrupts. */
4223 /* This does not change the PCI config regs just set above. */
4224 WRITE_CSR(TLP_BUS_MODE, TLP_BUS_RESET); /* self-clearing */
4225 DELAY(5); /* Tulip is dead for 50 PCI cycles after reset. */
4227 /* Reset the Xilinx Field Programmable Gate Array. */
4228 reset_xilinx(sc); /* side effect: turns on all four LEDs */
4230 /* Configure card-specific stuff (framers, line interfaces, etc.). */
4231 sc->card->config(sc);
4233 /* Initializing cards can glitch clocks and upset fifos. */
4234 /* Reset the FIFOs between the Tulip and Xilinx chips. */
4235 set_mii16_bits(sc, MII16_FIFO);
4236 clr_mii16_bits(sc, MII16_FIFO);
4238 /* Initialize the PCI busmode register. */
4239 /* The PCI bus cycle type "Memory Write and Invalidate" does NOT */
4240 /* work cleanly in any version of the 21140A, so don't enable it! */
4241 WRITE_CSR(TLP_BUS_MODE,
4242 (tlp_bus_cal ? TLP_BUS_READ_LINE : 0) |
4243 (tlp_bus_cal ? TLP_BUS_READ_MULT : 0) |
4244 (tlp_bus_pbl<<TLP_BUS_PBL_SHIFT) |
4245 (tlp_bus_cal<<TLP_BUS_CAL_SHIFT) |
4246 ((BYTE_ORDER == BIG_ENDIAN) ? TLP_BUS_DESC_BIGEND : 0) |
4247 ((BYTE_ORDER == BIG_ENDIAN) ? TLP_BUS_DATA_BIGEND : 0) |
4251 /* Pick number of RX descriptors and TX fifo threshold. */
4252 /* tx_threshold in bytes: 0=128, 1=256, 2=512, 3=1024 */
4253 tlp_csid = READ_PCI_CFG(sc, TLP_CSID);
4256 case TLP_CSID_HSSI: /* 52 Mb/s */
4257 case TLP_CSID_HSSIc: /* 52 Mb/s */
4258 case TLP_CSID_T3: /* 45 Mb/s */
4259 { num_rx_descs = 48; tlp_op_tr = 2; break; }
4260 case TLP_CSID_SSI: /* 10 Mb/s */
4261 { num_rx_descs = 32; tlp_op_tr = 1; break; }
4262 case TLP_CSID_T1E1: /* 2 Mb/s */
4263 { num_rx_descs = 16; tlp_op_tr = 0; break; }
4265 { num_rx_descs = 16; tlp_op_tr = 0; break; }
4268 /* Create DMA descriptors and initialize list head registers. */
4269 if ((error = create_ring(sc, &sc->txring, NUM_TX_DESCS))) return error;
4270 WRITE_CSR(TLP_TX_LIST, sc->txring.dma_addr);
4271 if ((error = create_ring(sc, &sc->rxring, num_rx_descs))) return error;
4272 WRITE_CSR(TLP_RX_LIST, sc->rxring.dma_addr);
4274 /* Initialize the operating mode register. */
4275 WRITE_CSR(TLP_OP_MODE, TLP_OP_INIT | (tlp_op_tr<<TLP_OP_TR_SHIFT));
4277 /* Read the missed frame register (result ignored) to zero it. */
4278 error = READ_CSR( TLP_MISSED); /* error is used as a bit-dump */
4280 /* Disable rx watchdog and tx jabber features. */
4281 WRITE_CSR(TLP_WDOG, TLP_WDOG_INIT);
4283 /* Enable card interrupts. */
4284 WRITE_CSR(TLP_INT_ENBL, TLP_INT_TXRX);
4289 /* Stop DMA and Interrupts; free descriptors and buffers. */
4291 shutdown_card(void *arg)
4295 /* Leave the LEDs in the state they were in after power-on. */
4296 led_on(sc, MII16_LED_ALL);
4298 /* Software reset the Tulip chip; stops DMA and Interrupts */
4299 WRITE_CSR(TLP_BUS_MODE, TLP_BUS_RESET); /* self-clearing */
4300 DELAY(5); /* Tulip is dead for 50 PCI cycles after reset. */
4302 /* Disconnect from the PCI bus except for config cycles. */
4303 /* Hmmm; Linux syslogs a warning that IO and MEM are disabled. */
4304 WRITE_PCI_CFG(sc, TLP_CFCS, TLP_CFCS_MEM_ENABLE | TLP_CFCS_IO_ENABLE);
4306 /* Free the DMA descriptor rings. */
4307 destroy_ring(sc, &sc->txring);
4308 destroy_ring(sc, &sc->rxring);
4311 /* Start the card and attach a kernel interface and line protocol. */
4313 attach_card(softc_t *sc, const char *intrstr)
4315 struct config config;
4321 /* Start the card. */
4322 if ((error = startup_card(sc))) return error;
4324 callout_init(&sc->callout, 0);
4326 /* Attach a kernel interface. */
4328 if ((error = ng_attach(sc))) return error;
4329 sc->flags |= FLAG_NETGRAPH;
4331 if ((error = lmc_ifnet_attach(sc))) return error;
4332 sc->flags |= FLAG_IFNET;
4334 /* Attach a line protocol stack. */
4335 sc->config.line_pkg = PKG_RAWIP;
4336 config = sc->config; /* get current config */
4337 config.line_pkg = 0; /* select external stack */
4338 config.line_prot = PROT_C_HDLC;
4339 config.keep_alive = 1;
4340 config_proto(sc, &config); /* reconfigure */
4341 sc->config = config; /* save new configuration */
4343 /* Print interesting hardware-related things. */
4344 mii3 = read_mii(sc, 3);
4345 tlp_cfrv = READ_PCI_CFG(sc, TLP_CFRV);
4346 printf("%s: PCI rev %d.%d, MII rev %d.%d", NAME_UNIT,
4347 (tlp_cfrv>>4) & 0xF, tlp_cfrv & 0xF, (mii3>>4) & 0xF, mii3 & 0xF);
4348 ieee = (u_int8_t *)sc->status.ieee;
4349 for (i=0; i<3; i++) sc->status.ieee[i] = read_srom(sc, 10+i);
4350 printf(", IEEE addr %02x:%02x:%02x:%02x:%02x:%02x",
4351 ieee[0], ieee[1], ieee[2], ieee[3], ieee[4], ieee[5]);
4352 sc->card->ident(sc);
4353 printf(" %s\n", intrstr);
4355 /* Print interesting software-related things. */
4356 printf("%s: Driver rev %d.%d.%d", NAME_UNIT,
4357 DRIVER_MAJOR_VERSION, DRIVER_MINOR_VERSION, DRIVER_SUB_VERSION);
4358 printf(", Options %s%s%s%s%s%s%s%s%s\n",
4359 NETGRAPH ? "NETGRAPH " : "", GEN_HDLC ? "GEN_HDLC " : "",
4360 NSPPP ? "SPPP " : "", P2P ? "P2P " : "",
4361 ALTQ_PRESENT ? "ALTQ " : "", NBPFILTER ? "BPF " : "",
4362 DEV_POLL ? "POLL " : "", IOREF_CSR ? "IO_CSR " : "MEM_CSR ",
4363 (BYTE_ORDER == BIG_ENDIAN) ? "BIG_END " : "LITTLE_END ");
4365 /* Make the local hardware ready. */
4371 /* Detach from the kernel in all ways. */
4373 detach_card(softc_t *sc)
4375 struct config config;
4377 /* Make the local hardware NOT ready. */
4380 /* Detach external line protocol stack. */
4381 if (sc->config.line_pkg != PKG_RAWIP)
4383 config = sc->config;
4384 config.line_pkg = PKG_RAWIP;
4385 config_proto(sc, &config);
4386 sc->config = config;
4389 /* Detach kernel interfaces. */
4391 if (sc->flags & FLAG_NETGRAPH)
4393 IFQ_PURGE(&sc->ng_fastq);
4394 IFQ_PURGE(&sc->ng_sndq);
4396 sc->flags &= ~FLAG_NETGRAPH;
4399 if (sc->flags & FLAG_IFNET)
4401 IFQ_PURGE(&sc->ifp->if_snd);
4402 lmc_ifnet_detach(sc);
4403 sc->flags &= ~FLAG_IFNET;
4406 /* Reset the Tulip chip; stops DMA and Interrupts. */
4410 /* This is the I/O configuration interface for FreeBSD */
4414 fbsd_probe(device_t dev)
4416 u_int32_t cfid = pci_read_config(dev, TLP_CFID, 4);
4417 u_int32_t csid = pci_read_config(dev, TLP_CSID, 4);
4419 /* Looking for a DEC 21140A chip on any Lan Media Corp card. */
4420 if (cfid != TLP_CFID_TULIP) return ENXIO;
4424 case TLP_CSID_HSSIc:
4425 device_set_desc(dev, HSSI_DESC);
4428 device_set_desc(dev, T3_DESC);
4431 device_set_desc(dev, SSI_DESC);
4434 device_set_desc(dev, T1E1_DESC);
4443 fbsd_detach(device_t dev)
4445 softc_t *sc = device_get_softc(dev);
4447 /* Stop the card and detach from the kernel. */
4450 /* Release resources. */
4451 if (sc->irq_cookie != NULL)
4453 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie);
4454 sc->irq_cookie = NULL;
4456 if (sc->irq_res != NULL)
4458 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_res_id, sc->irq_res);
4461 if (sc->csr_res != NULL)
4463 bus_release_resource(dev, sc->csr_res_type, sc->csr_res_id, sc->csr_res);
4467 mtx_destroy(&sc->top_mtx);
4468 mtx_destroy(&sc->bottom_mtx);
4469 return 0; /* no error */
4473 fbsd_shutdown(device_t dev)
4475 shutdown_card(device_get_softc(dev));
4480 fbsd_attach(device_t dev)
4482 softc_t *sc = device_get_softc(dev);
4485 /* READ/WRITE_PCI_CFG need this. */
4488 /* What kind of card are we driving? */
4489 switch (READ_PCI_CFG(sc, TLP_CSID))
4492 case TLP_CSID_HSSIc:
4493 sc->card = &hssi_card;
4496 sc->card = &t3_card;
4499 sc->card = &ssi_card;
4502 sc->card = &t1_card;
4507 sc->dev_desc = device_get_desc(dev);
4509 /* Allocate PCI memory or IO resources to access the Tulip chip CSRs. */
4511 sc->csr_res_id = TLP_CBIO;
4512 sc->csr_res_type = SYS_RES_IOPORT;
4514 sc->csr_res_id = TLP_CBMA;
4515 sc->csr_res_type = SYS_RES_MEMORY;
4517 sc->csr_res = bus_alloc_resource_any(dev, sc->csr_res_type, &sc->csr_res_id,
4519 if (sc->csr_res == NULL)
4521 printf("%s: bus_alloc_resource(csr) failed.\n", NAME_UNIT);
4524 sc->csr_tag = rman_get_bustag(sc->csr_res);
4525 sc->csr_handle = rman_get_bushandle(sc->csr_res);
4527 /* Allocate PCI interrupt resources for the card. */
4529 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_res_id,
4530 RF_ACTIVE | RF_SHAREABLE);
4531 if (sc->irq_res == NULL)
4533 printf("%s: bus_alloc_resource(irq) failed.\n", NAME_UNIT);
4537 if ((error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,
4538 NULL, bsd_interrupt, sc, &sc->irq_cookie)))
4540 printf("%s: bus_setup_intr() failed; error %d\n", NAME_UNIT, error);
4545 /* Initialize the top-half and bottom-half locks. */
4546 mtx_init(&sc->top_mtx, NAME_UNIT, "top half lock", MTX_DEF);
4547 mtx_init(&sc->bottom_mtx, NAME_UNIT, "bottom half lock", MTX_DEF);
4549 /* Start the card and attach a kernel interface and line protocol. */
4550 if ((error = attach_card(sc, ""))) detach_card(sc);
4554 static device_method_t methods[] =
4556 DEVMETHOD(device_probe, fbsd_probe),
4557 DEVMETHOD(device_attach, fbsd_attach),
4558 DEVMETHOD(device_detach, fbsd_detach),
4559 DEVMETHOD(device_shutdown, fbsd_shutdown),
4560 /* This driver does not suspend and resume. */
4564 static driver_t driver =
4566 .name = DEVICE_NAME,
4568 .size = sizeof(softc_t),
4571 static devclass_t devclass;
4573 DRIVER_MODULE(lmc, pci, driver, devclass, 0, 0);
4574 MODULE_VERSION(lmc, 2);
4575 MODULE_DEPEND(lmc, pci, 1, 1, 1);
4577 MODULE_DEPEND(lmc, netgraph, NG_ABI_VERSION, NG_ABI_VERSION, NG_ABI_VERSION);
4580 MODULE_DEPEND(lmc, sppp, 1, 1, 1);
4584 /* This is the I/O configuration interface for NetBSD. */
4587 /* This is the I/O configuration interface for OpenBSD. */
4590 /* This is the I/O configuration interface for BSD/OS. */