2 * Copyright (c) 1994-1997 Matt Thomas (matt@3am-software.com)
3 * Copyright (c) LAN Media Corporation 1998, 1999.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the author may not be used to endorse or promote products
12 * derived from this software without specific prior written permission
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * From NetBSD: if_de.c,v 1.56.2.1 1997/10/27 02:13:25 thorpej Exp
26 * $Id: if_lmc_common.c,v 1.12 1999/03/01 15:22:37 explorer Exp $
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 * the dec chip has its own idea of what a receive error is, but we don't
34 * want to use it, as it will get the crc error wrong when 16-bit
35 * crcs are used. So, we only care about certain conditions.
37 #ifndef TULIP_DSTS_RxMIIERR
38 #define TULIP_DSTS_RxMIIERR 0x00000008
40 #define LMC_DSTS_ERRSUM (TULIP_DSTS_RxMIIERR)
43 lmc_gpio_mkinput(lmc_softc_t * const sc, u_int32_t bits)
45 sc->lmc_gpio_io &= ~bits;
46 LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
50 lmc_gpio_mkoutput(lmc_softc_t * const sc, u_int32_t bits)
52 sc->lmc_gpio_io |= bits;
53 LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
57 lmc_led_on(lmc_softc_t * const sc, u_int32_t led)
59 sc->lmc_miireg16 &= ~led;
60 lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
64 lmc_led_off(lmc_softc_t * const sc, u_int32_t led)
66 sc->lmc_miireg16 |= led;
67 lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
71 lmc_reset(lmc_softc_t * const sc)
73 sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
74 lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
76 sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
77 lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
80 * make some of the GPIO pins be outputs
82 lmc_gpio_mkoutput(sc, LMC_GEP_DP | LMC_GEP_RESET);
85 * drive DP and RESET low to force configuration. This also forces
86 * the transmitter clock to be internal, but we expect to reset
89 sc->lmc_gpio &= ~(LMC_GEP_DP | LMC_GEP_RESET);
90 LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
93 * hold for more than 10 microseconds
98 * stop driving Xilinx-related signals
100 lmc_gpio_mkinput(sc, LMC_GEP_DP | LMC_GEP_RESET);
103 * busy wait for the chip to reset
105 while ((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_DP) == 0)
109 * Call media specific init routine
111 sc->lmc_media->init(sc);
115 lmc_dec_reset(lmc_softc_t * const sc)
124 * disable all interrupts
126 sc->lmc_intrmask = 0;
127 LMC_CSR_WRITE(sc, csr_intr, sc->lmc_intrmask);
130 * we are, obviously, down.
133 sc->lmc_flags &= ~(LMC_IFUP | LMC_MODEMOK);
135 DP(("lmc_dec_reset\n"));
139 * Reset the chip with a software reset command.
140 * Wait 10 microseconds (actually 50 PCI cycles but at
141 * 33MHz that comes to two microseconds but wait a
142 * bit longer anyways)
144 LMC_CSR_WRITE(sc, csr_busmode, TULIP_BUSMODE_SWRESET);
146 sc->lmc_cmdmode = LMC_CSR_READ(sc, csr_command);
150 * no ethernet address in frames we write
151 * disable padding (txdesc, padding disable)
152 * ignore runt frames (rdes0 bit 15)
153 * no receiver watchdog or transmitter jabber timer
154 * (csr15 bit 0,14 == 1)
155 * if using 16-bit CRC, turn off CRC (trans desc, crc disable)
158 #ifndef TULIP_CMD_RECEIVEALL
159 #define TULIP_CMD_RECEIVEALL 0x40000000L
162 sc->lmc_cmdmode |= ( TULIP_CMD_PROMISCUOUS
163 | TULIP_CMD_FULLDUPLEX
164 | TULIP_CMD_PASSBADPKT
165 | TULIP_CMD_NOHEARTBEAT
166 | TULIP_CMD_PORTSELECT
167 | TULIP_CMD_RECEIVEALL
168 | TULIP_CMD_MUSTBEONE
170 sc->lmc_cmdmode &= ~( TULIP_CMD_OPERMODE
171 | TULIP_CMD_THRESHOLDCTL
173 | TULIP_CMD_TXTHRSHLDCTL
176 LMC_CSR_WRITE(sc, csr_command, sc->lmc_cmdmode);
179 * disable receiver watchdog and transmit jabber
181 val = LMC_CSR_READ(sc, csr_sia_general);
182 val |= (TULIP_WATCHDOG_TXDISABLE | TULIP_WATCHDOG_RXDISABLE);
183 LMC_CSR_WRITE(sc, csr_sia_general, val);
186 * turn off those LEDs...
188 sc->lmc_miireg16 |= LMC_MII16_LED_ALL;
189 lmc_led_on(sc, LMC_MII16_LED0);
193 * reprogram the tx desc, rx desc, and PCI bus options
195 LMC_CSR_WRITE(sc, csr_txlist,
196 LMC_KVATOPHYS(sc, &sc->lmc_txinfo.ri_first[0]));
197 LMC_CSR_WRITE(sc, csr_rxlist,
198 LMC_KVATOPHYS(sc, &sc->lmc_rxinfo.ri_first[0]));
199 LMC_CSR_WRITE(sc, csr_busmode,
200 (1 << (LMC_BURSTSIZE(sc->lmc_unit) + 8))
201 |TULIP_BUSMODE_CACHE_ALIGN8
202 |TULIP_BUSMODE_READMULTIPLE
203 |(BYTE_ORDER != LITTLE_ENDIAN ? TULIP_BUSMODE_BIGENDIAN : 0));
205 sc->lmc_txq.ifq_maxlen = LMC_TXDESCS;
208 * Free all the mbufs that were on the transmit ring.
213 _IF_DEQUEUE(&sc->lmc_txq, m);
220 * reset descriptor state and reclaim all descriptors.
222 ri = &sc->lmc_txinfo;
223 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
224 ri->ri_free = ri->ri_max;
225 for (di = ri->ri_first; di < ri->ri_last; di++)
229 * We need to collect all the mbufs were on the
230 * receive ring before we reinit it either to put
231 * them back on or to know if we have to allocate
234 ri = &sc->lmc_rxinfo;
235 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
236 ri->ri_free = ri->ri_max;
237 for (di = ri->ri_first; di < ri->ri_last; di++) {
239 di->d_length1 = 0; di->d_addr1 = 0;
240 di->d_length2 = 0; di->d_addr2 = 0;
244 _IF_DEQUEUE(&sc->lmc_rxq, m);
253 lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base,
256 sc->lmc_csrs.csr_busmode = csr_base + 0 * csr_size;
257 sc->lmc_csrs.csr_txpoll = csr_base + 1 * csr_size;
258 sc->lmc_csrs.csr_rxpoll = csr_base + 2 * csr_size;
259 sc->lmc_csrs.csr_rxlist = csr_base + 3 * csr_size;
260 sc->lmc_csrs.csr_txlist = csr_base + 4 * csr_size;
261 sc->lmc_csrs.csr_status = csr_base + 5 * csr_size;
262 sc->lmc_csrs.csr_command = csr_base + 6 * csr_size;
263 sc->lmc_csrs.csr_intr = csr_base + 7 * csr_size;
264 sc->lmc_csrs.csr_missed_frames = csr_base + 8 * csr_size;
265 sc->lmc_csrs.csr_9 = csr_base + 9 * csr_size;
266 sc->lmc_csrs.csr_10 = csr_base + 10 * csr_size;
267 sc->lmc_csrs.csr_11 = csr_base + 11 * csr_size;
268 sc->lmc_csrs.csr_12 = csr_base + 12 * csr_size;
269 sc->lmc_csrs.csr_13 = csr_base + 13 * csr_size;
270 sc->lmc_csrs.csr_14 = csr_base + 14 * csr_size;
271 sc->lmc_csrs.csr_15 = csr_base + 15 * csr_size;