2 * Copyright (c) 1994-1997 Matt Thomas (matt@3am-software.com)
3 * Copyright (c) LAN Media Corporation 1998, 1999.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the author may not be used to endorse or promote products
12 * derived from this software without specific prior written permission
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $Id: if_lmcioctl.h,v 1.9 1999/02/18 10:30:18 explorer Exp $
30 * IOCTLs for the sane world.
32 #define LMCIOCGINFO _IOW('i', 240, struct ifreq)
33 #define LMCIOCSINFO _IOWR('i', 241, struct ifreq)
46 * Common structure passed to the ioctl code.
50 u_int32_t clock_source; /* HSSI, SSI */
51 u_int32_t clock_rate; /* SSI */
53 u_int32_t cable_length; /* DS3 */
54 u_int32_t scrambler_onoff; /* DS3 */
55 u_int32_t cable_type; /* SSI */
56 u_int32_t keepalive_onoff; /* protocol */
57 u_int32_t ticks; /* ticks/sec */
61 u_int32_t circuit_type; /* T1 or E1 circuit */
64 #define LMC_CTL_CARDTYPE_LMC5200 0 /* HSSI */
65 #define LMC_CTL_CARDTYPE_LMC5245 1 /* DS3 */
66 #define LMC_CTL_CARDTYPE_LMC1000 2 /* SSI, E1, etc */
67 #define LMC_CTL_CARDTYPE_LMC1200 3 /* T1 */
69 #define LMC_CTL_OFF 0 /* generic OFF value */
70 #define LMC_CTL_ON 1 /* generic ON value */
72 #define LMC_CTL_CLOCK_SOURCE_EXT 0 /* clock off line */
73 #define LMC_CTL_CLOCK_SOURCE_INT 1 /* internal clock */
75 #define LMC_CTL_CRC_LENGTH_16 16
76 #define LMC_CTL_CRC_LENGTH_32 32
77 #define LMC_CTL_CRC_BYTESIZE_2 2
78 #define LMC_CTL_CRC_BYTESIZE_4 4
80 #define LMC_CTL_CABLE_LENGTH_LT_100FT 0 /* DS3 cable < 100 feet */
81 #define LMC_CTL_CABLE_LENGTH_GT_100FT 1 /* DS3 cable >= 100 feet */
83 #define LMC_CTL_CIRCUIT_TYPE_E1 0
84 #define LMC_CTL_CIRCUIT_TYPE_T1 1
87 * These are not in the least IOCTL related, but I want them common.
90 * assignments for the GPIO register on the DEC chip (common)
92 #define LMC_GEP_INIT 0x01 /* 0: */
93 #define LMC_GEP_RESET 0x02 /* 1: */
94 #define LMC_GEP_LOAD 0x10 /* 4: */
95 #define LMC_GEP_DP 0x20 /* 5: */
96 #define LMC_GEP_SERIAL 0x40 /* 6: serial out */
97 #define LMC_GEP_SERIALCLK 0x80 /* 7: serial clock */
100 * HSSI GPIO assignments
102 #define LMC_GEP_HSSI_ST 0x04 /* 2: receive timing sense (deprecated) */
103 #define LMC_GEP_HSSI_CLOCK 0x08 /* 3: clock source */
106 * SSI GPIO assignments
108 #define LMC_GEP_SSI_GENERATOR 0x04 /* 2: enable prog freq gen serial i/f */
109 #define LMC_GEP_SSI_TXCLOCK 0x08 /* 3: provide clock on TXCLOCK output */
111 /* Note: 2 pairs of LEDs where swapped by mistake
112 * in Xilinx code for DS3 & DS1 adapters */
113 #define LMC_DS3_LED0 0x0100 /* bit 08 yellow */
114 #define LMC_DS3_LED1 0x0080 /* bit 07 blue */
115 #define LMC_DS3_LED2 0x0400 /* bit 10 green */
116 #define LMC_DS3_LED3 0x0200 /* bit 09 red */
121 #define LMC_MII16_LED0 0x0080
122 #define LMC_MII16_LED1 0x0100
123 #define LMC_MII16_LED2 0x0200
124 #define LMC_MII16_LED3 0x0400 /* Error, and the red one */
125 #define LMC_MII16_LED_ALL 0x0780 /* LED bit mask */
126 #define LMC_MII16_FIFO_RESET 0x0800
129 * definitions for HSSI
131 #define LMC_MII16_HSSI_TA 0x0001
132 #define LMC_MII16_HSSI_CA 0x0002
133 #define LMC_MII16_HSSI_LA 0x0004
134 #define LMC_MII16_HSSI_LB 0x0008
135 #define LMC_MII16_HSSI_LC 0x0010
136 #define LMC_MII16_HSSI_TM 0x0020
137 #define LMC_MII16_HSSI_CRC 0x0040
140 * assignments for the MII register 16 (DS3)
142 #define LMC_MII16_DS3_ZERO 0x0001
143 #define LMC_MII16_DS3_TRLBK 0x0002
144 #define LMC_MII16_DS3_LNLBK 0x0004
145 #define LMC_MII16_DS3_RAIS 0x0008
146 #define LMC_MII16_DS3_TAIS 0x0010
147 #define LMC_MII16_DS3_BIST 0x0020
148 #define LMC_MII16_DS3_DLOS 0x0040
149 #define LMC_MII16_DS3_CRC 0x1000
150 #define LMC_MII16_DS3_SCRAM 0x2000
155 #define LMC_MII16_SSI_DTR 0x0001 /* DTR output RW */
156 #define LMC_MII16_SSI_DSR 0x0002 /* DSR input RO */
157 #define LMC_MII16_SSI_RTS 0x0004 /* RTS output RW */
158 #define LMC_MII16_SSI_CTS 0x0008 /* CTS input RO */
159 #define LMC_MII16_SSI_DCD 0x0010 /* DCD input RO */
160 #define LMC_MII16_SSI_RI 0x0020 /* RI input RO */
161 #define LMC_MII16_SSI_CRC 0x0040 /* CRC select */
164 * bits 0x0080 through 0x0800 are generic, and described
165 * above with LMC_MII16_LED[0123] _LED_ALL, and _FIFO_RESET
167 #define LMC_MII16_SSI_LL 0x1000 /* LL output RW */
168 #define LMC_MII16_SSI_RL 0x2000 /* RL output RW */
169 #define LMC_MII16_SSI_TM 0x4000 /* TM input RO */
170 #define LMC_MII16_SSI_LOOP 0x8000 /* loopback enable RW */
173 * Some of the MII16 bits are mirrored in the MII17 register as well,
174 * but let's keep thing separate for now, and get only the cable from
177 #define LMC_MII17_SSI_CABLE_MASK 0x0038 /* mask to extract the cable type */
178 #define LMC_MII17_SSI_CABLE_SHIFT 3 /* shift to extract the cable type */
181 * framer register 0 and 7 (7 is latched and reset on read)
183 #define LMC_FRAMER_REG0_DLOS 0x80 /* digital loss of service */
184 #define LMC_FRAMER_REG0_OOFS 0x40 /* out of frame sync */
185 #define LMC_FRAMER_REG0_AIS 0x20 /* alarm indication signal */
186 #define LMC_FRAMER_REG0_CIS 0x10 /* channel idle */
187 #define LMC_FRAMER_REG0_LOC 0x08 /* loss of clock */
189 #define LMC_CARDTYPE_UNKNOWN -1
190 #define LMC_CARDTYPE_HSSI 1 /* probed card is a HSSI card */
191 #define LMC_CARDTYPE_DS3 2 /* probed card is a DS3 card */
192 #define LMC_CARDTYPE_SSI 3 /* probed card is a SSI card */
193 #define LMC_CARDTYPE_T1 4 /* probed card is a T1 card */
196 * framer register 0 and 7 (7 is latched and reset on read)
198 #define LMC_FRAMER_REG0_DLOS 0x80 /* digital loss of service */
199 #define LMC_FRAMER_REG0_OOFS 0x40 /* out of frame sync */
200 #define LMC_FRAMER_REG0_AIS 0x20 /* alarm indication signal */
201 #define LMC_FRAMER_REG0_CIS 0x10 /* channel idle */
202 #define LMC_FRAMER_REG0_LOC 0x08 /* loss of clock */
203 #define LMC_MII16_T1_UNUSED1 0x0003
204 #define LMC_MII16_T1_XOE 0x0004
205 #define LMC_MII16_T1_RST 0x0008 /* T1 chip reset - RW */
206 #define LMC_MII16_T1_Z 0x0010 /* output impedance T1=1, E1=0 output - RW */
207 #define LMC_MII16_T1_INTR 0x0020 /* interrupt from 8370 - RO */
208 #define LMC_MII16_T1_ONESEC 0x0040 /* one second square wave - ro */
209 #define LMC_MII16_T1_LED0 0x0100
210 #define LMC_MII16_T1_LED1 0x0080
211 #define LMC_MII16_T1_LED2 0x0400
212 #define LMC_MII16_T1_LED3 0x0200
213 #define LMC_MII16_T1_FIFO_RESET 0x0800
215 #define LMC_MII16_T1_CRC 0x1000 /* CRC select - RW */
216 #define LMC_MII16_T1_UNUSED2 0xe000
218 #define T1FRAMER_ALARM1_STATUS 0x47
219 #define T1FRAMER_ALARM2_STATUS 0x48
220 #define T1FRAMER_FERR_LSB 0x50
221 #define T1FRAMER_FERR_MSB 0x51 /* framing bit error counter */
222 #define T1FRAMER_LCV_LSB 0x54
223 #define T1FRAMER_LCV_MSB 0x55 /* line code violation counter */
224 #define T1FRAMER_AERR 0x5A
226 /* mask for the above AERR register */
227 #define T1FRAMER_LOF_MASK (0x0f0) /* receive loss of frame */
228 #define T1FRAMER_COFA_MASK (0x0c0) /* change of frame alignment */
229 #define T1FRAMER_SEF_MASK (0x03) /* severely errored frame */
231 /* 8370 framer register ALM1 (0x47) values
232 * used to determine link status
235 #define T1F_SIGFRZ 0x01 /* signaling freeze */
236 #define T1F_RLOF 0x02 /* receive loss of frame alignment */
237 #define T1F_RLOS 0x04 /* receive loss of signal */
238 #define T1F_RALOS 0x08 /* receive analog loss of signal or RCKI loss of clock */
239 #define T1F_RAIS 0x10 /* receive alarm indication signal */
240 #define T1F_UNUSED 0x20
241 #define T1F_RYEL 0x40 /* receive yellow alarm */
242 #define T1F_RMYEL 0x80 /* receive multiframe yellow alarm */
244 /* ------------------ end T1 defs ------------------- */
246 #define LMC_MII_LedMask 0x0780
247 #define LMC_MII_LedBitPos 7
250 * NetBSD uses _KERNEL, FreeBSD uses KERNEL.
252 #if defined(_KERNEL) || defined(KERNEL) || defined(__KERNEL__)
254 * media independent methods to check on media status, link, light LEDs,
258 void (* init)(lmc_softc_t * const);
259 void (* defaults)(lmc_softc_t * const);
260 void (* set_status)(lmc_softc_t * const, lmc_ctl_t *);
261 void (* set_clock_source)(lmc_softc_t * const, int);
262 void (* set_speed)(lmc_softc_t * const, lmc_ctl_t *);
263 void (* set_cable_length)(lmc_softc_t * const, int);
264 void (* set_scrambler)(lmc_softc_t * const, int);
265 int (* get_link_status)(lmc_softc_t * const);
266 void (* set_link_status)(lmc_softc_t * const, int);
267 void (* set_crc_length)(lmc_softc_t * const, int);
268 void (* set_circuit_type)(lmc_softc_t * const, int);
271 static unsigned lmc_mii_readreg(lmc_softc_t * const sc, unsigned
272 devaddr, unsigned regno);
273 static void lmc_mii_writereg(lmc_softc_t * const sc, unsigned devaddr,
274 unsigned regno, unsigned data);