2 * Copyright (c) 1994-1997 Matt Thomas (matt@3am-software.com)
3 * Copyright (c) LAN Media Corporation 1998, 1999.
4 * Copyright (c) 2000 Stephen Kiernan (sk-ports@vegamuse.org)
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * From NetBSD: if_devar.h,v 1.21 1997/10/16 22:02:32 matt Exp
28 * $Id: if_lmcvar.h,v 1.6 1999/01/12 14:16:58 explorer Exp $
31 #if !defined(_DEV_LMC_IF_LMCVAR_H)
32 #define _DEV_LMC_IF_LMCVAR_H
35 #define PPP_HEADER_LEN 4
38 #if !defined(PCI_VENDOR_LMC)
39 #define PCI_VENDOR_LMC 0x1376
41 #if !defined(PCI_PRODUCT_LMC_HSSI)
42 #define PCI_PRODUCT_LMC_HSSI 0x0003
44 #if !defined(PCI_PRODUCT_LMC_DS3)
45 #define PCI_PRODUCT_LMC_DS3 0x0004
47 #if !defined(PCI_PRODUCT_LMC_SSI)
48 #define PCI_PRODUCT_LMC_SSI 0x0005
50 #if !defined(PCI_PRODUCT_LMC_T1)
51 #define PCI_PRODUCT_LMC_T1 0x0006
55 #define LMC_EISA_CSRSIZE 16
56 #define LMC_EISA_CSROFFSET 0
57 #define LMC_PCI_CSRSIZE 8
58 #define LMC_PCI_CSROFFSET 0
60 typedef u_int16_t lmc_csrptr_t;
62 #define LMC_CSR_READ(sc, csr) (inl((sc)->lmc_csrs.csr))
63 #define LMC_CSR_WRITE(sc, csr, val) outl((sc)->lmc_csrs.csr, val)
65 #define LMC_CSR_READBYTE(sc, csr) (inb((sc)->lmc_csrs.csr))
66 #define LMC_CSR_WRITEBYTE(sc, csr, val) outb((sc)->lmc_csrs.csr, val)
68 #else /* LMC_IOMAPPED */
70 #define LMC_PCI_CSRSIZE 8
71 #define LMC_PCI_CSROFFSET 0
73 typedef volatile u_int32_t *lmc_csrptr_t;
76 * macros to read and write CSRs. Note that the "0 +" in
77 * READ_CSR is to prevent the macro from being an lvalue
78 * and WRITE_CSR shouldn't be assigned from.
80 #define LMC_CSR_READ(sc, csr) (0 + *(sc)->lmc_csrs.csr)
81 #define LMC_CSR_WRITE(sc, csr, val) ((void)(*(sc)->lmc_csrs.csr = (val)))
83 #endif /* LMC_IOMAPPED */
86 * This structure contains "pointers" for the registers on
87 * the various 21x4x chips. CSR0 through CSR8 are common
88 * to all chips. After that, it gets messy...
91 lmc_csrptr_t csr_busmode; /* CSR0 */
92 lmc_csrptr_t csr_txpoll; /* CSR1 */
93 lmc_csrptr_t csr_rxpoll; /* CSR2 */
94 lmc_csrptr_t csr_rxlist; /* CSR3 */
95 lmc_csrptr_t csr_txlist; /* CSR4 */
96 lmc_csrptr_t csr_status; /* CSR5 */
97 lmc_csrptr_t csr_command; /* CSR6 */
98 lmc_csrptr_t csr_intr; /* CSR7 */
99 lmc_csrptr_t csr_missed_frames; /* CSR8 */
100 lmc_csrptr_t csr_9; /* CSR9 */
101 lmc_csrptr_t csr_10; /* CSR10 */
102 lmc_csrptr_t csr_11; /* CSR11 */
103 lmc_csrptr_t csr_12; /* CSR12 */
104 lmc_csrptr_t csr_13; /* CSR13 */
105 lmc_csrptr_t csr_14; /* CSR14 */
106 lmc_csrptr_t csr_15; /* CSR15 */
109 #define csr_enetrom csr_9 /* 21040 */
110 #define csr_reserved csr_10 /* 21040 */
111 #define csr_full_duplex csr_11 /* 21040 */
112 #define csr_bootrom csr_10 /* 21041/21140A/?? */
113 #define csr_gp csr_12 /* 21140* */
114 #define csr_watchdog csr_15 /* 21140* */
115 #define csr_gp_timer csr_11 /* 21041/21140* */
116 #define csr_srom_mii csr_9 /* 21041/21140* */
117 #define csr_sia_status csr_12 /* 2104x */
118 #define csr_sia_connectivity csr_13 /* 2104x */
119 #define csr_sia_tx_rx csr_14 /* 2104x */
120 #define csr_sia_general csr_15 /* 2104x */
123 * While 21x4x allows chaining of its descriptors, this driver
124 * doesn't take advantage of it. We keep the descriptors in a
125 * traditional FIFO ring.
128 tulip_desc_t *ri_first; /* first entry in ring */
129 tulip_desc_t *ri_last; /* one after last entry */
130 tulip_desc_t *ri_nextin; /* next to processed by host */
131 tulip_desc_t *ri_nextout; /* next to processed by adapter */
137 * The 21040 has a stupid restriction in that the receive
138 * buffers must be longword aligned. But since Ethernet
139 * headers are not a multiple of longwords in size this forces
140 * the data to non-longword aligned. Since IP requires the
141 * data to be longword aligned, we need to copy it after it has
142 * been DMA'ed in our memory.
144 * Since we have to copy it anyways, we might as well as allocate
145 * dedicated receive space for the input. This allows to use a
146 * small receive buffer size and more ring entries to be able to
147 * better keep with a flood of tiny Ethernet packets.
149 * The receive space MUST ALWAYS be a multiple of the page size.
150 * And the number of receive descriptors multiplied by the size
151 * of the receive buffers must equal the recevive space. This
152 * is so that we can manipulate the page tables so that even if a
153 * packet wraps around the end of the receive space, we can
154 * treat it as virtually contiguous.
156 * The above used to be true (the stupid restriction is still true)
157 * but we gone to directly DMA'ing into MBUFs (unless it's on an
158 * architecture which can't handle unaligned accesses) because with
159 * 100Mb/s cards the copying is just too much of a hit.
162 #define LMC_RXDESCS 48
163 #define LMC_TXDESCS 128
164 #define LMC_RXQ_TARGET 32
165 #if LMC_RXQ_TARGET >= LMC_RXDESCS
166 #error LMC_RXQ_TARGET must be less than LMC_RXDESCS
169 #define LMC_RX_BUFLEN ((MCLBYTES < 2048 ? MCLBYTES : 2048) - 16)
172 * The various controllers support. Technically the DE425 is just
173 * a 21040 on EISA. But since it remarkably difference from normal
174 * 21040s, we give it its own chip id.
178 LMC_21140, LMC_21140A,
182 #define LMC_BIT(b) (1L << ((int)(b)))
184 typedef struct lmc_xinfo {
185 u_int32_t Magic0; /* BEEFCAFE */
187 u_int32_t PciCardType;
188 u_int32_t PciSlotNumber; /* PCI slot number */
190 u_int16_t DriverMajorVersion;
191 u_int16_t DriverMinorVersion;
192 u_int16_t DriverSubVersion;
194 u_int16_t XilinxRevisionNumber;
195 u_int16_t MaxFrameSize;
197 u_int16_t t1_alarm1_status;
198 u_int16_t t1_alarm2_status;
203 u_int32_t Magic1; /* DEADBEEF */
209 * Transmit Statistics
211 u_int32_t dot3StatsSingleCollisionFrames;
212 u_int32_t dot3StatsMultipleCollisionFrames;
213 u_int32_t dot3StatsSQETestErrors;
214 u_int32_t dot3StatsDeferredTransmissions;
215 u_int32_t dot3StatsLateCollisions;
216 u_int32_t dot3StatsExcessiveCollisions;
217 u_int32_t dot3StatsCarrierSenseErrors;
218 u_int32_t dot3StatsInternalMacTransmitErrors;
219 u_int32_t dot3StatsInternalTransmitUnderflows; /* not in rfc1650! */
220 u_int32_t dot3StatsInternalTransmitBabbles; /* not in rfc1650! */
224 u_int32_t dot3StatsMissedFrames; /* not in rfc1650! */
225 u_int32_t dot3StatsAlignmentErrors;
226 u_int32_t dot3StatsFCSErrors;
227 u_int32_t dot3StatsFrameTooLongs;
228 u_int32_t dot3StatsInternalMacReceiveErrors;
232 * Now to important stuff. This is softc structure (where does softc
233 * come from??? No idea) for the tulip device.
238 const char *lmc_name;
241 u_int8_t lmc_enaddr[6]; /* yes, a small hack... */
242 lmc_regfile_t lmc_csrs;
243 volatile u_int32_t lmc_txtick;
244 volatile u_int32_t lmc_rxtick;
247 u_int32_t lmc_features; /* static bits indicating features of chip */
248 u_int32_t lmc_intrmask; /* our copy of csr_intr */
249 u_int32_t lmc_cmdmode; /* our copy of csr_cmdmode */
250 u_int32_t lmc_last_system_error : 3; /* last system error (only value is LMC_SYSTEMERROR is also set) */
251 u_int32_t lmc_system_errors; /* number of system errors encountered */
252 u_int32_t lmc_statusbits; /* status bits from CSR5 that may need to be printed */
254 u_int8_t lmc_revinfo; /* revision of chip */
255 u_int8_t lmc_cardtype; /* LMC_CARDTYPE_HSSI or ..._DS3 */
256 u_int32_t lmc_gpio_io; /* state of in/out settings */
257 u_int32_t lmc_gpio; /* state of outputs */
260 lmc_chipid_t lmc_chipid; /* type of chip we are using */
261 u_int32_t lmc_miireg16;
262 struct ifqueue lmc_txq;
263 struct ifqueue lmc_rxq;
264 lmc_dot3_stats_t lmc_dot3stats;
265 lmc_ringinfo_t lmc_rxinfo;
266 lmc_ringinfo_t lmc_txinfo;
267 u_int8_t lmc_rombuf[128];
268 lmc_media_t *lmc_media;
272 u_int8_t lmc_pci_busno; /* needed for multiport boards */
273 u_int8_t lmc_pci_devno; /* needed for multiport boards */
274 tulip_desc_t *lmc_rxdescs;
275 tulip_desc_t *lmc_txdescs;
277 u_int32_t lmc_crcSize;
278 char lmc_timing; /* for HSSI and SSI */
279 u_int16_t t1_alarm1_status;
280 u_int16_t t1_alarm2_status;
283 char lmc_nodename[NG_NODELEN + 1];
287 hook_p lmc_debug_hook;
288 struct ifqueue lmc_xmitq_hipri;
289 struct ifqueue lmc_xmitq;
290 struct callout_handle lmc_handle;
293 u_long lmc_inbytes, lmc_outbytes; /* stats */
294 u_long lmc_lastinbytes, lmc_lastoutbytes; /* a second ago */
295 u_long lmc_inrate, lmc_outrate; /* highest rate seen */
296 u_long lmc_inlast; /* last input N secs ago */
297 u_long lmc_out_deficit; /* output since last input */
298 u_long lmc_oerrors, lmc_ierrors;
299 u_long lmc_opackets, lmc_ipackets;
303 #define LMC_DOG_HOLDOFF 6 /* dog holds off for 6 secs */
304 #define LMC_QUITE_A_WHILE 300 /* 5 MINUTES */
305 #define LMC_LOTS_OF_PACKETS 100
307 /* Node type name and type cookie */
308 #define NG_LMC_NODE_TYPE "lmc"
309 #define NG_LMC_COOKIE 956095698
312 #define NG_LMC_HOOK_DEBUG "debug"
313 #define NG_LMC_HOOK_CONTROL "control"
314 #define NG_LMC_HOOK_RAW "rawdata"
316 /* Netgraph commands understood by this node type */
325 #define LMC_IFUP 0x00000001
326 #define LMC_00000002 0x00000002
327 #define LMC_00000004 0x00000004
328 #define LMC_00000008 0x00000008
329 #define LMC_00000010 0x00000010
330 #define LMC_MODEMOK 0x00000020
331 #define LMC_00000040 0x00000040
332 #define LMC_00000080 0x00000080
333 #define LMC_RXACT 0x00000100
334 #define LMC_INRESET 0x00000200
335 #define LMC_NEEDRESET 0x00000400
336 #define LMC_00000800 0x00000800
337 #define LMC_00001000 0x00001000
338 #define LMC_00002000 0x00002000
339 #define LMC_WANTTXSTART 0x00004000
340 #define LMC_NEWTXTHRESH 0x00008000
341 #define LMC_NOAUTOSENSE 0x00010000
342 #define LMC_PRINTLINKUP 0x00020000
343 #define LMC_LINKUP 0x00040000
344 #define LMC_RXBUFSLOW 0x00080000
345 #define LMC_NOMESSAGES 0x00100000
346 #define LMC_SYSTEMERROR 0x00200000
347 #define LMC_TIMEOUTPENDING 0x00400000
348 #define LMC_00800000 0x00800000
349 #define LMC_01000000 0x01000000
350 #define LMC_02000000 0x02000000
351 #define LMC_RXIGNORE 0x04000000
352 #define LMC_08000000 0x08000000
353 #define LMC_10000000 0x10000000
354 #define LMC_20000000 0x20000000
355 #define LMC_40000000 0x40000000
356 #define LMC_80000000 0x80000000
361 #define LMC_HAVE_GPR 0x00000001 /* have gp register (140[A]) */
362 #define LMC_HAVE_RXBADOVRFLW 0x00000002 /* RX corrupts on overflow */
363 #define LMC_HAVE_POWERMGMT 0x00000004 /* Snooze/sleep modes */
364 #define LMC_HAVE_MII 0x00000008 /* Some medium on MII */
365 #define LMC_HAVE_SIANWAY 0x00000010 /* SIA does NWAY */
366 #define LMC_HAVE_DUALSENSE 0x00000020 /* SIA senses both AUI & TP */
367 #define LMC_HAVE_SIAGP 0x00000040 /* SIA has a GP port */
368 #define LMC_HAVE_BROKEN_HASH 0x00000080 /* Broken Multicast Hash */
369 #define LMC_HAVE_ISVSROM 0x00000100 /* uses ISV SROM Format */
370 #define LMC_HAVE_BASEROM 0x00000200 /* Board ROM can be cloned */
371 #define LMC_HAVE_SLAVEDROM 0x00000400 /* Board ROM cloned */
372 #define LMC_HAVE_SLAVEDINTR 0x00000800 /* Board slaved interrupt */
373 #define LMC_HAVE_SHAREDINTR 0x00001000 /* Board shares interrupts */
374 #define LMC_HAVE_OKROM 0x00002000 /* ROM was recognized */
375 #define LMC_HAVE_NOMEDIA 0x00004000 /* did not detect any media */
376 #define LMC_HAVE_STOREFWD 0x00008000 /* have CMD_STOREFWD */
377 #define LMC_HAVE_SIA100 0x00010000 /* has LS100 in SIA status */
379 static const char * const lmc_system_errors[] = {
390 static const char * const lmc_status_bits[] = {
392 "transmit process stopped",
394 "transmit jabber timeout",
397 "transmit underflow",
401 "receive process stopped",
402 "receive watchdog timeout",
412 * This driver supports a maximum of 32 tulip boards.
413 * This should be enough for the forseeable future.
415 #define LMC_MAX_DEVICES 32
417 typedef void ifnet_ret_t;
418 typedef int ioctl_cmd_t;
419 static lmc_softc_t *tulips[LMC_MAX_DEVICES];
420 #define LMC_IFP_TO_SOFTC(ifp) ((lmc_softc_t *)((ifp)->if_softc))
421 #define lmc_intrfunc_t void
422 #define LMC_VOID_INTRFUNC
423 #define IFF_NOTRAILERS 0
424 #define CLBYTES PAGE_SIZE
425 #define LMC_EADDR_FMT "%6D"
426 #define LMC_EADDR_ARGS(addr) addr, ":"
427 #define LMC_UNIT_TO_SOFTC(unit) (tulips[unit])
428 #define LMC_BURSTSIZE(unit) pci_max_burst_len
429 #define loudprintf if (bootverbose) printf
431 #ifndef LMC_PRINTF_FMT
432 #define LMC_PRINTF_FMT "%s%d"
434 #ifndef LMC_PRINTF_ARGS
435 #define LMC_PRINTF_ARGS sc->lmc_name, sc->lmc_unit
438 #ifndef LMC_BURSTSIZE
439 #define LMC_BURSTSIZE(unit) 3
442 #if !defined(lmc_intrfunc_t)
443 #define lmc_intrfunc_t int
446 #if !defined(LMC_KVATOPHYS)
447 #define LMC_KVATOPHYS(sc, va) vtophys(va)
451 #define LMC_RAISESPL() splimp()
453 #ifndef LMC_RAISESOFTSPL
454 #define LMC_RAISESOFTSPL() splnet()
456 #ifndef TULUP_RESTORESPL
457 #define LMC_RESTORESPL(s) splx(s)
461 * While I think FreeBSD's 2.2 change to the bpf is a nice simplification,
462 * it does add yet more conditional code to this driver. Sigh.
464 #if !defined(LMC_BPF_MTAP) && NBPFILTER > 0
465 #define LMC_BPF_MTAP(sc, m) bpf_mtap((sc)->lmc_bpf, m)
466 #define LMC_BPF_TAP(sc, p, l) bpf_tap((sc)->lmc_bpf, p, l)
467 #define LMC_BPF_ATTACH(sc) bpfattach(&(sc)->lmc_bpf, &(sc)->lmc_sppp.pp_if, DLT_PPP, PPP_HEADER_LEN)
471 * However, this change to FreeBSD I am much less enamored with.
473 #if !defined(LMC_EADDR_FMT)
474 #define LMC_EADDR_FMT "%s"
475 #define LMC_EADDR_ARGS(addr) ether_sprintf(addr)
478 #define LMC_CRC32_POLY 0xEDB88320UL /* CRC-32 Poly -- Little Endian */
479 #define LMC_MAX_TXSEG 30
481 #define LMC_ADDREQUAL(a1, a2) \
482 (((u_int16_t *)a1)[0] == ((u_int16_t *)a2)[0] \
483 && ((u_int16_t *)a1)[1] == ((u_int16_t *)a2)[1] \
484 && ((u_int16_t *)a1)[2] == ((u_int16_t *)a2)[2])
485 #define LMC_ADDRBRDCST(a1) \
486 (((u_int16_t *)a1)[0] == 0xFFFFU \
487 && ((u_int16_t *)a1)[1] == 0xFFFFU \
488 && ((u_int16_t *)a1)[2] == 0xFFFFU)
490 typedef int lmc_spl_t;
492 #endif /* !defined(_DEV_LMC_IF_LMCVAR_H) */