2 * Copyright (c) 1994-2000
3 * Paul Richards. All rights reserved.
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6 * modification, are permitted provided that the following conditions
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18 * THIS SOFTWARE IS PROVIDED BY PAUL RICHARDS ``AS IS'' AND
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25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Am7990, Local Area Network Controller for Ethernet (LANCE)
36 * The LANCE has four Control and Status Registers(CSRs) which are accessed
37 * through two bus addressable ports, the address port (RAP) and the data
55 /* Control and Status Register Masks */
79 * Bits 3-15 are reserved.
87 /* ISA Bus Configuration Registers */
88 #define MSRDA 0x0000 /* ISACSR0: Master Mode Read Activity */
89 #define MSWRA 0x0001 /* ISACSR1: Master Mode Write Activity */
90 #define MC 0x0002 /* ISACSR2: Miscellaneous Configuration */
92 #define LED1 0x0005 /* ISACSR5: LED1 Status */
93 #define LED2 0x0006 /* ISACSR6: LED2 Status */
94 #define LED3 0x0007 /* ISACSR7: LED3 Status */
96 #define LED_PSE 0x0080 /* Pulse Stretcher */
97 #define LED_XMTE 0x0010 /* Transmit Status */
98 #define LED_RVPOLE 0x0008 /* Receive Polarity */
99 #define LED_RCVE 0x0004 /* Receive Status */
100 #define LED_JABE 0x0002 /* Jabber */
101 #define LED_COLE 0x0001 /* Collision */
103 /* Initialisation block */
106 u_short mode; /* Mode register */
107 u_char padr[6]; /* Ethernet address */
108 u_char ladrf[8]; /* Logical address filter (multicast) */
109 u_short rdra; /* Low order pointer to receive ring */
110 u_short rlen; /* High order pointer and no. rings */
111 u_short tdra; /* Low order pointer to transmit ring */
112 u_short tlen; /* High order pointer and no rings */
115 /* Initialisation Block Mode Register Masks */
117 #define PROM 0x8000 /* Promiscuous Mode */
118 #define DRCVBC 0x4000 /* Disable Receive Broadcast */
119 #define DRCVPA 0x2000 /* Disable Receive Physical Address */
120 #define DLNKTST 0x1000 /* Disable Link Status */
121 #define DAPC 0x0800 /* Disable Automatic Polarity Correction */
122 #define MENDECL 0x0400 /* MENDEC Loopback Mode */
123 #define LRT 0x0200 /* Low Receive Threshold (T-MAU mode only) */
124 #define TSEL 0x0200 /* Transmit Mode Select (AUI mode only) */
125 #define PORTSEL 0x0180 /* Port Select bits */
126 #define INTL 0x0040 /* Internal Loopback */
127 #define DRTY 0x0020 /* Disable Retry */
128 #define FCOLL 0x0010 /* Force Collision */
129 #define DXMTFCS 0x0008 /* Disable transmit CRC (FCS) */
130 #define LOOP 0x0004 /* Loopback Enabl */
131 #define DTX 0x0002 /* Disable the transmitter */
132 #define DRX 0x0001 /* Disable the receiver */
135 * Message Descriptor Structure
137 * Each transmit or receive descriptor ring entry (RDRE's and TDRE's)
138 * is composed of 4, 16-bit, message descriptors. They contain the following
141 * 1. The address of the actual message data buffer in user (host) memory.
142 * 2. The length of that message buffer.
143 * 3. The status information for that particular buffer. The eight most
144 * significant bits of md1 are collectively termed the STATUS of the
147 * Descriptor md0 contains LADR 0-15, the low order 16 bits of the 24-bit
148 * address of the actual data buffer. Bits 0-7 of descriptor md1 contain
149 * HADR, the high order 8-bits of the 24-bit data buffer address. Bits 8-15
150 * of md1 contain the status flags of the buffer. Descriptor md2 contains the
151 * buffer byte count in bits 0-11 as a two's complement number and must have
152 * 1's written to bits 12-15. For the receive entry md3 has the Message Byte
153 * Count in bits 0-11, this is the length of the received message and is valid
154 * only when ERR is cleared and ENP is set. For the transmit entry it contains
155 * more status information.
166 /* Receive STATUS flags for md1 */
168 #define OWN 0x8000 /* Owner bit, 0=host, 1=Lance */
169 #define MDERR 0x4000 /* Error */
170 #define FRAM 0x2000 /* Framing error error */
171 #define OFLO 0x1000 /* Silo overflow */
172 #define CRC 0x0800 /* CRC error */
173 #define RBUFF 0x0400 /* Buffer error */
174 #define STP 0x0200 /* Start of packet */
175 #define ENP 0x0100 /* End of packet */
176 #define HADR 0x00FF /* High order address bits */
178 /* Receive STATUS flags for md2 */
180 #define BCNT 0x0FFF /* Size of data buffer as 2's comp. no. */
182 /* Receive STATUS flags for md3 */
184 #define MCNT 0x0FFF /* Total size of data for received packet */
186 /* Transmit STATUS flags for md1 */
188 #define ADD_FCS 0x2000 /* Controls generation of FCS */
189 #define MORE 0x1000 /* Indicates more than one retry was needed */
190 #define ONE 0x0800 /* Exactly one retry was needed */
191 #define DEF 0x0400 /* Packet transmit deferred -- channel busy */
194 * Transmit status flags for md2
196 * Same as for receive descriptor.
198 * BCNT 0x0FFF Size of data buffer as 2's complement number.
202 /* Transmit status flags for md3 */
204 #define TBUFF 0x8000 /* Buffer error */
205 #define UFLO 0x4000 /* Silo underflow */
206 #define LCOL 0x1000 /* Late collision */
207 #define LCAR 0x0800 /* Loss of carrier */
208 #define RTRY 0x0400 /* Tried 16 times */
209 #define TDR 0x03FF /* Time domain reflectometry */