2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2007 Marvell Semiconductor, Inc.
5 * Copyright (c) 2007 Sam Leffler, Errno Consulting
6 * Copyright (c) 2008 Weongyo Jeong <weongyo@freebsd.org>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
16 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
17 * redistribution must be conditioned upon including a substantially
18 * similar Disclaimer requirement for further binary redistribution.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
24 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
25 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
26 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
29 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGES.
34 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/malloc.h>
44 #include <sys/firmware.h>
45 #include <sys/socket.h>
47 #include <machine/bus.h>
51 #include <net/if_var.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/ethernet.h>
56 #include <net80211/ieee80211_var.h>
58 #include <dev/malo/if_malo.h>
63 #define _CMD_SETUP(pCmd, _type, _cmd) do { \
64 pCmd = (_type *)&mh->mh_cmdbuf[0]; \
65 memset(pCmd, 0, sizeof(_type)); \
66 pCmd->cmdhdr.cmd = htole16(_cmd); \
67 pCmd->cmdhdr.length = htole16(sizeof(_type)); \
70 static __inline uint32_t
71 malo_hal_read4(struct malo_hal *mh, bus_size_t off)
73 return bus_space_read_4(mh->mh_iot, mh->mh_ioh, off);
77 malo_hal_write4(struct malo_hal *mh, bus_size_t off, uint32_t val)
79 bus_space_write_4(mh->mh_iot, mh->mh_ioh, off, val);
83 malo_hal_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
85 bus_addr_t *paddr = (bus_addr_t*) arg;
87 KASSERT(error == 0, ("error %u on bus_dma callback", error));
88 *paddr = segs->ds_addr;
92 * Setup for communication with the device. We allocate
93 * a command buffer and map it for bus dma use. The pci
94 * device id is used to identify whether the device has
95 * SRAM on it (in which case f/w download must include a
96 * memory controller reset). All bus i/o operations happen
97 * in BAR 1; the driver passes in the tag and handle we need.
100 malo_hal_attach(device_t dev, uint16_t devid,
101 bus_space_handle_t ioh, bus_space_tag_t iot, bus_dma_tag_t tag)
106 mh = malloc(sizeof(struct malo_hal), M_DEVBUF, M_NOWAIT | M_ZERO);
114 snprintf(mh->mh_mtxname, sizeof(mh->mh_mtxname),
115 "%s_hal", device_get_nameunit(dev));
116 mtx_init(&mh->mh_mtx, mh->mh_mtxname, NULL, MTX_DEF);
119 * Allocate the command buffer and map into the address
120 * space of the h/w. We request "coherent" memory which
121 * will be uncached on some architectures.
123 error = bus_dma_tag_create(tag, /* parent */
124 PAGE_SIZE, 0, /* alignment, bounds */
125 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
126 BUS_SPACE_MAXADDR, /* highaddr */
127 NULL, NULL, /* filter, filterarg */
128 MALO_CMDBUF_SIZE, /* maxsize */
130 MALO_CMDBUF_SIZE, /* maxsegsize */
131 BUS_DMA_ALLOCNOW, /* flags */
136 device_printf(dev, "unable to allocate memory for cmd tag, "
137 "error %u\n", error);
141 /* allocate descriptors */
142 error = bus_dmamem_alloc(mh->mh_dmat, (void**) &mh->mh_cmdbuf,
143 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
146 device_printf(dev, "unable to allocate memory for cmd buffer, "
147 "error %u\n", error);
151 error = bus_dmamap_load(mh->mh_dmat, mh->mh_dmamap,
152 mh->mh_cmdbuf, MALO_CMDBUF_SIZE,
153 malo_hal_load_cb, &mh->mh_cmdaddr,
156 device_printf(dev, "unable to load cmd buffer, error %u\n",
164 if (mh->mh_cmdbuf != NULL)
165 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf,
168 bus_dma_tag_destroy(mh->mh_dmat);
175 * Low level firmware cmd block handshake support.
179 malo_hal_send_cmd(struct malo_hal *mh)
183 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap,
184 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
186 malo_hal_write4(mh, MALO_REG_GEN_PTR, mh->mh_cmdaddr);
187 dummy = malo_hal_read4(mh, MALO_REG_INT_CODE);
189 malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS,
190 MALO_H2ARIC_BIT_DOOR_BELL);
194 malo_hal_waitforcmd(struct malo_hal *mh, uint16_t cmd)
196 #define MAX_WAIT_FW_COMPLETE_ITERATIONS 10000
199 for (i = 0; i < MAX_WAIT_FW_COMPLETE_ITERATIONS; i++) {
200 if (mh->mh_cmdbuf[0] == le16toh(cmd))
207 #undef MAX_WAIT_FW_COMPLETE_ITERATIONS
211 malo_hal_execute_cmd(struct malo_hal *mh, unsigned short cmd)
213 MALO_HAL_LOCK_ASSERT(mh);
215 if ((mh->mh_flags & MHF_FWHANG) &&
216 (mh->mh_debug & MALO_HAL_DEBUG_IGNHANG) == 0) {
217 device_printf(mh->mh_dev, "firmware hung, skipping cmd 0x%x\n",
222 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == 0xffffffff) {
223 device_printf(mh->mh_dev, "%s: device not present!\n",
228 malo_hal_send_cmd(mh);
229 if (!malo_hal_waitforcmd(mh, cmd | 0x8000)) {
230 device_printf(mh->mh_dev,
231 "timeout waiting for f/w cmd 0x%x\n", cmd);
232 mh->mh_flags |= MHF_FWHANG;
236 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap,
237 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
243 malo_hal_get_cal_table(struct malo_hal *mh, uint8_t annex, uint8_t index)
245 struct malo_cmd_caltable *cmd;
248 MALO_HAL_LOCK_ASSERT(mh);
250 _CMD_SETUP(cmd, struct malo_cmd_caltable, MALO_HOSTCMD_GET_CALTABLE);
254 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_GET_CALTABLE);
255 if (ret == 0 && cmd->caltbl[0] != annex && annex != 0 && annex != 255)
261 malo_hal_get_pwrcal_table(struct malo_hal *mh, struct malo_hal_caldata *cal)
267 /* NB: we hold the lock so it's ok to use cmdbuf */
268 data = ((const struct malo_cmd_caltable *) mh->mh_cmdbuf)->caltbl;
269 if (malo_hal_get_cal_table(mh, 33, 0) == 0) {
270 len = (data[2] | (data[3] << 8)) - 12;
271 /* XXX validate len */
272 memcpy(cal->pt_ratetable_20m, &data[12], len);
274 mh->mh_flags |= MHF_CALDATA;
281 * Reset internal state after a firmware download.
284 malo_hal_resetstate(struct malo_hal *mh)
287 * Fetch cal data for later use.
288 * XXX may want to fetch other stuff too.
290 if ((mh->mh_flags & MHF_CALDATA) == 0)
291 malo_hal_get_pwrcal_table(mh, &mh->mh_caldata);
296 malo_hal_fw_reset(struct malo_hal *mh)
299 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == 0xffffffff) {
300 device_printf(mh->mh_dev, "%s: device not present!\n",
305 malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS, MALO_ISR_RESET);
306 mh->mh_flags &= ~MHF_FWHANG;
310 malo_hal_trigger_pcicmd(struct malo_hal *mh)
314 bus_dmamap_sync(mh->mh_dmat, mh->mh_dmamap, BUS_DMASYNC_PREWRITE);
316 malo_hal_write4(mh, MALO_REG_GEN_PTR, mh->mh_cmdaddr);
317 dummy = malo_hal_read4(mh, MALO_REG_INT_CODE);
319 malo_hal_write4(mh, MALO_REG_INT_CODE, 0x00);
320 dummy = malo_hal_read4(mh, MALO_REG_INT_CODE);
322 malo_hal_write4(mh, MALO_REG_H2A_INTERRUPT_EVENTS,
323 MALO_H2ARIC_BIT_DOOR_BELL);
324 dummy = malo_hal_read4(mh, MALO_REG_INT_CODE);
328 malo_hal_waitfor(struct malo_hal *mh, uint32_t val)
332 for (i = 0; i < MALO_FW_MAX_NUM_CHECKS; i++) {
333 DELAY(MALO_FW_CHECK_USECS);
334 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == val)
342 * Firmware block xmit when talking to the boot-rom.
345 malo_hal_send_helper(struct malo_hal *mh, int bsize,
346 const void *data, size_t dsize, int waitfor)
348 mh->mh_cmdbuf[0] = htole16(MALO_HOSTCMD_CODE_DNLD);
349 mh->mh_cmdbuf[1] = htole16(bsize);
350 memcpy(&mh->mh_cmdbuf[4], data , dsize);
352 malo_hal_trigger_pcicmd(mh);
354 if (waitfor == MALO_NOWAIT)
357 /* XXX 2000 vs 200 */
358 if (malo_hal_waitfor(mh, MALO_INT_CODE_CMD_FINISHED) != 0) {
359 device_printf(mh->mh_dev,
360 "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n",
361 __func__, malo_hal_read4(mh, MALO_REG_INT_CODE));
367 malo_hal_write4(mh, MALO_REG_INT_CODE, 0);
373 malo_hal_fwload_helper(struct malo_hal *mh, char *helper)
375 const struct firmware *fw;
378 fw = firmware_get(helper);
380 device_printf(mh->mh_dev, "could not read microcode %s!\n",
385 device_printf(mh->mh_dev, "load %s firmware image (%zu bytes)\n",
386 helper, fw->datasize);
388 error = malo_hal_send_helper(mh, fw->datasize, fw->data, fw->datasize,
393 /* tell the card we're done and... */
394 error = malo_hal_send_helper(mh, 0, NULL, 0, MALO_NOWAIT);
397 firmware_put(fw, FIRMWARE_UNLOAD);
403 * Firmware block xmit when talking to the 1st-stage loader.
406 malo_hal_send_main(struct malo_hal *mh, const void *data, size_t dsize,
407 uint16_t seqnum, int waitfor)
409 mh->mh_cmdbuf[0] = htole16(MALO_HOSTCMD_CODE_DNLD);
410 mh->mh_cmdbuf[1] = htole16(dsize);
411 mh->mh_cmdbuf[2] = htole16(seqnum);
412 mh->mh_cmdbuf[3] = 0;
413 memcpy(&mh->mh_cmdbuf[4], data, dsize);
415 malo_hal_trigger_pcicmd(mh);
417 if (waitfor == MALO_NOWAIT)
420 if (malo_hal_waitfor(mh, MALO_INT_CODE_CMD_FINISHED) != 0) {
421 device_printf(mh->mh_dev,
422 "%s: timeout waiting for CMD_FINISHED, INT_CODE 0x%x\n",
423 __func__, malo_hal_read4(mh, MALO_REG_INT_CODE));
429 malo_hal_write4(mh, MALO_REG_INT_CODE, 0);
435 malo_hal_fwload_main(struct malo_hal *mh, char *firmware)
437 const struct firmware *fw;
446 fw = firmware_get(firmware);
448 device_printf(mh->mh_dev, "could not read firmware %s!\n",
453 device_printf(mh->mh_dev, "load %s firmware image (%zu bytes)\n",
454 firmware, fw->datasize);
457 for (count = 0; count < fw->datasize; count += blocksize) {
458 blocksize = MIN(256, fw->datasize - count);
459 fp = (const uint8_t *)fw->data + count;
461 error = malo_hal_send_main(mh, fp, blocksize, seqnum++,
469 * send a command with size 0 to tell that the firmware has been
472 error = malo_hal_send_main(mh, NULL, 0, seqnum++, MALO_NOWAIT);
476 firmware_put(fw, FIRMWARE_UNLOAD);
482 malo_hal_fwload(struct malo_hal *mh, char *helper, char *firmware)
485 uint32_t fwreadysig, opmode;
488 * NB: now malo(4) supports only STA mode. It will be better if it
491 fwreadysig = MALO_HOSTCMD_STA_FWRDY_SIGNATURE;
492 opmode = MALO_HOSTCMD_STA_MODE;
494 malo_hal_fw_reset(mh);
496 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_CLEAR_SEL,
497 MALO_A2HRIC_BIT_MASK);
498 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_CAUSE, 0x00);
499 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, 0x00);
500 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_STATUS_MASK,
501 MALO_A2HRIC_BIT_MASK);
503 error = malo_hal_fwload_helper(mh, helper);
505 device_printf(mh->mh_dev, "failed to load bootrom loader.\n");
509 DELAY(200 * MALO_FW_CHECK_USECS);
511 error = malo_hal_fwload_main(mh, firmware);
513 device_printf(mh->mh_dev, "failed to load firmware.\n");
518 * Wait for firmware to startup; we monitor the INT_CODE register
519 * waiting for a signature to written back indicating it's ready to go.
521 mh->mh_cmdbuf[1] = 0;
523 if (opmode != MALO_HOSTCMD_STA_MODE)
524 malo_hal_trigger_pcicmd(mh);
526 for (i = 0; i < MALO_FW_MAX_NUM_CHECKS; i++) {
527 malo_hal_write4(mh, MALO_REG_GEN_PTR, opmode);
528 DELAY(MALO_FW_CHECK_USECS);
529 if (malo_hal_read4(mh, MALO_REG_INT_CODE) == fwreadysig) {
530 malo_hal_write4(mh, MALO_REG_INT_CODE, 0x00);
531 return malo_hal_resetstate(mh);
537 malo_hal_fw_reset(mh);
543 * Return "hw specs". Note this must be the first cmd MUST be done after
544 * a firmware download or the f/w will lockup.
547 malo_hal_gethwspecs(struct malo_hal *mh, struct malo_hal_hwspec *hw)
549 struct malo_cmd_get_hwspec *cmd;
554 _CMD_SETUP(cmd, struct malo_cmd_get_hwspec, MALO_HOSTCMD_GET_HW_SPEC);
555 memset(&cmd->permaddr[0], 0xff, IEEE80211_ADDR_LEN);
556 cmd->ul_fw_awakecookie = htole32((unsigned int)mh->mh_cmdaddr + 2048);
558 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_GET_HW_SPEC);
560 IEEE80211_ADDR_COPY(hw->macaddr, cmd->permaddr);
561 hw->wcbbase[0] = le32toh(cmd->wcbbase0) & 0x0000ffff;
562 hw->wcbbase[1] = le32toh(cmd->wcbbase1) & 0x0000ffff;
563 hw->wcbbase[2] = le32toh(cmd->wcbbase2) & 0x0000ffff;
564 hw->wcbbase[3] = le32toh(cmd->wcbbase3) & 0x0000ffff;
565 hw->rxdesc_read = le32toh(cmd->rxpdrd_ptr)& 0x0000ffff;
566 hw->rxdesc_write = le32toh(cmd->rxpdwr_ptr)& 0x0000ffff;
567 hw->regioncode = le16toh(cmd->regioncode) & 0x00ff;
568 hw->fw_releasenum = le32toh(cmd->fw_releasenum);
569 hw->maxnum_wcb = le16toh(cmd->num_wcb);
570 hw->maxnum_mcaddr = le16toh(cmd->num_mcastaddr);
571 hw->num_antenna = le16toh(cmd->num_antenna);
572 hw->hwversion = cmd->version;
573 hw->hostinterface = cmd->hostif;
582 malo_hal_detach(struct malo_hal *mh)
585 bus_dmamem_free(mh->mh_dmat, mh->mh_cmdbuf, mh->mh_dmamap);
586 bus_dma_tag_destroy(mh->mh_dmat);
587 mtx_destroy(&mh->mh_mtx);
592 * Configure antenna use. Takes effect immediately.
594 * XXX tx antenna setting ignored
595 * XXX rx antenna setting should always be 3 (for now)
598 malo_hal_setantenna(struct malo_hal *mh, enum malo_hal_antenna dirset, int ant)
600 struct malo_cmd_rf_antenna *cmd;
603 if (!(dirset == MHA_ANTENNATYPE_RX || dirset == MHA_ANTENNATYPE_TX))
608 _CMD_SETUP(cmd, struct malo_cmd_rf_antenna,
609 MALO_HOSTCMD_802_11_RF_ANTENNA);
610 cmd->action = htole16(dirset);
611 if (ant == 0) { /* default to all/both antennae */
612 /* XXX never reach now. */
615 cmd->mode = htole16(ant);
617 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RF_ANTENNA);
625 * Configure radio. Takes effect immediately.
627 * XXX preamble installed after set fixed rate cmd
630 malo_hal_setradio(struct malo_hal *mh, int onoff,
631 enum malo_hal_preamble preamble)
633 struct malo_cmd_radio_control *cmd;
638 _CMD_SETUP(cmd, struct malo_cmd_radio_control,
639 MALO_HOSTCMD_802_11_RADIO_CONTROL);
640 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET);
644 cmd->control = htole16(preamble);
645 cmd->radio_on = htole16(onoff);
647 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RADIO_CONTROL);
655 * Set the interrupt mask.
658 malo_hal_intrset(struct malo_hal *mh, uint32_t mask)
661 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, 0);
662 (void)malo_hal_read4(mh, MALO_REG_INT_CODE);
665 malo_hal_write4(mh, MALO_REG_A2H_INTERRUPT_MASK, mask);
666 (void)malo_hal_read4(mh, MALO_REG_INT_CODE);
670 malo_hal_setchannel(struct malo_hal *mh, const struct malo_hal_channel *chan)
672 struct malo_cmd_fw_set_rf_channel *cmd;
677 _CMD_SETUP(cmd, struct malo_cmd_fw_set_rf_channel,
678 MALO_HOSTCMD_SET_RF_CHANNEL);
679 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET);
680 cmd->cur_channel = chan->channel;
682 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_RF_CHANNEL);
690 malo_hal_settxpower(struct malo_hal *mh, const struct malo_hal_channel *c)
692 struct malo_cmd_rf_tx_power *cmd;
693 const struct malo_hal_caldata *cal = &mh->mh_caldata;
694 uint8_t chan = c->channel;
700 _CMD_SETUP(cmd, struct malo_cmd_rf_tx_power,
701 MALO_HOSTCMD_802_11_RF_TX_POWER);
702 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET_LIST);
703 for (i = 0; i < 4; i++) {
704 idx = (chan - 1) * 4 + i;
705 pow = cal->pt_ratetable_20m[idx];
706 cmd->power_levellist[i] = htole16(pow);
708 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_802_11_RF_TX_POWER);
716 malo_hal_setpromisc(struct malo_hal *mh, int enable)
718 /* XXX need host cmd */
723 malo_hal_setassocid(struct malo_hal *mh,
724 const uint8_t bssid[IEEE80211_ADDR_LEN], uint16_t associd)
726 struct malo_cmd_fw_set_aid *cmd;
731 _CMD_SETUP(cmd, struct malo_cmd_fw_set_aid,
732 MALO_HOSTCMD_SET_AID);
733 cmd->cmdhdr.seqnum = 1;
734 cmd->associd = htole16(associd);
735 IEEE80211_ADDR_COPY(&cmd->macaddr[0], bssid);
737 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_AID);
743 * Kick the firmware to tell it there are new tx descriptors
744 * for processing. The driver says what h/w q has work in
745 * case the f/w ever gets smarter.
748 malo_hal_txstart(struct malo_hal *mh, int qnum)
750 bus_space_write_4(mh->mh_iot, mh->mh_ioh,
751 MALO_REG_H2A_INTERRUPT_EVENTS, MALO_H2ARIC_BIT_PPA_READY);
752 (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, MALO_REG_INT_CODE);
756 * Return the current ISR setting and clear the cause.
759 malo_hal_getisr(struct malo_hal *mh, uint32_t *status)
763 cause = bus_space_read_4(mh->mh_iot, mh->mh_ioh,
764 MALO_REG_A2H_INTERRUPT_CAUSE);
765 if (cause == 0xffffffff) { /* card removed */
767 } else if (cause != 0) {
768 /* clear cause bits */
769 bus_space_write_4(mh->mh_iot, mh->mh_ioh,
770 MALO_REG_A2H_INTERRUPT_CAUSE, cause &~ mh->mh_imask);
771 (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh,
773 cause &= mh->mh_imask;
780 * Callback from the driver on a cmd done interrupt. Nothing to do right
781 * now as we spin waiting for cmd completion.
784 malo_hal_cmddone(struct malo_hal *mh)
786 /* NB : do nothing. */
790 malo_hal_prescan(struct malo_hal *mh)
792 struct malo_cmd_prescan *cmd;
797 _CMD_SETUP(cmd, struct malo_cmd_prescan, MALO_HOSTCMD_SET_PRE_SCAN);
798 cmd->cmdhdr.seqnum = 1;
800 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_PRE_SCAN);
808 malo_hal_postscan(struct malo_hal *mh, uint8_t *macaddr, uint8_t ibsson)
810 struct malo_cmd_postscan *cmd;
815 _CMD_SETUP(cmd, struct malo_cmd_postscan, MALO_HOSTCMD_SET_POST_SCAN);
816 cmd->cmdhdr.seqnum = 1;
817 cmd->isibss = htole32(ibsson);
818 IEEE80211_ADDR_COPY(&cmd->bssid[0], macaddr);
820 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_POST_SCAN);
828 malo_hal_set_slot(struct malo_hal *mh, int is_short)
831 struct malo_cmd_fw_setslot *cmd;
835 _CMD_SETUP(cmd, struct malo_cmd_fw_setslot, MALO_HOSTCMD_SET_SLOT);
836 cmd->action = htole16(MALO_HOSTCMD_ACT_GEN_SET);
837 cmd->slot = (is_short == 1 ? 1 : 0);
839 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_SLOT);
847 malo_hal_set_rate(struct malo_hal *mh, uint16_t curmode, uint8_t rate)
850 struct malo_cmd_set_rate *cmd;
854 _CMD_SETUP(cmd, struct malo_cmd_set_rate, MALO_HOSTCMD_SET_RATE);
857 cmd->aprates[2] = 11;
858 cmd->aprates[3] = 22;
859 if (curmode == IEEE80211_MODE_11G) {
860 cmd->aprates[4] = 0; /* XXX reserved? */
861 cmd->aprates[5] = 12;
862 cmd->aprates[6] = 18;
863 cmd->aprates[7] = 24;
864 cmd->aprates[8] = 36;
865 cmd->aprates[9] = 48;
866 cmd->aprates[10] = 72;
867 cmd->aprates[11] = 96;
868 cmd->aprates[12] = 108;
873 for (i = 0; i < 13; i++) {
874 if (cmd->aprates[i] == rate) {
876 cmd->dataratetype = 1;
882 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_SET_RATE);
890 malo_hal_setmcast(struct malo_hal *mh, int nmc, const uint8_t macs[])
892 struct malo_cmd_mcast *cmd;
895 if (nmc > MALO_HAL_MCAST_MAX)
900 _CMD_SETUP(cmd, struct malo_cmd_mcast, MALO_HOSTCMD_MAC_MULTICAST_ADR);
901 memcpy(cmd->maclist, macs, nmc * IEEE80211_ADDR_LEN);
902 cmd->numaddr = htole16(nmc);
903 cmd->action = htole16(0xffff);
905 ret = malo_hal_execute_cmd(mh, MALO_HOSTCMD_MAC_MULTICAST_ADR);