2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2021 Microsoft Corp.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/types.h>
35 #include <sys/systm.h>
39 #include "shm_channel.h"
40 #include "gdma_util.h"
42 #define PAGE_FRAME_L48_WIDTH_BYTES 6
43 #define PAGE_FRAME_L48_WIDTH_BITS (PAGE_FRAME_L48_WIDTH_BYTES * 8)
44 #define PAGE_FRAME_L48_MASK 0x0000FFFFFFFFFFFF
45 #define PAGE_FRAME_H4_WIDTH_BITS 4
46 #define VECTOR_MASK 0xFFFF
47 #define SHMEM_VF_RESET_STATE ((uint32_t)-1)
49 #define SMC_MSG_TYPE_ESTABLISH_HWC 1
50 #define SMC_MSG_TYPE_ESTABLISH_HWC_VERSION 0
52 #define SMC_MSG_TYPE_DESTROY_HWC 2
53 #define SMC_MSG_TYPE_DESTROY_HWC_VERSION 0
55 #define SMC_MSG_DIRECTION_REQUEST 0
56 #define SMC_MSG_DIRECTION_RESPONSE 1
58 /* Structures labeled with "HW DATA" are exchanged with the hardware. All of
59 * them are naturally aligned and hence don't need __packed.
62 /* Shared memory channel protocol header
64 * msg_type: set on request and response; response matches request.
65 * msg_version: newer PF writes back older response (matching request)
66 * older PF acts on latest version known and sets that version in result
67 * (less than request).
68 * direction: 0 for request, VF->PF; 1 for response, PF->VF.
69 * status: 0 on request,
70 * operation result on response (success = 0, failure = 1 or greater).
71 * reset_vf: If set on either establish or destroy request, indicates perform
72 * FLR before/after the operation.
73 * owner_is_pf: 1 indicates PF owned, 0 indicates VF owned.
80 uint8_t msg_version : 3;
81 uint8_t reserved_1 : 1;
82 uint8_t direction : 1;
89 uint8_t reserved_3 : 6;
90 uint8_t owner_is_pf : 1;
94 #define SMC_APERTURE_BITS 256
95 #define SMC_BASIC_UNIT (sizeof(uint32_t))
96 #define SMC_APERTURE_DWORDS (SMC_APERTURE_BITS / (SMC_BASIC_UNIT * 8))
97 #define SMC_LAST_DWORD (SMC_APERTURE_DWORDS - 1)
100 mana_smc_poll_register(void __iomem *base, bool reset)
102 void __iomem *ptr = (uint8_t *)base + SMC_LAST_DWORD * SMC_BASIC_UNIT;
103 volatile uint32_t last_dword;
106 /* Poll the hardware for the ownership bit. This should be pretty fast,
107 * but let's do it in a loop just in case the hardware or the PF
108 * driver are temporarily busy.
110 for (i = 0; i < 20 * 1000; i++) {
111 last_dword = readl(ptr);
113 /* shmem reads as 0xFFFFFFFF in the reset case */
114 if (reset && last_dword == SHMEM_VF_RESET_STATE)
117 /* If bit_31 is set, the PF currently owns the SMC. */
118 if (!(last_dword & BIT(31)))
128 mana_smc_read_response(struct shm_channel *sc, uint32_t msg_type,
129 uint32_t msg_version, bool reset_vf)
131 void __iomem *base = sc->base;
132 union smc_proto_hdr hdr;
135 /* Wait for PF to respond. */
136 err = mana_smc_poll_register(base, reset_vf);
141 readl((uint8_t *)base + SMC_LAST_DWORD * SMC_BASIC_UNIT);
142 mana_dbg(NULL, "shm response 0x%x\n", hdr.as_uint32);
144 if (reset_vf && hdr.as_uint32 == SHMEM_VF_RESET_STATE)
147 /* Validate protocol fields from the PF driver */
148 if (hdr.msg_type != msg_type || hdr.msg_version > msg_version ||
149 hdr.direction != SMC_MSG_DIRECTION_RESPONSE) {
150 device_printf(sc->dev,
151 "Wrong SMC response 0x%x, type=%d, ver=%d\n",
152 hdr.as_uint32, msg_type, msg_version);
156 /* Validate the operation result */
157 if (hdr.status != 0) {
158 device_printf(sc->dev,
159 "SMC operation failed: 0x%x\n", hdr.status);
167 mana_smc_init(struct shm_channel *sc, device_t dev, void __iomem *base)
174 mana_smc_setup_hwc(struct shm_channel *sc, bool reset_vf, uint64_t eq_addr,
175 uint64_t cq_addr, uint64_t rq_addr, uint64_t sq_addr,
176 uint32_t eq_msix_index)
178 union smc_proto_hdr *hdr;
179 uint16_t all_addr_h4bits = 0;
180 uint16_t frame_addr_seq = 0;
181 uint64_t frame_addr = 0;
189 /* Ensure VF already has possession of shared memory */
190 err = mana_smc_poll_register(sc->base, false);
192 device_printf(sc->dev,
193 "Timeout when setting up HWC: %d\n", err);
197 if (!IS_ALIGNED(eq_addr, PAGE_SIZE) ||
198 !IS_ALIGNED(cq_addr, PAGE_SIZE) ||
199 !IS_ALIGNED(rq_addr, PAGE_SIZE) ||
200 !IS_ALIGNED(sq_addr, PAGE_SIZE))
203 if ((eq_msix_index & VECTOR_MASK) != eq_msix_index)
206 /* Scheme for packing four addresses and extra info into 256 bits.
208 * Addresses must be page frame aligned, so only frame address bits
211 * 52-bit frame addresses are split into the lower 48 bits and upper
212 * 4 bits. Lower 48 bits of 4 address are written sequentially from
213 * the start of the 256-bit shared memory region followed by 16 bits
214 * containing the upper 4 bits of the 4 addresses in sequence.
216 * A 16 bit EQ vector number fills out the next-to-last 32-bit dword.
218 * The final 32-bit dword is used for protocol control information as
219 * defined in smc_proto_hdr.
222 memset(shm_buf, 0, sizeof(shm_buf));
225 /* EQ addr: low 48 bits of frame address */
226 shmem = (uint64_t *)ptr;
227 frame_addr = PHYS_PFN(eq_addr);
228 *shmem = frame_addr & PAGE_FRAME_L48_MASK;
229 all_addr_h4bits |= (frame_addr >> PAGE_FRAME_L48_WIDTH_BITS) <<
230 (frame_addr_seq++ * PAGE_FRAME_H4_WIDTH_BITS);
231 ptr += PAGE_FRAME_L48_WIDTH_BYTES;
233 /* CQ addr: low 48 bits of frame address */
234 shmem = (uint64_t *)ptr;
235 frame_addr = PHYS_PFN(cq_addr);
236 *shmem = frame_addr & PAGE_FRAME_L48_MASK;
237 all_addr_h4bits |= (frame_addr >> PAGE_FRAME_L48_WIDTH_BITS) <<
238 (frame_addr_seq++ * PAGE_FRAME_H4_WIDTH_BITS);
239 ptr += PAGE_FRAME_L48_WIDTH_BYTES;
241 /* RQ addr: low 48 bits of frame address */
242 shmem = (uint64_t *)ptr;
243 frame_addr = PHYS_PFN(rq_addr);
244 *shmem = frame_addr & PAGE_FRAME_L48_MASK;
245 all_addr_h4bits |= (frame_addr >> PAGE_FRAME_L48_WIDTH_BITS) <<
246 (frame_addr_seq++ * PAGE_FRAME_H4_WIDTH_BITS);
247 ptr += PAGE_FRAME_L48_WIDTH_BYTES;
249 /* SQ addr: low 48 bits of frame address */
250 shmem = (uint64_t *)ptr;
251 frame_addr = PHYS_PFN(sq_addr);
252 *shmem = frame_addr & PAGE_FRAME_L48_MASK;
253 all_addr_h4bits |= (frame_addr >> PAGE_FRAME_L48_WIDTH_BITS) <<
254 (frame_addr_seq++ * PAGE_FRAME_H4_WIDTH_BITS);
255 ptr += PAGE_FRAME_L48_WIDTH_BYTES;
257 /* High 4 bits of the four frame addresses */
258 *((uint16_t *)ptr) = all_addr_h4bits;
259 ptr += sizeof(uint16_t);
261 /* EQ MSIX vector number */
262 *((uint16_t *)ptr) = (uint16_t)eq_msix_index;
263 ptr += sizeof(uint16_t);
265 /* 32-bit protocol header in final dword */
266 *((uint32_t *)ptr) = 0;
268 hdr = (union smc_proto_hdr *)ptr;
269 hdr->msg_type = SMC_MSG_TYPE_ESTABLISH_HWC;
270 hdr->msg_version = SMC_MSG_TYPE_ESTABLISH_HWC_VERSION;
271 hdr->direction = SMC_MSG_DIRECTION_REQUEST;
272 hdr->reset_vf = reset_vf;
274 /* Write 256-message buffer to shared memory (final 32-bit write
275 * triggers HW to set possession bit to PF).
277 dword = (uint32_t *)shm_buf;
278 for (i = 0; i < SMC_APERTURE_DWORDS; i++) {
279 mana_dbg(NULL, "write shm_buf %d, val: 0x%x\n",
281 writel((char *)sc->base + i * SMC_BASIC_UNIT, *dword++);
284 /* Read shmem response (polling for VF possession) and validate.
285 * For setup, waiting for response on shared memory is not strictly
286 * necessary, since wait occurs later for results to appear in EQE's.
288 err = mana_smc_read_response(sc, SMC_MSG_TYPE_ESTABLISH_HWC,
289 SMC_MSG_TYPE_ESTABLISH_HWC_VERSION, reset_vf);
291 device_printf(sc->dev,
292 "Error when setting up HWC: %d\n", err);
300 mana_smc_teardown_hwc(struct shm_channel *sc, bool reset_vf)
302 union smc_proto_hdr hdr = {};
305 /* Ensure already has possession of shared memory */
306 err = mana_smc_poll_register(sc->base, false);
308 device_printf(sc->dev, "Timeout when tearing down HWC\n");
312 /* Set up protocol header for HWC destroy message */
313 hdr.msg_type = SMC_MSG_TYPE_DESTROY_HWC;
314 hdr.msg_version = SMC_MSG_TYPE_DESTROY_HWC_VERSION;
315 hdr.direction = SMC_MSG_DIRECTION_REQUEST;
316 hdr.reset_vf = reset_vf;
318 /* Write message in high 32 bits of 256-bit shared memory, causing HW
319 * to set possession bit to PF.
321 writel((char *)sc->base + SMC_LAST_DWORD * SMC_BASIC_UNIT,
324 /* Read shmem response (polling for VF possession) and validate.
325 * For teardown, waiting for response is required to ensure hardware
326 * invalidates MST entries before software frees memory.
328 err = mana_smc_read_response(sc, SMC_MSG_TYPE_DESTROY_HWC,
329 SMC_MSG_TYPE_DESTROY_HWC_VERSION, reset_vf);
331 device_printf(sc->dev,
332 "Error when tearing down HWC: %d\n", err);