2 * Copyright (c) 2006 IronPort Systems
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * Copyright (c) 2007 LSI Corp.
28 * Copyright (c) 2007 Rajesh Prabhakaran.
29 * All rights reserved.
31 * Redistribution and use in source and binary forms, with or without
32 * modification, are permitted provided that the following conditions
34 * 1. Redistributions of source code must retain the above copyright
35 * notice, this list of conditions and the following disclaimer.
36 * 2. Redistributions in binary form must reproduce the above copyright
37 * notice, this list of conditions and the following disclaimer in the
38 * documentation and/or other materials provided with the distribution.
40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
56 #include <sys/cdefs.h>
57 __FBSDID("$FreeBSD$");
60 * MegaRAID SAS MFI firmware definitions
62 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely
63 * new firmware interface from the old AMI MegaRAID one, and there is no
64 * reason why this interface should be limited to just SAS. In any case, LSI
65 * seems to also call this interface 'MFI', so that will be used here.
69 * Start with the register set. All registers are 32 bits wide.
70 * The usual Intel IOP style setup.
72 #define MFI_IMSG0 0x10 /* Inbound message 0 */
73 #define MFI_IMSG1 0x14 /* Inbound message 1 */
74 #define MFI_OMSG0 0x18 /* Outbound message 0 */
75 #define MFI_OMSG1 0x1c /* Outbound message 1 */
76 #define MFI_IDB 0x20 /* Inbound doorbell */
77 #define MFI_ISTS 0x24 /* Inbound interrupt status */
78 #define MFI_IMSK 0x28 /* Inbound interrupt mask */
79 #define MFI_ODB 0x2c /* Outbound doorbell */
80 #define MFI_OSTS 0x30 /* Outbound interrupt status */
81 #define MFI_OMSK 0x34 /* Outbound interrupt mask */
82 #define MFI_IQP 0x40 /* Inbound queue port */
83 #define MFI_OQP 0x44 /* Outbound queue port */
86 * 1078 specific related register
88 #define MFI_ODR0 0x9c /* outbound doorbell register0 */
89 #define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */
90 #define MFI_OSP0 0xb0 /* outbound scratch pad0 */
91 #define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */
92 #define MFI_RMI 0x2 /* reply message interrupt */
93 #define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */
94 #define MFI_ODC 0x4 /* outbound doorbell change interrupt */
97 * GEN2 specific changes
99 #define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */
100 #define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */
102 /* Bits for MFI_OSTS */
103 #define MFI_OSTS_INTR_VALID 0x00000002
106 * Firmware state values. Found in OMSG0 during initialization.
108 #define MFI_FWSTATE_MASK 0xf0000000
109 #define MFI_FWSTATE_UNDEFINED 0x00000000
110 #define MFI_FWSTATE_BB_INIT 0x10000000
111 #define MFI_FWSTATE_FW_INIT 0x40000000
112 #define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000
113 #define MFI_FWSTATE_FW_INIT_2 0x70000000
114 #define MFI_FWSTATE_DEVICE_SCAN 0x80000000
115 #define MFI_FWSTATE_FLUSH_CACHE 0xa0000000
116 #define MFI_FWSTATE_READY 0xb0000000
117 #define MFI_FWSTATE_OPERATIONAL 0xc0000000
118 #define MFI_FWSTATE_FAULT 0xf0000000
119 #define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000
120 #define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff
123 * Control bits to drive the card to ready state. These go into the IDB
126 #define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */
127 #define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */
128 #define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */
129 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */
144 /* Direct commands */
146 MFI_DCMD_CTRL_GETINFO = 0x01010000,
147 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201,
148 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202,
149 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000,
150 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000,
151 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100,
152 MFI_DCMD_CTRL_EVENT_GET = 0x01040300,
153 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500,
154 MFI_DCMD_LD_GET_LIST = 0x03010000,
155 MFI_DCMD_LD_GET_INFO = 0x03020000,
156 MFI_DCMD_LD_GET_PROP = 0x03030000,
157 MFI_DCMD_LD_SET_PROP = 0x03040000,
158 MFI_DCMD_LD_DELETE = 0x03090000,
159 MFI_DCMD_CFG_READ = 0x04010000,
160 MFI_DCMD_CFG_ADD = 0x04020000,
161 MFI_DCMD_CFG_CLEAR = 0x04030000,
162 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400,
163 MFI_DCMD_CLUSTER = 0x08000000,
164 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100,
165 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200
168 /* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */
169 #define MFI_FLUSHCACHE_CTRL 0x01
170 #define MFI_FLUSHCACHE_DISK 0x02
172 /* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */
173 #define MFI_SHUTDOWN_SPINDOWN 0x01
178 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
179 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
180 #define MFI_FRAME_SGL32 0x0000
181 #define MFI_FRAME_SGL64 0x0002
182 #define MFI_FRAME_SENSE32 0x0000
183 #define MFI_FRAME_SENSE64 0x0004
184 #define MFI_FRAME_DIR_NONE 0x0000
185 #define MFI_FRAME_DIR_WRITE 0x0008
186 #define MFI_FRAME_DIR_READ 0x0010
187 #define MFI_FRAME_DIR_BOTH 0x0018
189 /* MFI Status codes */
192 MFI_STAT_INVALID_CMD,
193 MFI_STAT_INVALID_DCMD,
194 MFI_STAT_INVALID_PARAMETER,
195 MFI_STAT_INVALID_SEQUENCE_NUMBER,
196 MFI_STAT_ABORT_NOT_POSSIBLE,
197 MFI_STAT_APP_HOST_CODE_NOT_FOUND,
199 MFI_STAT_APP_NOT_INITIALIZED,
200 MFI_STAT_ARRAY_INDEX_INVALID,
201 MFI_STAT_ARRAY_ROW_NOT_EMPTY,
202 MFI_STAT_CONFIG_RESOURCE_CONFLICT,
203 MFI_STAT_DEVICE_NOT_FOUND,
204 MFI_STAT_DRIVE_TOO_SMALL,
205 MFI_STAT_FLASH_ALLOC_FAIL,
207 MFI_STAT_FLASH_ERROR = 0x10,
208 MFI_STAT_FLASH_IMAGE_BAD,
209 MFI_STAT_FLASH_IMAGE_INCOMPLETE,
210 MFI_STAT_FLASH_NOT_OPEN,
211 MFI_STAT_FLASH_NOT_STARTED,
212 MFI_STAT_FLUSH_FAILED,
213 MFI_STAT_HOST_CODE_NOT_FOUNT,
214 MFI_STAT_LD_CC_IN_PROGRESS,
215 MFI_STAT_LD_INIT_IN_PROGRESS,
216 MFI_STAT_LD_LBA_OUT_OF_RANGE,
217 MFI_STAT_LD_MAX_CONFIGURED,
218 MFI_STAT_LD_NOT_OPTIMAL,
219 MFI_STAT_LD_RBLD_IN_PROGRESS,
220 MFI_STAT_LD_RECON_IN_PROGRESS,
221 MFI_STAT_LD_WRONG_RAID_LEVEL,
222 MFI_STAT_MAX_SPARES_EXCEEDED,
223 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
224 MFI_STAT_MFC_HW_ERROR,
225 MFI_STAT_NO_HW_PRESENT,
227 MFI_STAT_NOT_IN_ENCL,
228 MFI_STAT_PD_CLEAR_IN_PROGRESS,
229 MFI_STAT_PD_TYPE_WRONG,
230 MFI_STAT_PR_DISABLED,
231 MFI_STAT_ROW_INDEX_INVALID,
232 MFI_STAT_SAS_CONFIG_INVALID_ACTION,
233 MFI_STAT_SAS_CONFIG_INVALID_DATA,
234 MFI_STAT_SAS_CONFIG_INVALID_PAGE,
235 MFI_STAT_SAS_CONFIG_INVALID_TYPE,
236 MFI_STAT_SCSI_DONE_WITH_ERROR,
237 MFI_STAT_SCSI_IO_FAILED,
238 MFI_STAT_SCSI_RESERVATION_CONFLICT,
239 MFI_STAT_SHUTDOWN_FAILED = 0x30,
240 MFI_STAT_TIME_NOT_SET,
241 MFI_STAT_WRONG_STATE,
243 MFI_STAT_PEER_NOTIFICATION_REJECTED,
244 MFI_STAT_PEER_NOTIFICATION_FAILED,
245 MFI_STAT_RESERVATION_IN_PROGRESS,
246 MFI_STAT_I2C_ERRORS_DETECTED,
247 MFI_STAT_PCI_ERRORS_DETECTED,
248 MFI_STAT_INVALID_STATUS = 0xFF
252 MFI_EVT_CLASS_DEBUG = -2,
253 MFI_EVT_CLASS_PROGRESS = -1,
254 MFI_EVT_CLASS_INFO = 0,
255 MFI_EVT_CLASS_WARNING = 1,
256 MFI_EVT_CLASS_CRITICAL = 2,
257 MFI_EVT_CLASS_FATAL = 3,
258 MFI_EVT_CLASS_DEAD = 4
262 MFI_EVT_LOCALE_LD = 0x0001,
263 MFI_EVT_LOCALE_PD = 0x0002,
264 MFI_EVT_LOCALE_ENCL = 0x0004,
265 MFI_EVT_LOCALE_BBU = 0x0008,
266 MFI_EVT_LOCALE_SAS = 0x0010,
267 MFI_EVT_LOCALE_CTRL = 0x0020,
268 MFI_EVT_LOCALE_CONFIG = 0x0040,
269 MFI_EVT_LOCALE_CLUSTER = 0x0080,
270 MFI_EVT_LOCALE_ALL = 0xffff
274 MR_EVT_ARGS_NONE = 0x00,
275 MR_EVT_ARGS_CDB_SENSE,
277 MR_EVT_ARGS_LD_COUNT,
279 MR_EVT_ARGS_LD_OWNER,
280 MR_EVT_ARGS_LD_LBA_PD_LBA,
282 MR_EVT_ARGS_LD_STATE,
283 MR_EVT_ARGS_LD_STRIP,
287 MR_EVT_ARGS_PD_LBA_LD,
289 MR_EVT_ARGS_PD_STATE,
298 MR_LD_CACHE_WRITE_BACK = 0x01,
299 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02,
300 MR_LD_CACHE_READ_AHEAD = 0x04,
301 MR_LD_CACHE_READ_ADAPTIVE = 0x08,
302 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10,
303 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20,
304 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40
308 MR_PD_CACHE_UNCHANGED = 0,
309 MR_PD_CACHE_ENABLE = 1,
310 MR_PD_CACHE_DISABLE = 2
314 * Other propertities and definitions
316 #define MFI_MAX_PD_CHANNELS 2
317 #define MFI_MAX_LD_CHANNELS 2
318 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS)
319 #define MFI_MAX_CHANNEL_DEVS 128
320 #define MFI_DEFAULT_ID -1
321 #define MFI_MAX_LUN 8
322 #define MFI_MAX_LD 64
324 #define MFI_FRAME_SIZE 64
325 #define MFI_MBOX_SIZE 12
327 /* Firmware flashing can take 40s */
328 #define MFI_POLL_TIMEOUT_SECS 50
330 /* Allow for speedier math calculations */
331 #define MFI_SECTOR_LEN 512
333 /* Scatter Gather elements */
345 struct mfi_sg32 sg32[1];
346 struct mfi_sg64 sg64[1];
349 /* Message frames. All messages have a common header */
350 struct mfi_frame_header {
362 #define MFI_FRAME_DATAOUT 0x08
363 #define MFI_FRAME_DATAIN 0x10
368 struct mfi_init_frame {
369 struct mfi_frame_header header;
370 uint32_t qinfo_new_addr_lo;
371 uint32_t qinfo_new_addr_hi;
372 uint32_t qinfo_old_addr_lo;
373 uint32_t qinfo_old_addr_hi;
374 uint32_t reserved[6];
377 #define MFI_IO_FRAME_SIZE 40
378 struct mfi_io_frame {
379 struct mfi_frame_header header;
380 uint32_t sense_addr_lo;
381 uint32_t sense_addr_hi;
387 #define MFI_PASS_FRAME_SIZE 48
388 struct mfi_pass_frame {
389 struct mfi_frame_header header;
390 uint32_t sense_addr_lo;
391 uint32_t sense_addr_hi;
396 #define MFI_DCMD_FRAME_SIZE 40
397 struct mfi_dcmd_frame {
398 struct mfi_frame_header header;
400 uint8_t mbox[MFI_MBOX_SIZE];
404 struct mfi_abort_frame {
405 struct mfi_frame_header header;
406 uint32_t abort_context;
408 uint32_t abort_mfi_addr_lo;
409 uint32_t abort_mfi_addr_hi;
410 uint32_t reserved[6];
413 struct mfi_smp_frame {
414 struct mfi_frame_header header;
417 struct mfi_sg32 sg32[2];
418 struct mfi_sg64 sg64[2];
422 struct mfi_stp_frame {
423 struct mfi_frame_header header;
427 struct mfi_sg32 sg32[2];
428 struct mfi_sg64 sg64[2];
433 struct mfi_frame_header header;
434 struct mfi_init_frame init;
435 struct mfi_io_frame io;
436 struct mfi_pass_frame pass;
437 struct mfi_dcmd_frame dcmd;
438 struct mfi_abort_frame abort;
439 struct mfi_smp_frame smp;
440 struct mfi_stp_frame stp;
441 uint8_t bytes[MFI_FRAME_SIZE];
444 #define MFI_SENSE_LEN 128
446 uint8_t data[MFI_SENSE_LEN];
449 /* The queue init structure that is passed with the init message */
450 struct mfi_init_qinfo {
461 /* SAS (?) controller properties, part of mfi_ctrl_info */
462 struct mfi_ctrl_props {
464 uint16_t pred_fail_poll_interval;
465 uint16_t intr_throttle_cnt;
466 uint16_t intr_throttle_timeout;
467 uint8_t rebuild_rate;
468 uint8_t patrol_read_rate;
472 uint8_t cache_flush_interval;
473 uint8_t spinup_drv_cnt;
474 uint8_t spinup_delay;
475 uint8_t cluster_enable;
476 uint8_t coercion_mode;
477 uint8_t alarm_enable;
478 uint8_t disable_auto_rebuild;
479 uint8_t disable_battery_warn;
480 uint8_t ecc_bucket_size;
481 uint16_t ecc_bucket_leak_rate;
482 uint8_t restore_hotspare_on_insertion;
483 uint8_t expose_encl_devices;
484 uint8_t reserved[38];
487 /* PCI information about the card. */
488 struct mfi_info_pci {
493 uint8_t reserved[24];
496 /* Host (front end) interface information */
497 struct mfi_info_host {
499 #define MFI_INFO_HOST_PCIX 0x01
500 #define MFI_INFO_HOST_PCIE 0x02
501 #define MFI_INFO_HOST_ISCSI 0x04
502 #define MFI_INFO_HOST_SAS3G 0x08
505 uint64_t port_addr[8];
508 /* Device (back end) interface information */
509 struct mfi_info_device {
511 #define MFI_INFO_DEV_SPI 0x01
512 #define MFI_INFO_DEV_SAS3G 0x02
513 #define MFI_INFO_DEV_SATA1 0x04
514 #define MFI_INFO_DEV_SATA3G 0x08
517 uint64_t port_addr[8];
520 /* Firmware component information */
521 struct mfi_info_component {
528 /* Controller default settings */
529 struct mfi_defaults {
531 uint8_t phy_polarity;
532 uint8_t background_rate;
537 uint8_t cache_when_bbu_bad;
540 uint8_t alarm_disable;
543 uint8_t dirty_led_shows_drive_activity;
544 uint8_t bios_continue_on_error;
545 uint8_t spindown_mode;
546 uint8_t allowed_device_types;
547 uint8_t allow_mix_in_enclosure;
548 uint8_t allow_mix_in_ld;
549 uint8_t allow_sata_in_cluster;
550 uint8_t max_chained_enclosures;
551 uint8_t disable_ctrl_r;
552 uint8_t enabel_web_bios;
553 uint8_t phy_polarity_split;
554 uint8_t direct_pd_mapping;
555 uint8_t bios_enumerate_lds;
556 uint8_t restored_hot_spare_on_insertion;
557 uint8_t expose_enclosure_devices;
558 uint8_t maintain_pd_fail_history;
562 /* Controller default settings */
563 struct mfi_bios_data {
564 uint16_t boot_target_id;
565 uint8_t do_not_int_13;
566 uint8_t continue_on_error;
569 uint8_t expose_all_drives;
570 uint8_t reserved[56];
574 /* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */
575 struct mfi_ctrl_info {
576 struct mfi_info_pci pci;
577 struct mfi_info_host host;
578 struct mfi_info_device device;
580 /* Firmware components that are present and active. */
581 uint32_t image_check_word;
582 uint32_t image_component_count;
583 struct mfi_info_component image_component[8];
585 /* Firmware components that have been flashed but are inactive */
586 uint32_t pending_image_component_count;
587 struct mfi_info_component pending_image_component[8];
593 char product_name[80];
594 char serial_number[32];
596 #define MFI_INFO_HW_BBU 0x01
597 #define MFI_INFO_HW_ALARM 0x02
598 #define MFI_INFO_HW_NVRAM 0x04
599 #define MFI_INFO_HW_UART 0x08
600 uint32_t current_fw_time;
602 uint16_t max_sg_elements;
603 uint32_t max_request_size;
604 uint16_t lds_present;
605 uint16_t lds_degraded;
606 uint16_t lds_offline;
608 uint16_t pd_disks_present;
609 uint16_t pd_disks_pred_failure;
610 uint16_t pd_disks_failed;
612 uint16_t memory_size;
614 uint16_t ram_correctable_errors;
615 uint16_t ram_uncorrectable_errors;
616 uint8_t cluster_allowed;
617 uint8_t cluster_active;
618 uint16_t max_strips_per_io;
620 uint32_t raid_levels;
621 #define MFI_INFO_RAID_0 0x01
622 #define MFI_INFO_RAID_1 0x02
623 #define MFI_INFO_RAID_5 0x04
624 #define MFI_INFO_RAID_1E 0x08
625 #define MFI_INFO_RAID_6 0x10
627 uint32_t adapter_ops;
628 #define MFI_INFO_AOPS_RBLD_RATE 0x0001
629 #define MFI_INFO_AOPS_CC_RATE 0x0002
630 #define MFI_INFO_AOPS_BGI_RATE 0x0004
631 #define MFI_INFO_AOPS_RECON_RATE 0x0008
632 #define MFI_INFO_AOPS_PATROL_RATE 0x0010
633 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020
634 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040
635 #define MFI_INFO_AOPS_BBU 0x0080
636 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100
637 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200
638 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400
639 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800
640 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000
641 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000
642 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000
645 #define MFI_INFO_LDOPS_READ_POLICY 0x01
646 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02
647 #define MFI_INFO_LDOPS_IO_POLICY 0x04
648 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08
649 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10
655 } __packed stripe_sz_ops;
658 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01
659 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02
660 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04
662 uint32_t pd_mix_support;
663 #define MFI_INFO_PDMIX_SAS 0x01
664 #define MFI_INFO_PDMIX_SATA 0x02
665 #define MFI_INFO_PDMIX_ENCL 0x04
666 #define MFI_INFO_PDMIX_LD 0x08
667 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10
669 uint8_t ecc_bucket_count;
670 uint8_t reserved2[11];
671 struct mfi_ctrl_props properties;
672 char package_version[0x60];
673 uint8_t pad[0x800 - 0x6a0];
676 /* keep track of an event. */
686 /* event log state. */
687 struct mfi_evt_log_state {
688 uint32_t newest_seq_num;
689 uint32_t oldest_seq_num;
690 uint32_t clear_seq_num;
691 uint32_t shutdown_seq_num;
692 uint32_t boot_seq_num;
695 struct mfi_progress {
697 uint16_t elapsed_seconds;
708 uint8_t enclosure_index;
712 /* SAS (?) event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */
713 struct mfi_evt_detail {
719 uint8_t reserved1[15];
723 struct mfi_evt_pd pd;
731 struct mfi_evt_ld ld;
734 struct mfi_evt_ld ld;
740 struct mfi_evt_ld ld;
744 struct mfi_evt_ld ld;
752 struct mfi_evt_ld ld;
753 struct mfi_evt_pd pd;
757 struct mfi_evt_ld ld;
758 struct mfi_progress prog;
762 struct mfi_evt_ld ld;
769 struct mfi_evt_ld ld;
772 struct mfi_evt_pd pd;
775 struct mfi_evt_pd pd;
781 struct mfi_evt_pd pd;
786 struct mfi_evt_pd pd;
787 struct mfi_evt_ld ld;
791 struct mfi_evt_pd pd;
792 struct mfi_progress prog;
796 struct mfi_evt_pd ld;
804 uint16_t subVenderId;
805 uint16_t subDeviceId;
814 uint16_t elapsedSeconds;
829 char description[128];
832 struct mfi_evt_list {
835 struct mfi_evt_detail event[1];
846 union mfi_pd_ddf_type {
850 uint16_t forced_pd_guid : 1;
852 uint16_t is_global_spare : 1;
853 uint16_t is_spare : 1;
854 uint16_t is_foreign : 1;
855 uint16_t reserved : 7;
868 struct mfi_pd_progress {
873 uint32_t reserved: 29;
875 struct mfi_progress rbld;
876 struct mfi_progress patrol;
877 struct mfi_progress clear;
878 struct mfi_progress reserved[4];
882 union mfi_pd_ref ref;
883 uint8_t inquiry_data[96];
884 uint8_t vpd_page83[64];
885 uint8_t not_supported;
886 uint8_t scsi_dev_type;
887 uint8_t connected_port_bitmap;
888 uint8_t device_speed;
889 uint32_t media_err_count;
890 uint32_t other_err_count;
891 uint32_t pred_fail_count;
892 uint32_t last_pred_fail_event_seq_num;
894 uint8_t disable_for_removal;
896 union mfi_pd_ddf_type state;
899 uint8_t is_path_broken;
901 uint64_t sas_addr[4];
904 uint64_t non_coerced_size;
905 uint64_t coerced_size;
906 uint16_t encl_device_id;
909 struct mfi_pd_progress prog_info;
910 uint8_t bad_block_table_full;
911 uint8_t unusable_in_current_config;
912 uint8_t vpd_page83_ext[64];
913 uint8_t reserved[512-358];
916 struct mfi_pd_address {
918 uint16_t encl_device_id;
921 uint8_t scsi_dev_type;
922 uint8_t connect_port_bitmap;
923 uint64_t sas_addr[2];
931 struct mfi_pd_address addr[];
950 uint8_t reserved2[3];
952 } ld_list[MFI_MAX_LD];
956 MFI_LD_ACCESS_RW = 0,
957 MFI_LD_ACCSSS_RO = 2,
958 MFI_LD_ACCESS_BLOCKED = 3,
960 #define MFI_LD_ACCESS_MASK 3
963 MFI_LD_STATE_OFFLINE = 0,
964 MFI_LD_STATE_PARTIALLY_DEGRADED = 1,
965 MFI_LD_STATE_DEGRADED = 2,
966 MFI_LD_STATE_OPTIMAL = 3
969 struct mfi_ld_props {
972 uint8_t default_cache_policy;
973 uint8_t access_policy;
974 uint8_t disk_cache_policy;
975 uint8_t current_cache_policy;
980 struct mfi_ld_params {
981 uint8_t primary_raid_level;
982 uint8_t raid_level_qualifier;
983 uint8_t secondary_raid_level;
989 uint8_t is_consistent;
990 uint8_t reserved[23];
993 struct mfi_ld_progress {
995 #define MFI_LD_PROGRESS_CC (1<<0)
996 #define MFI_LD_PROGRESS_BGI (1<<1)
997 #define MFI_LD_PROGRESS_FGI (1<<2)
998 #define MFI_LD_PORGRESS_RECON (1<<3)
999 struct mfi_progress cc;
1000 struct mfi_progress bgi;
1001 struct mfi_progress fgi;
1002 struct mfi_progress recon;
1003 struct mfi_progress reserved[4];
1007 uint64_t start_block;
1008 uint64_t num_blocks;
1010 uint8_t reserved[6];
1013 #define MFI_MAX_SPAN_DEPTH 8
1014 struct mfi_ld_config {
1015 struct mfi_ld_props properties;
1016 struct mfi_ld_params params;
1017 struct mfi_span span[MFI_MAX_SPAN_DEPTH];
1020 struct mfi_ld_info {
1021 struct mfi_ld_config ld_config;
1023 struct mfi_ld_progress progress;
1024 uint16_t cluster_owner;
1025 uint8_t reconstruct_active;
1026 uint8_t reserved1[1];
1027 uint8_t vpd_page83[64];
1028 uint8_t reserved2[16];
1031 union mfi_spare_type {
1033 uint8_t is_dedicate :1;
1034 uint8_t is_revertable :1;
1035 uint8_t is_encl_affinity :1;
1036 uint8_t reserved :5;
1041 #define MAX_ARRAYS 16
1043 union mfi_pd_ref ref;
1044 union mfi_spare_type spare_type;
1045 uint8_t reserved[2];
1046 uint8_t array_count;
1047 uint16_t array_refd[MAX_ARRAYS];
1050 #define MAX_ROW_SIZE 32
1058 union mfi_pd_ref ref;
1067 struct mfi_config_data {
1069 uint16_t array_count;
1070 uint16_t array_size;
1071 uint16_t log_drv_count;
1072 uint16_t log_drv_size;
1073 uint16_t spares_count;
1074 uint16_t spares_size;
1075 uint8_t reserved[16];
1078 struct mfi_array array[];
1079 struct mfi_ld_config ld[];
1080 struct mfi_spare spare[];
1084 #define MFI_SCSI_MAX_TARGETS 128
1085 #define MFI_SCSI_MAX_LUNS 8
1086 #define MFI_SCSI_INITIATOR_ID 255
1087 #define MFI_SCSI_MAX_CMDS 8
1088 #define MFI_SCSI_MAX_CDB_LEN 16
1090 #endif /* _MFIREG_H */