2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
5 * Developed by Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 #define MGE_INTR_COUNT 5 /* ETH controller occupies 5 IRQ lines */
38 #define MGE_TX_DESC_NUM 256
39 #define MGE_RX_DESC_NUM 256
40 #define MGE_RX_QUEUE_NUM 8
41 #define MGE_RX_DEFAULT_QUEUE 0
43 #define MGE_CHECKSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
45 /* Interrupt Coalescing types */
57 struct mge_desc_wrapper {
58 bus_dmamap_t desc_dmap;
59 struct mge_desc* mge_desc;
60 bus_addr_t mge_desc_paddr;
61 bus_dmamap_t buffer_dmap;
66 struct ifnet *ifp; /* per-interface network data */
74 struct resource *res[1 + MGE_INTR_COUNT]; /* resources */
75 void *ih_cookie[MGE_INTR_COUNT]; /* interrupt handlers cookies */
76 struct mtx transmit_lock; /* transmitter lock */
77 struct mtx receive_lock; /* receiver lock */
79 uint32_t mge_if_flags;
80 uint32_t mge_media_status;
82 struct callout wd_callout;
85 bus_dma_tag_t mge_desc_dtag;
86 bus_dma_tag_t mge_tx_dtag;
87 bus_dma_tag_t mge_rx_dtag;
88 bus_addr_t tx_desc_start;
89 bus_addr_t rx_desc_start;
90 uint32_t tx_desc_curr;
91 uint32_t rx_desc_curr;
92 uint32_t tx_desc_used_idx;
93 uint32_t tx_desc_used_count;
96 struct mge_desc_wrapper mge_tx_desc[MGE_TX_DESC_NUM];
97 struct mge_desc_wrapper mge_rx_desc[MGE_RX_DESC_NUM];
99 uint32_t mge_tfut_ipg_max; /* TX FIFO Urgent Threshold */
100 uint32_t mge_rx_ipg_max;
101 uint32_t mge_tx_arb_cfg;
102 uint32_t mge_tx_tok_cfg;
103 uint32_t mge_tx_tok_cnt;
109 struct mge_softc *phy_sc;
113 /* bus access macros */
114 #define MGE_READ(sc,reg) bus_read_4((sc)->res[0], (reg))
115 #define MGE_WRITE(sc,reg,val) bus_write_4((sc)->res[0], (reg), (val))
118 #define MGE_TRANSMIT_LOCK(sc) do { \
119 mtx_assert(&(sc)->receive_lock, MA_NOTOWNED); \
120 mtx_lock(&(sc)->transmit_lock); \
123 #define MGE_TRANSMIT_UNLOCK(sc) mtx_unlock(&(sc)->transmit_lock)
124 #define MGE_TRANSMIT_LOCK_ASSERT(sc) mtx_assert(&(sc)->transmit_lock, MA_OWNED)
126 #define MGE_RECEIVE_LOCK(sc) do { \
127 mtx_assert(&(sc)->transmit_lock, MA_NOTOWNED); \
128 mtx_lock(&(sc)->receive_lock); \
131 #define MGE_RECEIVE_UNLOCK(sc) mtx_unlock(&(sc)->receive_lock)
132 #define MGE_RECEIVE_LOCK_ASSERT(sc) mtx_assert(&(sc)->receive_lock, MA_OWNED)
134 #define MGE_GLOBAL_LOCK(sc) do { \
135 if ((mtx_owned(&(sc)->transmit_lock) ? 1 : 0) != \
136 (mtx_owned(&(sc)->receive_lock) ? 1 : 0)) { \
137 panic("mge deadlock possibility detection!"); \
139 mtx_lock(&(sc)->transmit_lock); \
140 mtx_lock(&(sc)->receive_lock); \
143 #define MGE_GLOBAL_UNLOCK(sc) do { \
144 MGE_RECEIVE_UNLOCK(sc); \
145 MGE_TRANSMIT_UNLOCK(sc); \
148 #define MGE_GLOBAL_LOCK_ASSERT(sc) do { \
149 MGE_TRANSMIT_LOCK_ASSERT(sc); \
150 MGE_RECEIVE_LOCK_ASSERT(sc); \
153 /* SMI-related macros */
154 #define MGE_REG_PHYDEV 0x000
155 #define MGE_REG_SMI 0x004
156 #define MGE_SMI_READ (1 << 26)
157 #define MGE_SMI_WRITE (0 << 26)
158 #define MGE_SMI_READVALID (1 << 27)
159 #define MGE_SMI_BUSY (1 << 28)
161 /* TODO verify the timings and retries count w/specs */
162 #define MGE_SMI_READ_RETRIES 1000
163 #define MGE_SMI_READ_DELAY 100
164 #define MGE_SMI_WRITE_RETRIES 1000
165 #define MGE_SMI_WRITE_DELAY 100
168 #define MGE_INT_CAUSE 0x080
169 #define MGE_INT_MASK 0x084
171 #define MGE_PORT_CONFIG 0x400
172 #define PORT_CONFIG_UPM (1 << 0) /* promiscuous */
173 #define PORT_CONFIG_DFLT_RXQ(val) (((val) & 7) << 1) /* default RX queue */
174 #define PORT_CONFIG_ARO_RXQ(val) (((val) & 7) << 4) /* ARP RX queue */
175 #define PORT_CONFIG_REJECT_BCAST (1 << 7) /* reject non-ip and non-arp bcast */
176 #define PORT_CONFIG_REJECT_IP_BCAST (1 << 8) /* reject ip bcast */
177 #define PORT_CONFIG_REJECT_ARP__BCAST (1 << 9) /* reject arp bcast */
178 #define PORT_CONFIG_AMNoTxES (1 << 12) /* Automatic mode not updating Error Summary in Tx descriptor */
179 #define PORT_CONFIG_TCP_CAP (1 << 14) /* capture tcp to a different queue */
180 #define PORT_CONFIG_UDP_CAP (1 << 15) /* capture udp to a different queue */
181 #define PORT_CONFIG_TCPQ (7 << 16) /* queue to capture tcp */
182 #define PORT_CONFIG_UDPQ (7 << 19) /* queue to capture udp */
183 #define PORT_CONFIG_BPDUQ (7 << 22) /* queue to capture bpdu */
184 #define PORT_CONFIG_RXCS (1 << 25) /* calculation Rx TCP checksum include pseudo header */
186 #define MGE_PORT_EXT_CONFIG 0x404
187 #define MGE_MAC_ADDR_L 0x414
188 #define MGE_MAC_ADDR_H 0x418
190 #define MGE_SDMA_CONFIG 0x41c
191 #define MGE_SDMA_INT_ON_FRAME_BOUND (1 << 0)
192 #define MGE_SDMA_RX_BURST_SIZE(val) (((val) & 7) << 1)
193 #define MGE_SDMA_TX_BURST_SIZE(val) (((val) & 7) << 22)
194 #define MGE_SDMA_BURST_1_WORD 0x0
195 #define MGE_SDMA_BURST_2_WORD 0x1
196 #define MGE_SDMA_BURST_4_WORD 0x2
197 #define MGE_SDMA_BURST_8_WORD 0x3
198 #define MGE_SDMA_BURST_16_WORD 0x4
199 #define MGE_SDMA_RX_BYTE_SWAP (1 << 4)
200 #define MGE_SDMA_TX_BYTE_SWAP (1 << 5)
201 #define MGE_SDMA_DESC_SWAP_MODE (1 << 6)
203 #define MGE_PORT_SERIAL_CTRL 0x43c
204 #define PORT_SERIAL_ENABLE (1 << 0) /* serial port enable */
205 #define PORT_SERIAL_FORCE_LINKUP (1 << 1) /* force link status to up */
206 #define PORT_SERIAL_AUTONEG (1 << 2) /* enable autoneg for duplex mode */
207 #define PORT_SERIAL_AUTONEG_FC (1 << 3) /* enable autoneg for FC */
208 #define PORT_SERIAL_PAUSE_ADV (1 << 4) /* advertise symmetric FC in autoneg */
209 #define PORT_SERIAL_FORCE_FC(val) (((val) & 3) << 5) /* pause enable & disable frames conf */
210 #define PORT_SERIAL_NO_PAUSE_DIS 0x00
211 #define PORT_SERIAL_PAUSE_DIS 0x01
212 #define PORT_SERIAL_FORCE_BP(val) (((val) & 3) << 7) /* transmitting JAM configuration */
213 #define PORT_SERIAL_NO_JAM 0x00
214 #define PORT_SERIAL_JAM 0x01
215 #define PORT_SERIAL_RES_BIT9 (1 << 9)
216 #define PORT_SERIAL_FORCE_LINK_FAIL (1 << 10)
217 #define PORT_SERIAL_SPEED_AUTONEG (1 << 13)
218 #define PORT_SERIAL_FORCE_DTE_ADV (1 << 14)
219 #define PORT_SERIAL_MRU(val) (((val) & 7) << 17)
220 #define PORT_SERIAL_MRU_1518 0x0
221 #define PORT_SERIAL_MRU_1522 0x1
222 #define PORT_SERIAL_MRU_1552 0x2
223 #define PORT_SERIAL_MRU_9022 0x3
224 #define PORT_SERIAL_MRU_9192 0x4
225 #define PORT_SERIAL_MRU_9700 0x5
226 #define PORT_SERIAL_FULL_DUPLEX (1 << 21)
227 #define PORT_SERIAL_FULL_DUPLEX_FC (1 << 22)
228 #define PORT_SERIAL_GMII_SPEED_1000 (1 << 23)
229 #define PORT_SERIAL_MII_SPEED_100 (1 << 24)
231 #define MGE_PORT_STATUS 0x444
232 #define MGE_STATUS_LINKUP (1 << 1)
233 #define MGE_STATUS_FULL_DUPLEX (1 << 2)
234 #define MGE_STATUS_FLOW_CONTROL (1 << 3)
235 #define MGE_STATUS_1000MB (1 << 4)
236 #define MGE_STATUS_100MB (1 << 5)
237 #define MGE_STATUS_TX_IN_PROG (1 << 7)
238 #define MGE_STATUS_TX_FIFO_EMPTY (1 << 10)
240 #define MGE_TX_QUEUE_CMD 0x448
241 #define MGE_ENABLE_TXQ (1 << 0)
242 #define MGE_DISABLE_TXQ (1 << 8)
245 #define MGE_PORT_SERIAL_CTRL1 0x44c
246 #define MGE_PCS_LOOPBACK (1 << 1)
247 #define MGE_RGMII_EN (1 << 3)
248 #define MGE_PORT_RESET (1 << 4)
249 #define MGE_CLK125_BYPASS (1 << 5)
250 #define MGE_INBAND_AUTONEG (1 << 6)
251 #define MGE_INBAND_AUTONEG_BYPASS (1 << 6)
252 #define MGE_INBAND_AUTONEG_RESTART (1 << 7)
253 #define MGE_1000BASEX (1 << 11)
254 #define MGE_BP_COLLISION_COUNT (1 << 15)
255 #define MGE_COLLISION_LIMIT(val) (((val) & 0x3f) << 16)
256 #define MGE_DROP_ODD_PREAMBLE (1 << 22)
258 #define MGE_PORT_INT_CAUSE 0x460
259 #define MGE_PORT_INT_MASK 0x468
260 #define MGE_PORT_INT_RX (1 << 0)
261 #define MGE_PORT_INT_EXTEND (1 << 1)
262 #define MGE_PORT_INT_RXQ0 (1 << 2)
263 #define MGE_PORT_INT_RXERR (1 << 10)
264 #define MGE_PORT_INT_RXERRQ0 (1 << 11)
265 #define MGE_PORT_INT_SUM (1U << 31)
267 #define MGE_PORT_INT_CAUSE_EXT 0x464
268 #define MGE_PORT_INT_MASK_EXT 0x46C
269 #define MGE_PORT_INT_EXT_TXBUF0 (1 << 0)
270 #define MGE_PORT_INT_EXT_TXERR0 (1 << 8)
271 #define MGE_PORT_INT_EXT_PHYSC (1 << 16)
272 #define MGE_PORT_INT_EXT_RXOR (1 << 18)
273 #define MGE_PORT_INT_EXT_TXUR (1 << 19)
274 #define MGE_PORT_INT_EXT_LC (1 << 20)
275 #define MGE_PORT_INT_EXT_IAR (1 << 23)
276 #define MGE_PORT_INT_EXT_SUM (1U << 31)
278 #define MGE_RX_FIFO_URGENT_TRSH 0x470
279 #define MGE_TX_FIFO_URGENT_TRSH 0x474
281 #define MGE_FIXED_PRIO_CONF 0x4dc
282 #define MGE_FIXED_PRIO_EN(q) (1 << (q))
284 #define MGE_RX_CUR_DESC_PTR(q) (0x60c + ((q)<<4))
286 #define MGE_RX_QUEUE_CMD 0x680
287 #define MGE_ENABLE_RXQ(q) (1 << ((q) & 0x7))
288 #define MGE_ENABLE_RXQ_ALL (0xff)
289 #define MGE_DISABLE_RXQ(q) (1 << (((q) & 0x7) + 8))
290 #define MGE_DISABLE_RXQ_ALL (0xff00)
292 #define MGE_TX_CUR_DESC_PTR 0x6c0
294 #define MGE_TX_TOKEN_COUNT(q) (0x700 + ((q)<<4))
295 #define MGE_TX_TOKEN_CONF(q) (0x704 + ((q)<<4))
296 #define MGE_TX_ARBITER_CONF(q) (0x704 + ((q)<<4))
298 #define MGE_MCAST_REG_NUMBER 64
299 #define MGE_DA_FILTER_SPEC_MCAST(i) (0x1400 + ((i) << 2))
300 #define MGE_DA_FILTER_OTH_MCAST(i) (0x1500 + ((i) << 2))
302 #define MGE_UCAST_REG_NUMBER 4
303 #define MGE_DA_FILTER_UCAST(i) (0x1600 + ((i) << 2))
306 /* TX descriptor bits */
307 #define MGE_TX_LLC_SNAP (1 << 9)
308 #define MGE_TX_NOT_FRAGMENT (1 << 10)
309 #define MGE_TX_VLAN_TAGGED (1 << 15)
310 #define MGE_TX_UDP (1 << 16)
311 #define MGE_TX_GEN_L4_CSUM (1 << 17)
312 #define MGE_TX_GEN_IP_CSUM (1 << 18)
313 #define MGE_TX_PADDING (1 << 19)
314 #define MGE_TX_LAST (1 << 20)
315 #define MGE_TX_FIRST (1 << 21)
316 #define MGE_TX_ETH_CRC (1 << 22)
317 #define MGE_TX_EN_INT (1 << 23)
319 #define MGE_TX_IP_HDR_SIZE(size) ((size << 11) & 0xFFFF)
321 /* RX descriptor bits */
322 #define MGE_ERR_SUMMARY (1 << 0)
323 #define MGE_ERR_MASK (3 << 1)
324 #define MGE_RX_L4_PROTO_MASK (3 << 21)
325 #define MGE_RX_L4_PROTO_TCP (0 << 21)
326 #define MGE_RX_L4_PROTO_UDP (1 << 21)
327 #define MGE_RX_L3_IS_IP (1 << 24)
328 #define MGE_RX_IP_OK (1 << 25)
329 #define MGE_RX_DESC_LAST (1 << 26)
330 #define MGE_RX_DESC_FIRST (1 << 27)
331 #define MGE_RX_ENABLE_INT (1 << 29)
332 #define MGE_RX_L4_CSUM_OK (1 << 30)
333 #define MGE_DMA_OWNED (1U << 31)
335 #define MGE_RX_IP_FRAGMENT (1 << 2)
337 #define MGE_RX_L4_IS_TCP(status) ((status & MGE_RX_L4_PROTO_MASK) \
338 == MGE_RX_L4_PROTO_TCP)
340 #define MGE_RX_L4_IS_UDP(status) ((status & MGE_RX_L4_PROTO_MASK) \
341 == MGE_RX_L4_PROTO_UDP)
344 #define MGE_TX_ERROR_LC (0 << 1) /* Late collision */
345 #define MGE_TX_ERROR_UR (1 << 1) /* Underrun error */
346 #define MGE_TX_ERROR_RL (2 << 1) /* Excessive collision */
349 #define MGE_RX_ERROR_CE (0 << 1) /* CRC error */
350 #define MGE_RX_ERROR_OR (1 << 1) /* Overrun error */
351 #define MGE_RX_ERROR_MF (2 << 1) /* Max frame lenght error */
352 #define MGE_RX_ERROR_RE (3 << 1) /* Resource error */
354 #endif /* __IF_MGE_H__ */