2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 * Driver for the Attansic/Atheros F1 10/100/1000 PHY.
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/socket.h>
43 #include <net/if_media.h>
45 #include <dev/mii/mii.h>
46 #include <dev/mii/miivar.h>
49 #include <dev/mii/atphyreg.h>
51 #include "miibus_if.h"
53 static int atphy_probe(device_t);
54 static int atphy_attach(device_t);
56 static device_method_t atphy_methods[] = {
57 /* Device interface. */
58 DEVMETHOD(device_probe, atphy_probe),
59 DEVMETHOD(device_attach, atphy_attach),
60 DEVMETHOD(device_detach, mii_phy_detach),
61 DEVMETHOD(device_shutdown, bus_generic_shutdown),
65 static devclass_t atphy_devclass;
66 static driver_t atphy_driver = {
69 sizeof(struct mii_softc)
72 DRIVER_MODULE(atphy, miibus, atphy_driver, atphy_devclass, 0, 0);
74 static int atphy_service(struct mii_softc *, struct mii_data *, int);
75 static void atphy_status(struct mii_softc *);
76 static void atphy_reset(struct mii_softc *);
77 static uint16_t atphy_anar(struct ifmedia_entry *);
78 static int atphy_setmedia(struct mii_softc *, int);
80 static const struct mii_phydesc atphys[] = {
81 MII_PHY_DESC(xxATHEROS, F1),
82 MII_PHY_DESC(xxATHEROS, F1_7),
83 MII_PHY_DESC(xxATHEROS, AR8021),
84 MII_PHY_DESC(xxATHEROS, F2),
88 static const struct mii_phy_funcs atphy_funcs = {
95 atphy_probe(device_t dev)
98 return (mii_phy_dev_probe(dev, atphys, BUS_PROBE_DEFAULT));
102 atphy_attach(device_t dev)
105 mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &atphy_funcs, 1);
110 atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
112 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
113 uint16_t anar, bmcr, bmsr;
120 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO ||
121 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
122 atphy_setmedia(sc, ife->ifm_media);
127 switch (IFM_SUBTYPE(ife->ifm_media)) {
135 bmcr = PHY_READ(sc, MII_BMCR);
138 * Due to an unknown reason powering down PHY resulted
139 * in unexpected results such as inaccessibility of
140 * hardware of freshly rebooted system. Disable
141 * powering down PHY until I got more information for
142 * Attansic/Atheros PHY hardwares.
144 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
150 anar = atphy_anar(ife);
151 if ((ife->ifm_media & IFM_FDX) != 0) {
153 if ((ife->ifm_media & IFM_FLOW) != 0 ||
154 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
155 anar |= ANAR_PAUSE_TOWARDS;
158 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX |
159 EXTSR_1000THDX)) != 0)
160 PHY_WRITE(sc, MII_100T2CR, 0);
161 PHY_WRITE(sc, MII_ANAR, anar | ANAR_CSMA);
164 * Reset the PHY so all changes take effect.
166 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN |
173 * Only used for autonegotiation.
175 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
182 * Read the status register twice; BMSR_LINK is latch-low.
184 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
185 if (bmsr & BMSR_LINK) {
190 /* Announce link loss right after it happens. */
191 if (sc->mii_ticks++ == 0)
193 if (sc->mii_ticks <= sc->mii_anegticks)
197 atphy_setmedia(sc, ife->ifm_media);
201 /* Update the media status. */
204 /* Callback if something changed. */
205 mii_phy_update(sc, cmd);
210 atphy_status(struct mii_softc *sc)
212 struct mii_data *mii = sc->mii_pdata;
213 uint32_t bmsr, bmcr, ssr;
215 mii->mii_media_status = IFM_AVALID;
216 mii->mii_media_active = IFM_ETHER;
218 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
219 if ((bmsr & BMSR_LINK) != 0)
220 mii->mii_media_status |= IFM_ACTIVE;
222 bmcr = PHY_READ(sc, MII_BMCR);
223 if ((bmcr & BMCR_ISO) != 0) {
224 mii->mii_media_active |= IFM_NONE;
225 mii->mii_media_status = 0;
229 if ((bmcr & BMCR_LOOP) != 0)
230 mii->mii_media_active |= IFM_LOOP;
232 ssr = PHY_READ(sc, ATPHY_SSR);
233 if ((ssr & ATPHY_SSR_SPD_DPLX_RESOLVED) == 0) {
234 /* Erg, still trying, I guess... */
235 mii->mii_media_active |= IFM_NONE;
239 switch (ssr & ATPHY_SSR_SPEED_MASK) {
240 case ATPHY_SSR_1000MBS:
241 mii->mii_media_active |= IFM_1000_T;
243 * atphy(4) has a valid link so reset mii_ticks.
244 * Resetting mii_ticks is needed in order to
245 * detect link loss after auto-negotiation.
249 case ATPHY_SSR_100MBS:
250 mii->mii_media_active |= IFM_100_TX;
253 case ATPHY_SSR_10MBS:
254 mii->mii_media_active |= IFM_10_T;
258 mii->mii_media_active |= IFM_NONE;
262 if ((ssr & ATPHY_SSR_DUPLEX) != 0)
263 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
265 mii->mii_media_active |= IFM_HDX;
267 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
268 (PHY_READ(sc, MII_100T2SR) & GTSR_MS_RES) != 0)
269 mii->mii_media_active |= IFM_ETH_MASTER;
273 atphy_reset(struct mii_softc *sc)
275 struct ifmedia_entry *ife = sc->mii_pdata->mii_media.ifm_cur;
279 /* Take PHY out of power down mode. */
280 PHY_WRITE(sc, 29, 0x29);
281 PHY_WRITE(sc, 30, 0);
283 reg = PHY_READ(sc, ATPHY_SCR);
284 /* Enable automatic crossover. */
285 reg |= ATPHY_SCR_AUTO_X_MODE;
286 /* Disable power down. */
287 reg &= ~ATPHY_SCR_MAC_PDOWN;
288 /* Enable CRS on Tx. */
289 reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;
290 /* Auto correction for reversed cable polarity. */
291 reg |= ATPHY_SCR_POLARITY_REVERSAL;
292 PHY_WRITE(sc, ATPHY_SCR, reg);
294 /* Workaround F1 bug to reset phy. */
295 atphy_setmedia(sc, ife == NULL ? IFM_AUTO : ife->ifm_media);
297 for (i = 0; i < 1000; i++) {
299 if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
305 atphy_anar(struct ifmedia_entry *ife)
310 switch (IFM_SUBTYPE(ife->ifm_media)) {
312 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
326 if ((ife->ifm_media & IFM_FDX) != 0) {
327 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX)
337 atphy_setmedia(struct mii_softc *sc, int media)
341 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
342 if ((IFM_SUBTYPE(media) == IFM_AUTO || (media & IFM_FDX) != 0) &&
343 ((media & IFM_FLOW) != 0 ||
344 (sc->mii_flags & MIIF_FORCEPAUSE) != 0))
345 anar |= ANAR_PAUSE_TOWARDS;
346 PHY_WRITE(sc, MII_ANAR, anar);
347 if ((sc->mii_extcapabilities &
348 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
349 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
351 else if (sc->mii_mpd_model == MII_MODEL_xxATHEROS_F1) {
353 * AR8132 has 10/100 PHY and the PHY uses the same
354 * model number of F1 gigabit PHY. The PHY has no
355 * ability to establish gigabit link so explicitly
356 * disable 1000baseT configuration for the PHY.
357 * Otherwise, there is a case that atphy(4) could
358 * not establish a link against gigabit link partner
359 * unless the link partner supports down-shifting.
361 PHY_WRITE(sc, MII_100T2CR, 0);
363 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
365 return (EJUSTRETURN);