sys/dev/mii/brgphy.c

   1 /*-
   2  * Copyright (c) 2000
   3  *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 /*
  37  * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
  38  */
  39
  40 #include <sys/param.h>
  41 #include <sys/systm.h>
  42 #include <sys/kernel.h>
  43 #include <sys/module.h>
  44 #include <sys/socket.h>
  45 #include <sys/bus.h>
  46
  47 #include <net/if.h>
  48 #include <net/ethernet.h>
  49 #include <net/if_media.h>
  50
  51 #include <dev/mii/mii.h>
  52 #include <dev/mii/miivar.h>
  53 #include "miidevs.h"
  54
  55 #include <dev/mii/brgphyreg.h>
  56 #include <net/if_arp.h>
  57 #include <machine/bus.h>
  58 #include <dev/bge/if_bgereg.h>
  59 #include <dev/bce/if_bcereg.h>
  60
  61 #include <dev/pci/pcireg.h>
  62 #include <dev/pci/pcivar.h>
  63
  64 #include "miibus_if.h"
  65
  66 static int brgphy_probe(device_t);
  67 static int brgphy_attach(device_t);
  68
  69 struct brgphy_softc {
  70         struct mii_softc mii_sc;
  71         int mii_oui;
  72         int mii_model;
  73         int mii_rev;
  74         int serdes_flags;       /* Keeps track of the serdes type used */
  75 #define BRGPHY_5706S    0x0001
  76 #define BRGPHY_5708S    0x0002
  77         int bce_phy_flags;              /* PHY flags transferred from the MAC driver */
  78 };
  79
  80 static device_method_t brgphy_methods[] = {
  81         /* device interface */
  82         DEVMETHOD(device_probe,         brgphy_probe),
  83         DEVMETHOD(device_attach,        brgphy_attach),
  84         DEVMETHOD(device_detach,        mii_phy_detach),
  85         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  86         { 0, 0 }
  87 };
  88
  89 static devclass_t brgphy_devclass;
  90
  91 static driver_t brgphy_driver = {
  92         "brgphy",
  93         brgphy_methods,
  94         sizeof(struct brgphy_softc)
  95 };
  96
  97 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
  98
  99 static int      brgphy_service(struct mii_softc *, struct mii_data *, int);
 100 static void     brgphy_setmedia(struct mii_softc *, int, int);
 101 static void     brgphy_status(struct mii_softc *);
 102 static void     brgphy_mii_phy_auto(struct mii_softc *);
 103 static void     brgphy_reset(struct mii_softc *);
 104 static void     brgphy_enable_loopback(struct mii_softc *);
 105 static void     bcm5401_load_dspcode(struct mii_softc *);
 106 static void     bcm5411_load_dspcode(struct mii_softc *);
 107 static void     brgphy_fixup_5704_a0_bug(struct mii_softc *);
 108 static void     brgphy_fixup_adc_bug(struct mii_softc *);
 109 static void     brgphy_fixup_adjust_trim(struct mii_softc *);
 110 static void     brgphy_fixup_ber_bug(struct mii_softc *);
 111 static void     brgphy_fixup_crc_bug(struct mii_softc *);
 112 static void     brgphy_fixup_jitter_bug(struct mii_softc *);
 113 static void     brgphy_ethernet_wirespeed(struct mii_softc *);
 114 static void     brgphy_jumbo_settings(struct mii_softc *, u_long);
 115
 116 static const struct mii_phydesc brgphys[] = {
 117         MII_PHY_DESC(xxBROADCOM, BCM5400),
 118         MII_PHY_DESC(xxBROADCOM, BCM5401),
 119         MII_PHY_DESC(xxBROADCOM, BCM5411),
 120         MII_PHY_DESC(xxBROADCOM, BCM5701),
 121         MII_PHY_DESC(xxBROADCOM, BCM5703),
 122         MII_PHY_DESC(xxBROADCOM, BCM5704),
 123         MII_PHY_DESC(xxBROADCOM, BCM5705),
 124         MII_PHY_DESC(xxBROADCOM, BCM5706),
 125         MII_PHY_DESC(xxBROADCOM, BCM5714),
 126         MII_PHY_DESC(xxBROADCOM, BCM5750),
 127         MII_PHY_DESC(xxBROADCOM, BCM5752),
 128         MII_PHY_DESC(xxBROADCOM, BCM5754),
 129         MII_PHY_DESC(xxBROADCOM, BCM5780),
 130         MII_PHY_DESC(xxBROADCOM, BCM5708C),
 131         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755),
 132         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787),
 133         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S),
 134         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722),
 135         MII_PHY_DESC(BROADCOM2, BCM5906),
 136         MII_PHY_END
 137 };
 138
 139
 140 /* Search for our PHY in the list of known PHYs */
 141 static int
 142 brgphy_probe(device_t dev)
 143 {
 144         return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
 145 }
 146
 147 /* Attach the PHY to the MII bus */
 148 static int
 149 brgphy_attach(device_t dev)
 150 {
 151         struct brgphy_softc *bsc;
 152         struct bge_softc *bge_sc = NULL;
 153         struct bce_softc *bce_sc = NULL;
 154         struct mii_softc *sc;
 155         struct mii_attach_args *ma;
 156         struct mii_data *mii;
 157         struct ifnet *ifp;
 158         int fast_ether;
 159
 160         bsc = device_get_softc(dev);
 161         sc = &bsc->mii_sc;
 162         ma = device_get_ivars(dev);
 163         sc->mii_dev = device_get_parent(dev);
 164         mii = device_get_softc(sc->mii_dev);
 165         LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
 166
 167         /* Initialize mii_softc structure */
 168         sc->mii_inst = mii->mii_instance;
 169         sc->mii_phy = ma->mii_phyno;
 170         sc->mii_service = brgphy_service;
 171         sc->mii_pdata = mii;
 172         sc->mii_anegticks = MII_ANEGTICKS_GIGE;
 173         sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
 174         mii->mii_instance++;
 175
 176         /* Initialize brgphy_softc structure */
 177         bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
 178         bsc->mii_model = MII_MODEL(ma->mii_id2);
 179         bsc->mii_rev = MII_REV(ma->mii_id2);
 180         bsc->serdes_flags = 0;
 181
 182         fast_ether = 0;
 183
 184         if (bootverbose)
 185                 device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
 186                     bsc->mii_oui, bsc->mii_model, bsc->mii_rev);
 187
 188         /* Handle any special cases based on the PHY ID */
 189         switch (bsc->mii_oui) {
 190         case MII_OUI_BROADCOM:
 191         case MII_OUI_BROADCOM2:
 192                 break;
 193         case MII_OUI_xxBROADCOM:
 194                 switch (bsc->mii_model) {
 195                         case MII_MODEL_xxBROADCOM_BCM5706:
 196                                 /*
 197                                  * The 5464 PHY used in the 5706 supports both copper
 198                                  * and fiber interfaces over GMII.  Need to check the
 199                                  * shadow registers to see which mode is actually
 200                                  * in effect, and therefore whether we have 5706C or
 201                                  * 5706S.
 202                                  */
 203                                 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
 204                                         BRGPHY_SHADOW_1C_MODE_CTRL);
 205                                 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
 206                                         BRGPHY_SHADOW_1C_ENA_1000X) {
 207                                         bsc->serdes_flags |= BRGPHY_5706S;
 208                                         sc->mii_flags |= MIIF_HAVEFIBER;
 209                                 }
 210                                 break;
 211                 } break;
 212         case MII_OUI_xxBROADCOM_ALT1:
 213                 switch (bsc->mii_model) {
 214                         case MII_MODEL_xxBROADCOM_ALT1_BCM5708S:
 215                                 bsc->serdes_flags |= BRGPHY_5708S;
 216                                 sc->mii_flags |= MIIF_HAVEFIBER;
 217                                 break;
 218                 } break;
 219         default:
 220                 device_printf(dev, "Unrecognized OUI for PHY!\n");
 221         }
 222
 223         ifp = sc->mii_pdata->mii_ifp;
 224
 225         /* Find the MAC driver associated with this PHY. */
 226         if (strcmp(ifp->if_dname, "bge") == 0)  {
 227                 bge_sc = ifp->if_softc;
 228         } else if (strcmp(ifp->if_dname, "bce") == 0) {
 229                 bce_sc = ifp->if_softc;
 230         }
 231
 232         /* Todo: Need to add additional controllers such as 5787F */
 233         /* The 590x chips are 10/100 only. */
 234         if (bge_sc &&
 235             pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID &&
 236             (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 ||
 237             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2 ||
 238             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906 ||
 239             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906M)) {
 240                 fast_ether = 1;
 241                 sc->mii_anegticks = MII_ANEGTICKS;
 242         }
 243
 244         brgphy_reset(sc);
 245
 246         sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
 247         if (sc->mii_capabilities & BMSR_EXTSTAT)
 248                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 249         device_printf(dev, " ");
 250
 251 #define ADD(m, c)       ifmedia_add(&mii->mii_media, (m), (c), NULL)
 252
 253         /* Create an instance of Ethernet media. */
 254         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), BMCR_ISO);
 255
 256         /* Add the supported media types */
 257         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 258                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst),
 259                         BRGPHY_S10);
 260                 printf("10baseT, ");
 261                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
 262                         BRGPHY_S10 | BRGPHY_BMCR_FDX);
 263                 printf("10baseT-FDX, ");
 264                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst),
 265                         BRGPHY_S100);
 266                 printf("100baseTX, ");
 267                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
 268                         BRGPHY_S100 | BRGPHY_BMCR_FDX);
 269                 printf("100baseTX-FDX, ");
 270                 if (fast_ether == 0) {
 271                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
 272                                 BRGPHY_S1000);
 273                         printf("1000baseT, ");
 274                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst),
 275                                 BRGPHY_S1000 | BRGPHY_BMCR_FDX);
 276                         printf("1000baseT-FDX, ");
 277                 }
 278         } else {
 279                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
 280                         BRGPHY_S1000 | BRGPHY_BMCR_FDX);
 281                 printf("1000baseSX-FDX, ");
 282                 /* 2.5G support is a software enabled feature on the 5708S */
 283                 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 284                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0);
 285                         printf("2500baseSX-FDX, ");
 286                 }
 287         }
 288
 289         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
 290         printf("auto\n");
 291
 292 #undef ADD
 293         MIIBUS_MEDIAINIT(sc->mii_dev);
 294
 295         /* If MFW running on bce, bring the PHY up now. */
 296         if (bce_sc && (bce_sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
 297                 brgphy_mii_phy_auto(sc);
 298                 brgphy_status(sc);
 299         }
 300
 301         return (0);
 302 }
 303
 304 static int
 305 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 306 {
 307         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 308         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 309         int error = 0;
 310         int val;
 311
 312         switch (cmd) {
 313         case MII_POLLSTAT:
 314                 /* If we're not polling our PHY instance, just return. */
 315                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 316                         goto brgphy_service_exit;
 317                 break;
 318         case MII_MEDIACHG:
 319                 /*
 320                  * If the media indicates a different PHY instance,
 321                  * isolate ourselves.
 322                  */
 323                 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
 324                         PHY_WRITE(sc, MII_BMCR,
 325                             PHY_READ(sc, MII_BMCR) | BMCR_ISO);
 326                         goto brgphy_service_exit;
 327                 }
 328
 329                 /* If the interface is not up, don't do anything. */
 330                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 331                         break;
 332
 333                 /* Todo: Why is this here?  Is it really needed? */
 334                 brgphy_reset(sc);       /* XXX hardware bug work-around */
 335
 336                 switch (IFM_SUBTYPE(ife->ifm_media)) {
 337                 case IFM_AUTO:
 338                         brgphy_mii_phy_auto(sc);
 339                         break;
 340                 case IFM_2500_SX:
 341                 case IFM_1000_SX:
 342                 case IFM_1000_T:
 343                 case IFM_100_TX:
 344                 case IFM_10_T:
 345                         brgphy_setmedia(sc, ife->ifm_media,
 346                             mii->mii_ifp->if_flags & IFF_LINK0);
 347                         break;
 348                 default:
 349                         error = EINVAL;
 350                         goto brgphy_service_exit;
 351                 }
 352                 break;
 353         case MII_TICK:
 354                 /* Bail if we're not currently selected. */
 355                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 356                         goto brgphy_service_exit;
 357
 358                 /* Bail if the interface isn't up. */
 359                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 360                         goto brgphy_service_exit;
 361
 362
 363                 /* Bail if autoneg isn't in process. */
 364                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
 365                         sc->mii_ticks = 0;
 366                         break;
 367                 }
 368
 369                 /*
 370                  * Check to see if we have link.  If we do, we don't
 371                  * need to restart the autonegotiation process.
 372                  */
 373                 val     = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
 374                 if (val & BMSR_LINK) {
 375                         sc->mii_ticks = 0;      /* Reset autoneg timer. */
 376                         break;
 377                 }
 378
 379                 /* Announce link loss right after it happens. */
 380                 if (sc->mii_ticks++ == 0)
 381                         break;
 382
 383                 /* Only retry autonegotiation every mii_anegticks seconds. */
 384                 if (sc->mii_ticks <= sc->mii_anegticks)
 385                         break;
 386
 387
 388                 /* Retry autonegotiation */
 389                 sc->mii_ticks = 0;
 390                 brgphy_mii_phy_auto(sc);
 391                 break;
 392         }
 393
 394         /* Update the media status. */
 395         brgphy_status(sc);
 396
 397         /*
 398          * Callback if something changed. Note that we need to poke
 399          * the DSP on the Broadcom PHYs if the media changes.
 400          */
 401         if (sc->mii_media_active != mii->mii_media_active ||
 402             sc->mii_media_status != mii->mii_media_status ||
 403             cmd == MII_MEDIACHG) {
 404                 switch (bsc->mii_oui) {
 405                 case MII_OUI_BROADCOM:
 406                         break;
 407                 case MII_OUI_xxBROADCOM:
 408                         switch (bsc->mii_model) {
 409                         case MII_MODEL_xxBROADCOM_BCM5400:
 410                                 bcm5401_load_dspcode(sc);
 411                                 break;
 412                         case MII_MODEL_xxBROADCOM_BCM5401:
 413                                 if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
 414                                         bcm5401_load_dspcode(sc);
 415                                 break;
 416                         case MII_MODEL_xxBROADCOM_BCM5411:
 417                                 bcm5411_load_dspcode(sc);
 418                                 break;
 419                         }
 420                         break;
 421                 case MII_OUI_xxBROADCOM_ALT1:
 422                         break;
 423                 }
 424         }
 425         mii_phy_update(sc, cmd);
 426 brgphy_service_exit:
 427         return (error);
 428 }
 429
 430 static void
 431 brgphy_setmedia(struct mii_softc *sc, int media, int master)
 432 {
 433         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 434         int bmcr = 0, gig;
 435
 436         switch (IFM_SUBTYPE(media)) {
 437         case IFM_2500_SX:
 438                 break;
 439         case IFM_1000_SX:
 440         case IFM_1000_T:
 441                 bmcr = BRGPHY_S1000;
 442                 break;
 443         case IFM_100_TX:
 444                 bmcr = BRGPHY_S100;
 445                 break;
 446         case IFM_10_T:
 447         default:
 448                 bmcr = BRGPHY_S10;
 449                 break;
 450         }
 451         if ((media & IFM_GMASK) == IFM_FDX) {
 452                 bmcr |= BRGPHY_BMCR_FDX;
 453                 gig = BRGPHY_1000CTL_AFD;
 454         } else {
 455                 gig = BRGPHY_1000CTL_AHD;
 456         }
 457
 458         brgphy_enable_loopback(sc);
 459         PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
 460         PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
 461         PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
 462
 463         if ((IFM_SUBTYPE(media) != IFM_1000_T) && (IFM_SUBTYPE(media) != IFM_1000_SX))
 464                 goto brgphy_setmedia_exit;
 465
 466         PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
 467         PHY_WRITE(sc, BRGPHY_MII_BMCR,
 468             bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 469
 470         if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
 471                 goto brgphy_setmedia_exit;
 472
 473         /*
 474          * When setting the link manually, one side must be the master and
 475          * the other the slave. However ifmedia doesn't give us a good way
 476          * to specify this, so we fake it by using one of the LINK flags.
 477          * If LINK0 is set, we program the PHY to be a master, otherwise
 478          * it's a slave.
 479          */
 480         if (master) {
 481                 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
 482                     gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC);
 483         } else {
 484                 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
 485                     gig | BRGPHY_1000CTL_MSE);
 486         }
 487 brgphy_setmedia_exit:
 488         return;
 489 }
 490
 491 /* Set the media status based on the PHY settings. */
 492 /* IFM_FLAG0 = 0 (RX flow control disabled | 1 (enabled) */
 493 /* IFM_FLAG1 = 0 (TX flow control disabled | 1 (enabled) */
 494 static void
 495 brgphy_status(struct mii_softc *sc)
 496 {
 497         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 498         struct mii_data *mii = sc->mii_pdata;
 499         int aux, bmcr, bmsr, anar, anlpar, xstat, val;
 500
 501
 502         mii->mii_media_status = IFM_AVALID;
 503         mii->mii_media_active = IFM_ETHER;
 504
 505         bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
 506         bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
 507         anar = PHY_READ(sc, BRGPHY_MII_ANAR);
 508         anlpar = PHY_READ(sc, BRGPHY_MII_ANLPAR);
 509
 510         /* Loopback is enabled. */
 511         if (bmcr & BRGPHY_BMCR_LOOP) {
 512
 513                 mii->mii_media_active |= IFM_LOOP;
 514         }
 515
 516         /* Autoneg is still in progress. */
 517         if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
 518             (bmsr & BRGPHY_BMSR_ACOMP) == 0) {
 519                 /* Erg, still trying, I guess... */
 520                 mii->mii_media_active |= IFM_NONE;
 521                 goto brgphy_status_exit;
 522         }
 523
 524         /* Autoneg is enabled and complete, link should be up. */
 525         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 526                 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
 527
 528                 /* If copper link is up, get the negotiated speed/duplex. */
 529                 if (aux & BRGPHY_AUXSTS_LINK) {
 530                         mii->mii_media_status |= IFM_ACTIVE;
 531                         switch (aux & BRGPHY_AUXSTS_AN_RES) {
 532                         case BRGPHY_RES_1000FD:
 533                                 mii->mii_media_active |= IFM_1000_T | IFM_FDX;  break;
 534                         case BRGPHY_RES_1000HD:
 535                                 mii->mii_media_active |= IFM_1000_T | IFM_HDX;  break;
 536                         case BRGPHY_RES_100FD:
 537                                 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
 538                         case BRGPHY_RES_100T4:
 539                                 mii->mii_media_active |= IFM_100_T4; break;
 540                         case BRGPHY_RES_100HD:
 541                                 mii->mii_media_active |= IFM_100_TX | IFM_HDX;  break;
 542                         case BRGPHY_RES_10FD:
 543                                 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
 544                         case BRGPHY_RES_10HD:
 545                                 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
 546                         default:
 547                                 mii->mii_media_active |= IFM_NONE; break;
 548                         }
 549                 }
 550         } else {
 551                 /* If serdes link is up, get the negotiated speed/duplex. */
 552                 if (bmsr & BRGPHY_BMSR_LINK) {
 553                         mii->mii_media_status |= IFM_ACTIVE;
 554                 }
 555
 556                 /* Check the link speed/duplex based on the PHY type. */
 557                 if (bsc->serdes_flags & BRGPHY_5706S) {
 558                         mii->mii_media_active |= IFM_1000_SX;
 559
 560                         /* If autoneg enabled, read negotiated duplex settings */
 561                         if (bmcr & BRGPHY_BMCR_AUTOEN) {
 562                                 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
 563                                 if (val & BRGPHY_SERDES_ANAR_FDX)
 564                                         mii->mii_media_active |= IFM_FDX;
 565                                 else
 566                                         mii->mii_media_active |= IFM_HDX;
 567                         }
 568
 569                 } else if (bsc->serdes_flags & BRGPHY_5708S) {
 570                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
 571                         xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
 572
 573                         /* Todo: Create #defines for hard coded values */
 574                         switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
 575                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
 576                                 mii->mii_media_active |= IFM_10_FL; break;
 577                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
 578                                 mii->mii_media_active |= IFM_100_FX; break;
 579                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
 580                                 mii->mii_media_active |= IFM_1000_SX; break;
 581                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
 582                                 mii->mii_media_active |= IFM_2500_SX; break;
 583                         }
 584
 585                         if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
 586                                 mii->mii_media_active |= IFM_FDX;
 587                         else
 588                                 mii->mii_media_active |= IFM_HDX;
 589                 }
 590         }
 591
 592 #if 0
 593         /* Todo: Change bge/bce to use these settings. */
 594
 595         /* Fetch flow control settings from the PHY */
 596         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 597                 /* Set FLAG0 is RX is enabled and FLAG1 if TX is enabled */
 598                 if ((anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANLPAR_PC)) {
 599                         mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;
 600                 } else if (!(anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANAR_ASP) &&
 601                     (anlpar & BRPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) {
 602                         mii->mii_media_active |= IFM_FLAG1;
 603                 } else if ((anar & BRGPHY_ANAR_PC) && (anar & BRGPHY_ANAR_ASP) &&
 604                     !(anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) {
 605                         mii->mii_media_active |= IFM_FLAG0;
 606                 }
 607         }
 608         /* Todo: Add support for fiber settings too. */
 609 #endif
 610
 611
 612 brgphy_status_exit:
 613         return;
 614 }
 615
 616 static void
 617 brgphy_mii_phy_auto(struct mii_softc *sc)
 618 {
 619         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 620         int ktcr = 0;
 621
 622         brgphy_reset(sc);
 623
 624         /* Enable flow control in the advertisement register. */
 625         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 626                 /* Pause capability advertisement (pause capable & asymmetric) */
 627                 PHY_WRITE(sc, BRGPHY_MII_ANAR,
 628                 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA |
 629                 BRGPHY_ANAR_ASP | BRGPHY_ANAR_PC);
 630         } else {
 631                 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, BRGPHY_SERDES_ANAR_FDX |
 632                         BRGPHY_SERDES_ANAR_HDX | BRGPHY_SERDES_ANAR_BOTH_PAUSE);
 633         }
 634
 635         /* Enable speed in the 1000baseT control register */
 636         ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
 637         if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
 638                 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
 639         PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
 640         ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
 641
 642         /* Start autonegotiation */
 643         PHY_WRITE(sc, BRGPHY_MII_BMCR,BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 644         PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
 645
 646 }
 647
 648 /* Enable loopback to force the link down. */
 649 static void
 650 brgphy_enable_loopback(struct mii_softc *sc)
 651 {
 652         int i;
 653
 654         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
 655         for (i = 0; i < 15000; i++) {
 656                 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
 657                         break;
 658                 DELAY(10);
 659         }
 660 }
 661
 662 /* Turn off tap power management on 5401. */
 663 static void
 664 bcm5401_load_dspcode(struct mii_softc *sc)
 665 {
 666         static const struct {
 667                 int             reg;
 668                 uint16_t        val;
 669         } dspcode[] = {
 670                 { BRGPHY_MII_AUXCTL,            0x0c20 },
 671                 { BRGPHY_MII_DSP_ADDR_REG,      0x0012 },
 672                 { BRGPHY_MII_DSP_RW_PORT,       0x1804 },
 673                 { BRGPHY_MII_DSP_ADDR_REG,      0x0013 },
 674                 { BRGPHY_MII_DSP_RW_PORT,       0x1204 },
 675                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 676                 { BRGPHY_MII_DSP_RW_PORT,       0x0132 },
 677                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 678                 { BRGPHY_MII_DSP_RW_PORT,       0x0232 },
 679                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 680                 { BRGPHY_MII_DSP_RW_PORT,       0x0a20 },
 681                 { 0,                            0 },
 682         };
 683         int i;
 684
 685         for (i = 0; dspcode[i].reg != 0; i++)
 686                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 687         DELAY(40);
 688 }
 689
 690 static void
 691 bcm5411_load_dspcode(struct mii_softc *sc)
 692 {
 693         static const struct {
 694                 int             reg;
 695                 uint16_t        val;
 696         } dspcode[] = {
 697                 { 0x1c,                         0x8c23 },
 698                 { 0x1c,                         0x8ca3 },
 699                 { 0x1c,                         0x8c23 },
 700                 { 0,                            0 },
 701         };
 702         int i;
 703
 704         for (i = 0; dspcode[i].reg != 0; i++)
 705                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 706 }
 707
 708 static void
 709 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
 710 {
 711         static const struct {
 712                 int             reg;
 713                 uint16_t        val;
 714         } dspcode[] = {
 715                 { 0x1c,                         0x8d68 },
 716                 { 0x1c,                         0x8d68 },
 717                 { 0,                            0 },
 718         };
 719         int i;
 720
 721         for (i = 0; dspcode[i].reg != 0; i++)
 722                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 723 }
 724
 725 static void
 726 brgphy_fixup_adc_bug(struct mii_softc *sc)
 727 {
 728         static const struct {
 729                 int             reg;
 730                 uint16_t        val;
 731         } dspcode[] = {
 732                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 733                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 734                 { BRGPHY_MII_DSP_RW_PORT,       0x2aaa },
 735                 { 0,                            0 },
 736         };
 737         int i;
 738
 739         for (i = 0; dspcode[i].reg != 0; i++)
 740                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 741 }
 742
 743 static void
 744 brgphy_fixup_adjust_trim(struct mii_softc *sc)
 745 {
 746         static const struct {
 747                 int             reg;
 748                 uint16_t        val;
 749         } dspcode[] = {
 750                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 751                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 752                 { BRGPHY_MII_DSP_RW_PORT,       0x110b },
 753                 { BRGPHY_MII_TEST1,                     0x0014 },
 754                 { BRGPHY_MII_AUXCTL,            0x0400 },
 755                 { 0,                            0 },
 756         };
 757         int i;
 758
 759         for (i = 0; dspcode[i].reg != 0; i++)
 760                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 761 }
 762
 763 static void
 764 brgphy_fixup_ber_bug(struct mii_softc *sc)
 765 {
 766         static const struct {
 767                 int             reg;
 768                 uint16_t        val;
 769         } dspcode[] = {
 770                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 771                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 772                 { BRGPHY_MII_DSP_RW_PORT,       0x310b },
 773                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 774                 { BRGPHY_MII_DSP_RW_PORT,       0x9506 },
 775                 { BRGPHY_MII_DSP_ADDR_REG,      0x401f },
 776                 { BRGPHY_MII_DSP_RW_PORT,       0x14e2 },
 777                 { BRGPHY_MII_AUXCTL,            0x0400 },
 778                 { 0,                            0 },
 779         };
 780         int i;
 781
 782         for (i = 0; dspcode[i].reg != 0; i++)
 783                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 784 }
 785
 786 static void
 787 brgphy_fixup_crc_bug(struct mii_softc *sc)
 788 {
 789         static const struct {
 790                 int             reg;
 791                 uint16_t        val;
 792         } dspcode[] = {
 793                 { BRGPHY_MII_DSP_RW_PORT,       0x0a75 },
 794                 { 0x1c,                         0x8c68 },
 795                 { 0x1c,                         0x8d68 },
 796                 { 0x1c,                         0x8c68 },
 797                 { 0,                            0 },
 798         };
 799         int i;
 800
 801         for (i = 0; dspcode[i].reg != 0; i++)
 802                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 803 }
 804
 805 static void
 806 brgphy_fixup_jitter_bug(struct mii_softc *sc)
 807 {
 808         static const struct {
 809                 int             reg;
 810                 uint16_t        val;
 811         } dspcode[] = {
 812                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 813                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 814                 { BRGPHY_MII_DSP_RW_PORT,       0x010b },
 815                 { BRGPHY_MII_AUXCTL,            0x0400 },
 816                 { 0,                            0 },
 817         };
 818         int i;
 819
 820         for (i = 0; dspcode[i].reg != 0; i++)
 821                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 822 }
 823
 824 static void
 825 brgphy_ethernet_wirespeed(struct mii_softc *sc)
 826 {
 827         uint32_t        val;
 828
 829         /* Enable Ethernet@WireSpeed. */
 830         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
 831         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 832         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
 833 }
 834
 835 static void
 836 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
 837 {
 838         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 839         uint32_t        val;
 840
 841         /* Set or clear jumbo frame settings in the PHY. */
 842         if (mtu > ETHER_MAX_LEN) {
 843                 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
 844                         /* BCM5401 PHY cannot read-modify-write. */
 845                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
 846                 } else {
 847                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 848                         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 849                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 850                             val | BRGPHY_AUXCTL_LONG_PKT);
 851                 }
 852
 853                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 854                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 855                     val | BRGPHY_PHY_EXTCTL_HIGH_LA);
 856         } else {
 857                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 858                 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 859                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 860                     val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
 861
 862                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 863                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 864                         val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
 865         }
 866 }
 867
 868 static void
 869 brgphy_reset(struct mii_softc *sc)
 870 {
 871         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 872         struct bge_softc *bge_sc = NULL;
 873         struct bce_softc *bce_sc = NULL;
 874         struct ifnet *ifp;
 875
 876         mii_phy_reset(sc);
 877
 878         /* Handle any PHY specific procedures to finish the reset. */
 879         switch (bsc->mii_oui) {
 880         case MII_OUI_BROADCOM:
 881                 break;
 882         case MII_OUI_xxBROADCOM:
 883                 switch (bsc->mii_model) {
 884                 case MII_MODEL_xxBROADCOM_BCM5400:
 885                         bcm5401_load_dspcode(sc);
 886                         break;
 887                 case MII_MODEL_xxBROADCOM_BCM5401:
 888                         if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
 889                                 bcm5401_load_dspcode(sc);
 890                         break;
 891                 case MII_MODEL_xxBROADCOM_BCM5411:
 892                         bcm5411_load_dspcode(sc);
 893                         break;
 894                 }
 895                 break;
 896         case MII_OUI_xxBROADCOM_ALT1:
 897                 break;
 898         }
 899
 900         ifp = sc->mii_pdata->mii_ifp;
 901
 902         /* Find the driver associated with this PHY. */
 903         if (strcmp(ifp->if_dname, "bge") == 0)  {
 904                 bge_sc = ifp->if_softc;
 905         } else if (strcmp(ifp->if_dname, "bce") == 0) {
 906                 bce_sc = ifp->if_softc;
 907         }
 908
 909         /* Handle any bge (NetXtreme/NetLink) workarounds. */
 910         if (bge_sc) {
 911                 /* Fix up various bugs */
 912                 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG)
 913                         brgphy_fixup_5704_a0_bug(sc);
 914                 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG)
 915                         brgphy_fixup_adc_bug(sc);
 916                 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM)
 917                         brgphy_fixup_adjust_trim(sc);
 918                 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG)
 919                         brgphy_fixup_ber_bug(sc);
 920                 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG)
 921                         brgphy_fixup_crc_bug(sc);
 922                 if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG)
 923                         brgphy_fixup_jitter_bug(sc);
 924
 925                 brgphy_jumbo_settings(sc, ifp->if_mtu);
 926
 927                 if (bge_sc->bge_flags & BGE_FLAG_WIRESPEED)
 928                         brgphy_ethernet_wirespeed(sc);
 929
 930                 /* Enable Link LED on Dell boxes */
 931                 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) {
 932                         PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 933                             PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
 934                             ~BRGPHY_PHY_EXTCTL_3_LED);
 935                 }
 936
 937                 /* Adjust output voltage (From Linux driver) */
 938                 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
 939                         PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
 940
 941         /* Handle any bce (NetXtreme II) workarounds. */
 942         } else if (bce_sc) {
 943
 944                 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
 945                         BCE_CHIP_BOND_ID(bce_sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
 946
 947                         /* Store autoneg capabilities/results in digital block (Page 0) */
 948                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
 949                         PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
 950                                 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
 951                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
 952
 953                         /* Enable fiber mode and autodetection */
 954                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
 955                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
 956                                 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
 957                                 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
 958
 959                         /* Enable parallel detection */
 960                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
 961                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
 962                                 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
 963
 964                         /* Advertise 2.5G support through next page during autoneg */
 965                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 966                                 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
 967                                         PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
 968                                         BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
 969
 970                         /* Increase TX signal amplitude */
 971                         if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
 972                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
 973                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
 974                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
 975                                         BRGPHY_5708S_TX_MISC_PG5);
 976                                 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
 977                                         PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
 978                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
 979                                         BRGPHY_5708S_DIG_PG0);
 980                         }
 981
 982                         /* Backplanes use special driver/pre-driver/pre-emphasis values. */
 983                         if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
 984                                 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
 985                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
 986                                                 BRGPHY_5708S_TX_MISC_PG5);
 987                                         PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
 988                                                 bce_sc->bce_port_hw_cfg &
 989                                                 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
 990                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
 991                                                 BRGPHY_5708S_DIG_PG0);
 992                         }
 993                 } else {
 994                         brgphy_fixup_ber_bug(sc);
 995                         brgphy_jumbo_settings(sc, ifp->if_mtu);
 996                         brgphy_ethernet_wirespeed(sc);
 997                 }
 998
 999         }
1000 }
1001