sys/dev/mii/brgphy.c

   1 /*-
   2  * Copyright (c) 2000
   3  *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 /*
  37  * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
  38  */
  39
  40 #include <sys/param.h>
  41 #include <sys/systm.h>
  42 #include <sys/kernel.h>
  43 #include <sys/module.h>
  44 #include <sys/socket.h>
  45 #include <sys/bus.h>
  46
  47 #include <net/if.h>
  48 #include <net/ethernet.h>
  49 #include <net/if_media.h>
  50
  51 #include <dev/mii/mii.h>
  52 #include <dev/mii/miivar.h>
  53 #include "miidevs.h"
  54
  55 #include <dev/mii/brgphyreg.h>
  56 #include <net/if_arp.h>
  57 #include <machine/bus.h>
  58 #include <dev/bge/if_bgereg.h>
  59 #include <dev/bce/if_bcereg.h>
  60
  61 #include <dev/pci/pcireg.h>
  62 #include <dev/pci/pcivar.h>
  63
  64 #include "miibus_if.h"
  65
  66 static int brgphy_probe(device_t);
  67 static int brgphy_attach(device_t);
  68
  69 struct brgphy_softc {
  70         struct mii_softc mii_sc;
  71         int mii_oui;
  72         int mii_model;
  73         int mii_rev;
  74         int serdes_flags;       /* Keeps track of the serdes type used */
  75 #define BRGPHY_5706S            0x0001
  76 #define BRGPHY_5708S            0x0002
  77 #define BRGPHY_NOANWAIT         0x0004
  78 #define BRGPHY_5709S            0x0008
  79         int bce_phy_flags;      /* PHY flags transferred from the MAC driver */
  80 };
  81
  82 static device_method_t brgphy_methods[] = {
  83         /* device interface */
  84         DEVMETHOD(device_probe,         brgphy_probe),
  85         DEVMETHOD(device_attach,        brgphy_attach),
  86         DEVMETHOD(device_detach,        mii_phy_detach),
  87         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  88         { 0, 0 }
  89 };
  90
  91 static devclass_t brgphy_devclass;
  92
  93 static driver_t brgphy_driver = {
  94         "brgphy",
  95         brgphy_methods,
  96         sizeof(struct brgphy_softc)
  97 };
  98
  99 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
 100
 101 static int      brgphy_service(struct mii_softc *, struct mii_data *, int);
 102 static void     brgphy_setmedia(struct mii_softc *, int, int);
 103 static void     brgphy_status(struct mii_softc *);
 104 static void     brgphy_mii_phy_auto(struct mii_softc *);
 105 static void     brgphy_reset(struct mii_softc *);
 106 static void     brgphy_enable_loopback(struct mii_softc *);
 107 static void     bcm5401_load_dspcode(struct mii_softc *);
 108 static void     bcm5411_load_dspcode(struct mii_softc *);
 109 static void     bcm54k2_load_dspcode(struct mii_softc *);
 110 static void     brgphy_fixup_5704_a0_bug(struct mii_softc *);
 111 static void     brgphy_fixup_adc_bug(struct mii_softc *);
 112 static void     brgphy_fixup_adjust_trim(struct mii_softc *);
 113 static void     brgphy_fixup_ber_bug(struct mii_softc *);
 114 static void     brgphy_fixup_crc_bug(struct mii_softc *);
 115 static void     brgphy_fixup_jitter_bug(struct mii_softc *);
 116 static void     brgphy_ethernet_wirespeed(struct mii_softc *);
 117 static void     brgphy_jumbo_settings(struct mii_softc *, u_long);
 118
 119 static const struct mii_phydesc brgphys[] = {
 120         MII_PHY_DESC(xxBROADCOM, BCM5400),
 121         MII_PHY_DESC(xxBROADCOM, BCM5401),
 122         MII_PHY_DESC(xxBROADCOM, BCM5411),
 123         MII_PHY_DESC(xxBROADCOM, BCM54K2),
 124         MII_PHY_DESC(xxBROADCOM, BCM5701),
 125         MII_PHY_DESC(xxBROADCOM, BCM5703),
 126         MII_PHY_DESC(xxBROADCOM, BCM5704),
 127         MII_PHY_DESC(xxBROADCOM, BCM5705),
 128         MII_PHY_DESC(xxBROADCOM, BCM5706),
 129         MII_PHY_DESC(xxBROADCOM, BCM5714),
 130         MII_PHY_DESC(xxBROADCOM, BCM5750),
 131         MII_PHY_DESC(xxBROADCOM, BCM5752),
 132         MII_PHY_DESC(xxBROADCOM, BCM5754),
 133         MII_PHY_DESC(xxBROADCOM, BCM5780),
 134         MII_PHY_DESC(xxBROADCOM, BCM5708C),
 135         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755),
 136         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787),
 137         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S),
 138         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX),
 139         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722),
 140         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784),
 141         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C),
 142         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761),
 143         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S),
 144         MII_PHY_DESC(xxBROADCOM_ALT2, BCM5717C),
 145         MII_PHY_DESC(BROADCOM2, BCM5906),
 146         MII_PHY_END
 147 };
 148
 149 #define HS21_PRODUCT_ID "IBM eServer BladeCenter HS21"
 150 #define HS21_BCM_CHIPID 0x57081021
 151
 152 static int
 153 detect_hs21(struct bce_softc *bce_sc)
 154 {
 155         char *sysenv;
 156
 157         if (bce_sc->bce_chipid != HS21_BCM_CHIPID)
 158                 return (0);
 159         sysenv = getenv("smbios.system.product");
 160         if (sysenv == NULL)
 161                 return (0);
 162         if (strncmp(sysenv, HS21_PRODUCT_ID, strlen(HS21_PRODUCT_ID)) != 0)
 163                 return (0);
 164         return (1);
 165 }
 166
 167 /* Search for our PHY in the list of known PHYs */
 168 static int
 169 brgphy_probe(device_t dev)
 170 {
 171         return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
 172 }
 173
 174 /* Attach the PHY to the MII bus */
 175 static int
 176 brgphy_attach(device_t dev)
 177 {
 178         struct brgphy_softc *bsc;
 179         struct bge_softc *bge_sc = NULL;
 180         struct bce_softc *bce_sc = NULL;
 181         struct mii_softc *sc;
 182         struct mii_attach_args *ma;
 183         struct mii_data *mii;
 184         struct ifnet *ifp;
 185         int fast_ether;
 186
 187         bsc = device_get_softc(dev);
 188         sc = &bsc->mii_sc;
 189         ma = device_get_ivars(dev);
 190         sc->mii_dev = device_get_parent(dev);
 191         mii = ma->mii_data;
 192         LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
 193
 194         /* Initialize mii_softc structure */
 195         sc->mii_flags = miibus_get_flags(dev);
 196         sc->mii_inst = mii->mii_instance++;
 197         sc->mii_phy = ma->mii_phyno;
 198         sc->mii_service = brgphy_service;
 199         sc->mii_pdata = mii;
 200
 201         /*
 202          * At least some variants wedge when isolating, at least some also
 203          * don't support loopback.
 204          */
 205         sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
 206         sc->mii_anegticks = MII_ANEGTICKS_GIGE;
 207
 208         /* Initialize brgphy_softc structure */
 209         bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
 210         bsc->mii_model = MII_MODEL(ma->mii_id2);
 211         bsc->mii_rev = MII_REV(ma->mii_id2);
 212         bsc->serdes_flags = 0;
 213
 214         fast_ether = 0;
 215
 216         if (bootverbose)
 217                 device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
 218                     bsc->mii_oui, bsc->mii_model, bsc->mii_rev);
 219
 220         /* Handle any special cases based on the PHY ID */
 221         switch (bsc->mii_oui) {
 222         case MII_OUI_BROADCOM:
 223         case MII_OUI_BROADCOM2:
 224                 break;
 225         case MII_OUI_xxBROADCOM:
 226                 switch (bsc->mii_model) {
 227                 case MII_MODEL_xxBROADCOM_BCM5706:
 228                 case MII_MODEL_xxBROADCOM_BCM5714:
 229                         /*
 230                          * The 5464 PHY used in the 5706 supports both copper
 231                          * and fiber interfaces over GMII.  Need to check the
 232                          * shadow registers to see which mode is actually
 233                          * in effect, and therefore whether we have 5706C or
 234                          * 5706S.
 235                          */
 236                         PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
 237                                 BRGPHY_SHADOW_1C_MODE_CTRL);
 238                         if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
 239                                 BRGPHY_SHADOW_1C_ENA_1000X) {
 240                                 bsc->serdes_flags |= BRGPHY_5706S;
 241                                 sc->mii_flags |= MIIF_HAVEFIBER;
 242                         }
 243                         break;
 244                 } break;
 245         case MII_OUI_xxBROADCOM_ALT1:
 246                 switch (bsc->mii_model) {
 247                 case MII_MODEL_xxBROADCOM_ALT1_BCM5708S:
 248                         bsc->serdes_flags |= BRGPHY_5708S;
 249                         sc->mii_flags |= MIIF_HAVEFIBER;
 250                         break;
 251                 case MII_MODEL_xxBROADCOM_ALT1_BCM5709S:
 252                         bsc->serdes_flags |= BRGPHY_5709S;
 253                         sc->mii_flags |= MIIF_HAVEFIBER;
 254                         break;
 255                 }
 256                 break;
 257         case MII_OUI_xxBROADCOM_ALT2:
 258                 /* No special handling yet. */
 259                 break;
 260         default:
 261                 device_printf(dev, "Unrecognized OUI for PHY!\n");
 262         }
 263
 264         ifp = sc->mii_pdata->mii_ifp;
 265
 266         /* Find the MAC driver associated with this PHY. */
 267         if (strcmp(ifp->if_dname, "bge") == 0)  {
 268                 bge_sc = ifp->if_softc;
 269         } else if (strcmp(ifp->if_dname, "bce") == 0) {
 270                 bce_sc = ifp->if_softc;
 271         }
 272
 273         /* Todo: Need to add additional controllers such as 5906 & 5787F */
 274         /* The 590x chips are 10/100 only. */
 275         if (bge_sc &&
 276             pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID &&
 277             (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 ||
 278             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2 ||
 279             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906 ||
 280             pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5906M)) {
 281                 fast_ether = 1;
 282                 sc->mii_anegticks = MII_ANEGTICKS;
 283         }
 284
 285         brgphy_reset(sc);
 286
 287         /* Read the PHY's capabilities. */
 288         sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
 289         if (sc->mii_capabilities & BMSR_EXTSTAT)
 290                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 291         device_printf(dev, " ");
 292
 293 #define ADD(m, c)       ifmedia_add(&mii->mii_media, (m), (c), NULL)
 294
 295         /* Add the supported media types */
 296         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 297                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst),
 298                         BRGPHY_S10);
 299                 printf("10baseT, ");
 300                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
 301                         BRGPHY_S10 | BRGPHY_BMCR_FDX);
 302                 printf("10baseT-FDX, ");
 303                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst),
 304                         BRGPHY_S100);
 305                 printf("100baseTX, ");
 306                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
 307                         BRGPHY_S100 | BRGPHY_BMCR_FDX);
 308                 printf("100baseTX-FDX, ");
 309                 if (fast_ether == 0) {
 310                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
 311                                 BRGPHY_S1000);
 312                         printf("1000baseT, ");
 313                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst),
 314                                 BRGPHY_S1000 | BRGPHY_BMCR_FDX);
 315                         printf("1000baseT-FDX, ");
 316                 }
 317         } else {
 318                 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
 319                         BRGPHY_S1000 | BRGPHY_BMCR_FDX);
 320                 printf("1000baseSX-FDX, ");
 321                 /* 2.5G support is a software enabled feature on the 5708S and 5709S. */
 322                 if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 323                         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0);
 324                         printf("2500baseSX-FDX, ");
 325                 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
 326                     (detect_hs21(bce_sc) != 0)) {
 327                         /*
 328                          * There appears to be certain silicon revision
 329                          * in IBM HS21 blades that is having issues with
 330                          * this driver wating for the auto-negotiation to
 331                          * complete. This happens with a specific chip id
 332                          * only and when the 1000baseSX-FDX is the only
 333                          * mode. Workaround this issue since it's unlikely
 334                          * to be ever addressed.
 335                          */
 336                         printf("auto-neg workaround, ");
 337                         bsc->serdes_flags |= BRGPHY_NOANWAIT;
 338                 }
 339         }
 340
 341         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
 342         printf("auto\n");
 343
 344 #undef ADD
 345         MIIBUS_MEDIAINIT(sc->mii_dev);
 346         return (0);
 347 }
 348
 349 static int
 350 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 351 {
 352         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 353         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 354         int val;
 355
 356         switch (cmd) {
 357         case MII_POLLSTAT:
 358                 break;
 359         case MII_MEDIACHG:
 360                 /* If the interface is not up, don't do anything. */
 361                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 362                         break;
 363
 364                 /* Todo: Why is this here?  Is it really needed? */
 365                 brgphy_reset(sc);       /* XXX hardware bug work-around */
 366
 367                 switch (IFM_SUBTYPE(ife->ifm_media)) {
 368                 case IFM_AUTO:
 369                         brgphy_mii_phy_auto(sc);
 370                         break;
 371                 case IFM_2500_SX:
 372                 case IFM_1000_SX:
 373                 case IFM_1000_T:
 374                 case IFM_100_TX:
 375                 case IFM_10_T:
 376                         brgphy_setmedia(sc, ife->ifm_media,
 377                             mii->mii_ifp->if_flags & IFF_LINK0);
 378                         break;
 379                 default:
 380                         return (EINVAL);
 381                 }
 382                 break;
 383         case MII_TICK:
 384                 /* Bail if the interface isn't up. */
 385                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 386                         return (0);
 387
 388
 389                 /* Bail if autoneg isn't in process. */
 390                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
 391                         sc->mii_ticks = 0;
 392                         break;
 393                 }
 394
 395                 /*
 396                  * Check to see if we have link.  If we do, we don't
 397                  * need to restart the autonegotiation process.
 398                  */
 399                 val     = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
 400                 if (val & BMSR_LINK) {
 401                         sc->mii_ticks = 0;      /* Reset autoneg timer. */
 402                         break;
 403                 }
 404
 405                 /* Announce link loss right after it happens. */
 406                 if (sc->mii_ticks++ == 0)
 407                         break;
 408
 409                 /* Only retry autonegotiation every mii_anegticks seconds. */
 410                 if (sc->mii_ticks <= sc->mii_anegticks)
 411                         break;
 412
 413
 414                 /* Retry autonegotiation */
 415                 sc->mii_ticks = 0;
 416                 brgphy_mii_phy_auto(sc);
 417                 break;
 418         }
 419
 420         /* Update the media status. */
 421         brgphy_status(sc);
 422
 423         /*
 424          * Callback if something changed. Note that we need to poke
 425          * the DSP on the Broadcom PHYs if the media changes.
 426          */
 427         if (sc->mii_media_active != mii->mii_media_active ||
 428             sc->mii_media_status != mii->mii_media_status ||
 429             cmd == MII_MEDIACHG) {
 430                 switch (bsc->mii_oui) {
 431                 case MII_OUI_BROADCOM:
 432                         break;
 433                 case MII_OUI_xxBROADCOM:
 434                         switch (bsc->mii_model) {
 435                         case MII_MODEL_xxBROADCOM_BCM5400:
 436                                 bcm5401_load_dspcode(sc);
 437                                 break;
 438                         case MII_MODEL_xxBROADCOM_BCM5401:
 439                                 if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
 440                                         bcm5401_load_dspcode(sc);
 441                                 break;
 442                         case MII_MODEL_xxBROADCOM_BCM5411:
 443                                 bcm5411_load_dspcode(sc);
 444                                 break;
 445                         case MII_MODEL_xxBROADCOM_BCM54K2:
 446                                 bcm54k2_load_dspcode(sc);
 447                                 break;
 448                         }
 449                         break;
 450                 case MII_OUI_xxBROADCOM_ALT1:
 451                         break;
 452                 }
 453         }
 454         mii_phy_update(sc, cmd);
 455         return (0);
 456 }
 457
 458
 459 /****************************************************************************/
 460 /* Sets the PHY link speed.                                                 */
 461 /*                                                                          */
 462 /* Returns:                                                                 */
 463 /*   None                                                                   */
 464 /****************************************************************************/
 465 static void
 466 brgphy_setmedia(struct mii_softc *sc, int media, int master)
 467 {
 468         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 469         int bmcr = 0, gig;
 470
 471         /* Calculate the value for the BMCR register. */
 472         switch (IFM_SUBTYPE(media)) {
 473         case IFM_2500_SX:
 474                 break;
 475         case IFM_1000_SX:
 476         case IFM_1000_T:
 477                 bmcr = BRGPHY_S1000;
 478                 break;
 479         case IFM_100_TX:
 480                 bmcr = BRGPHY_S100;
 481                 break;
 482         case IFM_10_T:
 483         default:
 484                 bmcr = BRGPHY_S10;
 485                 break;
 486         }
 487
 488         /* Calculate duplex settings for 1000BasetT/1000BaseX. */
 489         if ((media & IFM_GMASK) == IFM_FDX) {
 490                 bmcr |= BRGPHY_BMCR_FDX;
 491                 gig = BRGPHY_1000CTL_AFD;
 492         } else {
 493                 gig = BRGPHY_1000CTL_AHD;
 494         }
 495
 496         /* Force loopback to disconnect PHY for Ethernet medium. */
 497         brgphy_enable_loopback(sc);
 498
 499         /* Disable 1000BaseT advertisements. */
 500         PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
 501         /* Disable 10/100 advertisements. */
 502         PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
 503         /* Write forced link speed. */
 504         PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
 505
 506         /* If 10/100 only then configuration is complete. */
 507         if ((IFM_SUBTYPE(media) != IFM_1000_T) && (IFM_SUBTYPE(media) != IFM_1000_SX))
 508                 goto brgphy_setmedia_exit;
 509
 510         /* Set duplex speed advertisement for 1000BaseT/1000BaseX. */
 511         PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
 512         /* Restart auto-negotiation for 1000BaseT/1000BaseX. */
 513         PHY_WRITE(sc, BRGPHY_MII_BMCR,
 514             bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 515
 516         /* If not 5701 PHY then configuration is complete. */
 517         if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
 518                 goto brgphy_setmedia_exit;
 519
 520         /*
 521          * When setting the link manually, one side must be the master and
 522          * the other the slave. However ifmedia doesn't give us a good way
 523          * to specify this, so we fake it by using one of the LINK flags.
 524          * If LINK0 is set, we program the PHY to be a master, otherwise
 525          * it's a slave.
 526          */
 527         if (master) {
 528                 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
 529                     gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC);
 530         } else {
 531                 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
 532                     gig | BRGPHY_1000CTL_MSE);
 533         }
 534
 535 brgphy_setmedia_exit:
 536         return;
 537 }
 538
 539 /****************************************************************************/
 540 /* Set the media status based on the PHY settings.                          */
 541 /* IFM_FLAG0 = 0 (RX flow control disabled) | 1 (enabled)                   */
 542 /* IFM_FLAG1 = 0 (TX flow control disabled) | 1 (enabled)                   */
 543 /*                                                                          */
 544 /* Returns:                                                                 */
 545 /*   None                                                                   */
 546 /****************************************************************************/
 547 static void
 548 brgphy_status(struct mii_softc *sc)
 549 {
 550         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 551         struct mii_data *mii = sc->mii_pdata;
 552         int aux, bmcr, bmsr, anar, anlpar, xstat, val;
 553
 554
 555         mii->mii_media_status = IFM_AVALID;
 556         mii->mii_media_active = IFM_ETHER;
 557
 558         bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
 559         bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
 560         anar = PHY_READ(sc, BRGPHY_MII_ANAR);
 561         anlpar = PHY_READ(sc, BRGPHY_MII_ANLPAR);
 562
 563         /* Loopback is enabled. */
 564         if (bmcr & BRGPHY_BMCR_LOOP) {
 565
 566                 mii->mii_media_active |= IFM_LOOP;
 567         }
 568
 569         /* Autoneg is still in progress. */
 570         if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
 571             (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
 572             (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
 573                 /* Erg, still trying, I guess... */
 574                 mii->mii_media_active |= IFM_NONE;
 575                 goto brgphy_status_exit;
 576         }
 577
 578         /* Autoneg is enabled and complete, link should be up. */
 579         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 580                 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
 581
 582                 /* If copper link is up, get the negotiated speed/duplex. */
 583                 if (aux & BRGPHY_AUXSTS_LINK) {
 584                         mii->mii_media_status |= IFM_ACTIVE;
 585                         switch (aux & BRGPHY_AUXSTS_AN_RES) {
 586                         case BRGPHY_RES_1000FD:
 587                                 mii->mii_media_active |= IFM_1000_T | IFM_FDX;  break;
 588                         case BRGPHY_RES_1000HD:
 589                                 mii->mii_media_active |= IFM_1000_T | IFM_HDX;  break;
 590                         case BRGPHY_RES_100FD:
 591                                 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
 592                         case BRGPHY_RES_100T4:
 593                                 mii->mii_media_active |= IFM_100_T4; break;
 594                         case BRGPHY_RES_100HD:
 595                                 mii->mii_media_active |= IFM_100_TX | IFM_HDX;  break;
 596                         case BRGPHY_RES_10FD:
 597                                 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
 598                         case BRGPHY_RES_10HD:
 599                                 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
 600                         default:
 601                                 mii->mii_media_active |= IFM_NONE; break;
 602                         }
 603                 }
 604         } else {
 605                 /* If serdes link is up, get the negotiated speed/duplex. */
 606                 if (bmsr & BRGPHY_BMSR_LINK) {
 607                         mii->mii_media_status |= IFM_ACTIVE;
 608                 }
 609
 610                 /* Check the link speed/duplex based on the PHY type. */
 611                 if (bsc->serdes_flags & BRGPHY_5706S) {
 612                         mii->mii_media_active |= IFM_1000_SX;
 613
 614                         /* If autoneg enabled, read negotiated duplex settings */
 615                         if (bmcr & BRGPHY_BMCR_AUTOEN) {
 616                                 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
 617                                 if (val & BRGPHY_SERDES_ANAR_FDX)
 618                                         mii->mii_media_active |= IFM_FDX;
 619                                 else
 620                                         mii->mii_media_active |= IFM_HDX;
 621                         }
 622
 623                 } else if (bsc->serdes_flags & BRGPHY_5708S) {
 624                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
 625                         xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
 626
 627                         /* Check for MRBE auto-negotiated speed results. */
 628                         switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
 629                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
 630                                 mii->mii_media_active |= IFM_10_FL; break;
 631                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
 632                                 mii->mii_media_active |= IFM_100_FX; break;
 633                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
 634                                 mii->mii_media_active |= IFM_1000_SX; break;
 635                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
 636                                 mii->mii_media_active |= IFM_2500_SX; break;
 637                         }
 638
 639                         /* Check for MRBE auto-negotiated duplex results. */
 640                         if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
 641                                 mii->mii_media_active |= IFM_FDX;
 642                         else
 643                                 mii->mii_media_active |= IFM_HDX;
 644
 645                 } else if (bsc->serdes_flags & BRGPHY_5709S) {
 646
 647                         /* Select GP Status Block of the AN MMD, get autoneg results. */
 648                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
 649                         xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
 650
 651                         /* Restore IEEE0 block (assumed in all brgphy(4) code). */
 652                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
 653
 654                         /* Check for MRBE auto-negotiated speed results. */
 655                         switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
 656                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
 657                                         mii->mii_media_active |= IFM_10_FL; break;
 658                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
 659                                         mii->mii_media_active |= IFM_100_FX; break;
 660                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
 661                                         mii->mii_media_active |= IFM_1000_SX; break;
 662                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
 663                                         mii->mii_media_active |= IFM_2500_SX; break;
 664                         }
 665
 666                         /* Check for MRBE auto-negotiated duplex results. */
 667                         if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
 668                                 mii->mii_media_active |= IFM_FDX;
 669                         else
 670                                 mii->mii_media_active |= IFM_HDX;
 671                 }
 672
 673         }
 674
 675         /* Todo: Change bge to use these settings. */
 676
 677         /* Fetch flow control settings from the copper PHY. */
 678         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 679                 /* Set FLAG0 if RX is enabled and FLAG1 if TX is enabled */
 680                 if ((anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANLPAR_PC)) {
 681                         mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;
 682                 } else if (!(anar & BRGPHY_ANAR_PC) && (anlpar & BRGPHY_ANAR_ASP) &&
 683                     (anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) {
 684                         mii->mii_media_active |= IFM_FLAG1;
 685                 } else if ((anar & BRGPHY_ANAR_PC) && (anar & BRGPHY_ANAR_ASP) &&
 686                     !(anlpar & BRGPHY_ANLPAR_PC) && (anlpar & BRGPHY_ANLPAR_ASP)) {
 687                         mii->mii_media_active |= IFM_FLAG0;
 688                 }
 689         }
 690
 691         /* Todo: Add support for fiber settings too. */
 692
 693
 694 brgphy_status_exit:
 695         return;
 696 }
 697
 698 static void
 699 brgphy_mii_phy_auto(struct mii_softc *sc)
 700 {
 701         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 702         int ktcr = 0;
 703
 704         brgphy_reset(sc);
 705
 706         /* Enable flow control in the advertisement register. */
 707         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 708                 /* Pause capability advertisement (pause capable & asymmetric) */
 709                 PHY_WRITE(sc, BRGPHY_MII_ANAR,
 710                 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA |
 711                 BRGPHY_ANAR_ASP | BRGPHY_ANAR_PC);
 712         } else {
 713                 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, BRGPHY_SERDES_ANAR_FDX |
 714                         BRGPHY_SERDES_ANAR_HDX | BRGPHY_SERDES_ANAR_BOTH_PAUSE);
 715         }
 716
 717         /* Enable speed in the 1000baseT control register */
 718         ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
 719         if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
 720                 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
 721         PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
 722         ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
 723
 724         /* Start autonegotiation */
 725         PHY_WRITE(sc, BRGPHY_MII_BMCR,BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 726         PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
 727
 728 }
 729
 730
 731 /* Enable loopback to force the link down. */
 732 static void
 733 brgphy_enable_loopback(struct mii_softc *sc)
 734 {
 735         int i;
 736
 737         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
 738         for (i = 0; i < 15000; i++) {
 739                 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
 740                         break;
 741                 DELAY(10);
 742         }
 743 }
 744
 745 /* Turn off tap power management on 5401. */
 746 static void
 747 bcm5401_load_dspcode(struct mii_softc *sc)
 748 {
 749         static const struct {
 750                 int             reg;
 751                 uint16_t        val;
 752         } dspcode[] = {
 753                 { BRGPHY_MII_AUXCTL,            0x0c20 },
 754                 { BRGPHY_MII_DSP_ADDR_REG,      0x0012 },
 755                 { BRGPHY_MII_DSP_RW_PORT,       0x1804 },
 756                 { BRGPHY_MII_DSP_ADDR_REG,      0x0013 },
 757                 { BRGPHY_MII_DSP_RW_PORT,       0x1204 },
 758                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 759                 { BRGPHY_MII_DSP_RW_PORT,       0x0132 },
 760                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 761                 { BRGPHY_MII_DSP_RW_PORT,       0x0232 },
 762                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 763                 { BRGPHY_MII_DSP_RW_PORT,       0x0a20 },
 764                 { 0,                            0 },
 765         };
 766         int i;
 767
 768         for (i = 0; dspcode[i].reg != 0; i++)
 769                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 770         DELAY(40);
 771 }
 772
 773 static void
 774 bcm5411_load_dspcode(struct mii_softc *sc)
 775 {
 776         static const struct {
 777                 int             reg;
 778                 uint16_t        val;
 779         } dspcode[] = {
 780                 { 0x1c,                         0x8c23 },
 781                 { 0x1c,                         0x8ca3 },
 782                 { 0x1c,                         0x8c23 },
 783                 { 0,                            0 },
 784         };
 785         int i;
 786
 787         for (i = 0; dspcode[i].reg != 0; i++)
 788                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 789 }
 790
 791 void
 792 bcm54k2_load_dspcode(struct mii_softc *sc)
 793 {
 794         static const struct {
 795                 int             reg;
 796                 uint16_t        val;
 797         } dspcode[] = {
 798                 { 4,                            0x01e1 },
 799                 { 9,                            0x0300 },
 800                 { 0,                            0 },
 801         };
 802         int i;
 803
 804         for (i = 0; dspcode[i].reg != 0; i++)
 805                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 806
 807 }
 808
 809 static void
 810 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
 811 {
 812         static const struct {
 813                 int             reg;
 814                 uint16_t        val;
 815         } dspcode[] = {
 816                 { 0x1c,                         0x8d68 },
 817                 { 0x1c,                         0x8d68 },
 818                 { 0,                            0 },
 819         };
 820         int i;
 821
 822         for (i = 0; dspcode[i].reg != 0; i++)
 823                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 824 }
 825
 826 static void
 827 brgphy_fixup_adc_bug(struct mii_softc *sc)
 828 {
 829         static const struct {
 830                 int             reg;
 831                 uint16_t        val;
 832         } dspcode[] = {
 833                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 834                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 835                 { BRGPHY_MII_DSP_RW_PORT,       0x2aaa },
 836                 { 0,                            0 },
 837         };
 838         int i;
 839
 840         for (i = 0; dspcode[i].reg != 0; i++)
 841                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 842 }
 843
 844 static void
 845 brgphy_fixup_adjust_trim(struct mii_softc *sc)
 846 {
 847         static const struct {
 848                 int             reg;
 849                 uint16_t        val;
 850         } dspcode[] = {
 851                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 852                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 853                 { BRGPHY_MII_DSP_RW_PORT,       0x110b },
 854                 { BRGPHY_MII_TEST1,                     0x0014 },
 855                 { BRGPHY_MII_AUXCTL,            0x0400 },
 856                 { 0,                            0 },
 857         };
 858         int i;
 859
 860         for (i = 0; dspcode[i].reg != 0; i++)
 861                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 862 }
 863
 864 static void
 865 brgphy_fixup_ber_bug(struct mii_softc *sc)
 866 {
 867         static const struct {
 868                 int             reg;
 869                 uint16_t        val;
 870         } dspcode[] = {
 871                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 872                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 873                 { BRGPHY_MII_DSP_RW_PORT,       0x310b },
 874                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 875                 { BRGPHY_MII_DSP_RW_PORT,       0x9506 },
 876                 { BRGPHY_MII_DSP_ADDR_REG,      0x401f },
 877                 { BRGPHY_MII_DSP_RW_PORT,       0x14e2 },
 878                 { BRGPHY_MII_AUXCTL,            0x0400 },
 879                 { 0,                            0 },
 880         };
 881         int i;
 882
 883         for (i = 0; dspcode[i].reg != 0; i++)
 884                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 885 }
 886
 887 static void
 888 brgphy_fixup_crc_bug(struct mii_softc *sc)
 889 {
 890         static const struct {
 891                 int             reg;
 892                 uint16_t        val;
 893         } dspcode[] = {
 894                 { BRGPHY_MII_DSP_RW_PORT,       0x0a75 },
 895                 { 0x1c,                         0x8c68 },
 896                 { 0x1c,                         0x8d68 },
 897                 { 0x1c,                         0x8c68 },
 898                 { 0,                            0 },
 899         };
 900         int i;
 901
 902         for (i = 0; dspcode[i].reg != 0; i++)
 903                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 904 }
 905
 906 static void
 907 brgphy_fixup_jitter_bug(struct mii_softc *sc)
 908 {
 909         static const struct {
 910                 int             reg;
 911                 uint16_t        val;
 912         } dspcode[] = {
 913                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 914                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 915                 { BRGPHY_MII_DSP_RW_PORT,       0x010b },
 916                 { BRGPHY_MII_AUXCTL,            0x0400 },
 917                 { 0,                            0 },
 918         };
 919         int i;
 920
 921         for (i = 0; dspcode[i].reg != 0; i++)
 922                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 923 }
 924
 925
 926 static void
 927 brgphy_fixup_disable_early_dac(struct mii_softc *sc)
 928 {
 929         uint32_t val;
 930
 931         PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
 932         val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
 933         val &= ~(1 << 8);
 934         PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
 935
 936 }
 937
 938
 939 static void
 940 brgphy_ethernet_wirespeed(struct mii_softc *sc)
 941 {
 942         uint32_t        val;
 943
 944         /* Enable Ethernet@WireSpeed. */
 945         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
 946         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 947         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
 948 }
 949
 950
 951 static void
 952 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
 953 {
 954         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 955         uint32_t        val;
 956
 957         /* Set or clear jumbo frame settings in the PHY. */
 958         if (mtu > ETHER_MAX_LEN) {
 959                 if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
 960                         /* BCM5401 PHY cannot read-modify-write. */
 961                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
 962                 } else {
 963                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 964                         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 965                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 966                             val | BRGPHY_AUXCTL_LONG_PKT);
 967                 }
 968
 969                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 970                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 971                     val | BRGPHY_PHY_EXTCTL_HIGH_LA);
 972         } else {
 973                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 974                 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 975                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 976                     val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
 977
 978                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 979                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 980                         val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
 981         }
 982 }
 983
 984 static void
 985 brgphy_reset(struct mii_softc *sc)
 986 {
 987         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 988         struct bge_softc *bge_sc = NULL;
 989         struct bce_softc *bce_sc = NULL;
 990         struct ifnet *ifp;
 991     int val;
 992
 993         /* Perform a standard PHY reset. */
 994         mii_phy_reset(sc);
 995
 996         /* Handle any PHY specific procedures following the reset. */
 997         switch (bsc->mii_oui) {
 998         case MII_OUI_BROADCOM:
 999                 break;
1000         case MII_OUI_xxBROADCOM:
1001                 switch (bsc->mii_model) {
1002                 case MII_MODEL_xxBROADCOM_BCM5400:
1003                         bcm5401_load_dspcode(sc);
1004                         break;
1005                 case MII_MODEL_xxBROADCOM_BCM5401:
1006                         if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
1007                                 bcm5401_load_dspcode(sc);
1008                         break;
1009                 case MII_MODEL_xxBROADCOM_BCM5411:
1010                         bcm5411_load_dspcode(sc);
1011                         break;
1012                 case MII_MODEL_xxBROADCOM_BCM54K2:
1013                         bcm54k2_load_dspcode(sc);
1014                         break;
1015                 }
1016                 break;
1017         case MII_OUI_xxBROADCOM_ALT1:
1018         case MII_OUI_xxBROADCOM_ALT2:
1019                 break;
1020         }
1021
1022         ifp = sc->mii_pdata->mii_ifp;
1023
1024         /* Find the driver associated with this PHY. */
1025         if (strcmp(ifp->if_dname, "bge") == 0)  {
1026                 bge_sc = ifp->if_softc;
1027         } else if (strcmp(ifp->if_dname, "bce") == 0) {
1028                 bce_sc = ifp->if_softc;
1029         }
1030
1031         /* Handle any bge (NetXtreme/NetLink) workarounds. */
1032         if (bge_sc) {
1033                 /* Fix up various bugs */
1034                 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
1035                         brgphy_fixup_5704_a0_bug(sc);
1036                 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
1037                         brgphy_fixup_adc_bug(sc);
1038                 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
1039                         brgphy_fixup_adjust_trim(sc);
1040                 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
1041                         brgphy_fixup_ber_bug(sc);
1042                 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
1043                         brgphy_fixup_crc_bug(sc);
1044                 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
1045                         brgphy_fixup_jitter_bug(sc);
1046
1047                 brgphy_jumbo_settings(sc, ifp->if_mtu);
1048
1049                 if (bge_sc->bge_phy_flags & BGE_PHY_WIRESPEED)
1050                         brgphy_ethernet_wirespeed(sc);
1051
1052                 /* Enable Link LED on Dell boxes */
1053                 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
1054                         PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
1055                             PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
1056                             ~BRGPHY_PHY_EXTCTL_3_LED);
1057                 }
1058
1059                 /* Adjust output voltage (From Linux driver) */
1060                 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
1061                         PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
1062
1063         /* Handle any bce (NetXtreme II) workarounds. */
1064         } else if (bce_sc) {
1065
1066                 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
1067                         (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1068
1069                         /* Store autoneg capabilities/results in digital block (Page 0) */
1070                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
1071                         PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
1072                                 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
1073                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
1074
1075                         /* Enable fiber mode and autodetection */
1076                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
1077                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
1078                                 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
1079                                 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
1080
1081                         /* Enable parallel detection */
1082                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
1083                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
1084                                 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
1085
1086                         /* Advertise 2.5G support through next page during autoneg */
1087                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1088                                 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
1089                                         PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
1090                                         BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
1091
1092                         /* Increase TX signal amplitude */
1093                         if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
1094                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
1095                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
1096                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1097                                         BRGPHY_5708S_TX_MISC_PG5);
1098                                 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
1099                                         PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
1100                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1101                                         BRGPHY_5708S_DIG_PG0);
1102                         }
1103
1104                         /* Backplanes use special driver/pre-driver/pre-emphasis values. */
1105                         if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
1106                                 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
1107                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1108                                                 BRGPHY_5708S_TX_MISC_PG5);
1109                                         PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1110                                                 bce_sc->bce_port_hw_cfg &
1111                                                 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1112                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1113                                                 BRGPHY_5708S_DIG_PG0);
1114                         }
1115                 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
1116                         (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1117
1118                         /* Select the SerDes Digital block of the AN MMD. */
1119                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
1120                         val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
1121                         val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
1122                         val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
1123                         PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
1124
1125                         /* Select the Over 1G block of the AN MMD. */
1126                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
1127
1128                         /* Enable autoneg "Next Page" to advertise 2.5G support. */
1129                         val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
1130                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1131                                 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1132                         else
1133                                 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1134                         PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
1135
1136                         /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
1137                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
1138
1139                         /* Enable MRBE speed autoneg. */
1140                         val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
1141                         val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
1142                             BRGPHY_MRBE_MSG_PG5_NP_T2;
1143                         PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
1144
1145                         /* Select the Clause 73 User B0 block of the AN MMD. */
1146                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
1147
1148                         /* Enable MRBE speed autoneg. */
1149                         PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
1150                             BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
1151                             BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
1152                             BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
1153
1154                         /* Restore IEEE0 block (assumed in all brgphy(4) code). */
1155                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
1156
1157         } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1158                         if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1159                                 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1160                                 brgphy_fixup_disable_early_dac(sc);
1161
1162                         brgphy_jumbo_settings(sc, ifp->if_mtu);
1163                         brgphy_ethernet_wirespeed(sc);
1164                 } else {
1165                         brgphy_fixup_ber_bug(sc);
1166                         brgphy_jumbo_settings(sc, ifp->if_mtu);
1167                         brgphy_ethernet_wirespeed(sc);
1168                 }
1169
1170         }
1171 }