3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
46 #include <sys/taskqueue.h>
49 #include <net/if_var.h>
50 #include <net/ethernet.h>
51 #include <net/if_media.h>
53 #include <dev/mii/mii.h>
54 #include <dev/mii/miivar.h>
57 #include <dev/mii/brgphyreg.h>
58 #include <net/if_arp.h>
59 #include <machine/bus.h>
60 #include <dev/bge/if_bgereg.h>
61 #include <dev/bce/if_bcereg.h>
63 #include <dev/pci/pcireg.h>
64 #include <dev/pci/pcivar.h>
66 #include "miibus_if.h"
68 static int brgphy_probe(device_t);
69 static int brgphy_attach(device_t);
72 struct mii_softc mii_sc;
73 int serdes_flags; /* Keeps track of the serdes type used */
74 #define BRGPHY_5706S 0x0001
75 #define BRGPHY_5708S 0x0002
76 #define BRGPHY_NOANWAIT 0x0004
77 #define BRGPHY_5709S 0x0008
78 int bce_phy_flags; /* PHY flags transferred from the MAC driver */
81 static device_method_t brgphy_methods[] = {
82 /* device interface */
83 DEVMETHOD(device_probe, brgphy_probe),
84 DEVMETHOD(device_attach, brgphy_attach),
85 DEVMETHOD(device_detach, mii_phy_detach),
86 DEVMETHOD(device_shutdown, bus_generic_shutdown),
90 static devclass_t brgphy_devclass;
92 static driver_t brgphy_driver = {
95 sizeof(struct brgphy_softc)
98 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
100 static int brgphy_service(struct mii_softc *, struct mii_data *, int);
101 static void brgphy_setmedia(struct mii_softc *, int);
102 static void brgphy_status(struct mii_softc *);
103 static void brgphy_mii_phy_auto(struct mii_softc *, int);
104 static void brgphy_reset(struct mii_softc *);
105 static void brgphy_enable_loopback(struct mii_softc *);
106 static void bcm5401_load_dspcode(struct mii_softc *);
107 static void bcm5411_load_dspcode(struct mii_softc *);
108 static void bcm54k2_load_dspcode(struct mii_softc *);
109 static void brgphy_fixup_5704_a0_bug(struct mii_softc *);
110 static void brgphy_fixup_adc_bug(struct mii_softc *);
111 static void brgphy_fixup_adjust_trim(struct mii_softc *);
112 static void brgphy_fixup_ber_bug(struct mii_softc *);
113 static void brgphy_fixup_crc_bug(struct mii_softc *);
114 static void brgphy_fixup_jitter_bug(struct mii_softc *);
115 static void brgphy_ethernet_wirespeed(struct mii_softc *);
116 static void brgphy_jumbo_settings(struct mii_softc *, u_long);
118 static const struct mii_phydesc brgphys[] = {
119 MII_PHY_DESC(BROADCOM, BCM5400),
120 MII_PHY_DESC(BROADCOM, BCM5401),
121 MII_PHY_DESC(BROADCOM, BCM5411),
122 MII_PHY_DESC(BROADCOM, BCM54K2),
123 MII_PHY_DESC(BROADCOM, BCM5701),
124 MII_PHY_DESC(BROADCOM, BCM5703),
125 MII_PHY_DESC(BROADCOM, BCM5704),
126 MII_PHY_DESC(BROADCOM, BCM5705),
127 MII_PHY_DESC(BROADCOM, BCM5706),
128 MII_PHY_DESC(BROADCOM, BCM5714),
129 MII_PHY_DESC(BROADCOM, BCM5421),
130 MII_PHY_DESC(BROADCOM, BCM5750),
131 MII_PHY_DESC(BROADCOM, BCM5752),
132 MII_PHY_DESC(BROADCOM, BCM5780),
133 MII_PHY_DESC(BROADCOM, BCM5708C),
134 MII_PHY_DESC(BROADCOM2, BCM5482),
135 MII_PHY_DESC(BROADCOM2, BCM5708S),
136 MII_PHY_DESC(BROADCOM2, BCM5709C),
137 MII_PHY_DESC(BROADCOM2, BCM5709S),
138 MII_PHY_DESC(BROADCOM2, BCM5709CAX),
139 MII_PHY_DESC(BROADCOM2, BCM5722),
140 MII_PHY_DESC(BROADCOM2, BCM5755),
141 MII_PHY_DESC(BROADCOM2, BCM5754),
142 MII_PHY_DESC(BROADCOM2, BCM5761),
143 MII_PHY_DESC(BROADCOM2, BCM5784),
144 #ifdef notyet /* better handled by ukphy(4) until WARs are implemented */
145 MII_PHY_DESC(BROADCOM2, BCM5785),
147 MII_PHY_DESC(BROADCOM3, BCM5717C),
148 MII_PHY_DESC(BROADCOM3, BCM5719C),
149 MII_PHY_DESC(BROADCOM3, BCM5720C),
150 MII_PHY_DESC(BROADCOM3, BCM57765),
151 MII_PHY_DESC(BROADCOM3, BCM57780),
152 MII_PHY_DESC(BROADCOM4, BCM5725C),
153 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
157 static const struct mii_phy_funcs brgphy_funcs = {
163 static const struct hs21_type {
166 } hs21_type_lists[] = {
167 { 0x57081021, "IBM eServer BladeCenter HS21" },
168 { 0x57081011, "IBM eServer BladeCenter HS21 -[8853PAU]-" },
172 detect_hs21(struct bce_softc *bce_sc)
178 sysenv = kern_getenv("smbios.system.product");
181 for (i = 0; i < nitems(hs21_type_lists); i++) {
182 if (bce_sc->bce_chipid == hs21_type_lists[i].id &&
183 strncmp(sysenv, hs21_type_lists[i].prod,
184 strlen(hs21_type_lists[i].prod)) == 0) {
193 /* Search for our PHY in the list of known PHYs */
195 brgphy_probe(device_t dev)
198 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
201 /* Attach the PHY to the MII bus */
203 brgphy_attach(device_t dev)
205 struct brgphy_softc *bsc;
206 struct bge_softc *bge_sc = NULL;
207 struct bce_softc *bce_sc = NULL;
208 struct mii_softc *sc;
210 bsc = device_get_softc(dev);
213 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
216 bsc->serdes_flags = 0;
218 /* Find the MAC driver associated with this PHY. */
219 if (mii_dev_mac_match(dev, "bge"))
220 bge_sc = mii_dev_mac_softc(dev);
221 else if (mii_dev_mac_match(dev, "bce"))
222 bce_sc = mii_dev_mac_softc(dev);
224 /* Handle any special cases based on the PHY ID */
225 switch (sc->mii_mpd_oui) {
226 case MII_OUI_BROADCOM:
227 switch (sc->mii_mpd_model) {
228 case MII_MODEL_BROADCOM_BCM5706:
229 case MII_MODEL_BROADCOM_BCM5714:
231 * The 5464 PHY used in the 5706 supports both copper
232 * and fiber interfaces over GMII. Need to check the
233 * shadow registers to see which mode is actually
234 * in effect, and therefore whether we have 5706C or
237 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
238 BRGPHY_SHADOW_1C_MODE_CTRL);
239 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
240 BRGPHY_SHADOW_1C_ENA_1000X) {
241 bsc->serdes_flags |= BRGPHY_5706S;
242 sc->mii_flags |= MIIF_HAVEFIBER;
247 case MII_OUI_BROADCOM2:
248 switch (sc->mii_mpd_model) {
249 case MII_MODEL_BROADCOM2_BCM5708S:
250 bsc->serdes_flags |= BRGPHY_5708S;
251 sc->mii_flags |= MIIF_HAVEFIBER;
253 case MII_MODEL_BROADCOM2_BCM5709S:
256 * 5720S and 5709S shares the same PHY id.
257 * Assume 5720S PHY if parent device is bge(4).
260 bsc->serdes_flags |= BRGPHY_5708S;
262 bsc->serdes_flags |= BRGPHY_5709S;
263 sc->mii_flags |= MIIF_HAVEFIBER;
271 /* Read the PHY's capabilities. */
272 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
273 if (sc->mii_capabilities & BMSR_EXTSTAT)
274 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
275 device_printf(dev, " ");
277 /* Add the supported media types */
278 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
279 mii_phy_add_media(sc);
282 sc->mii_anegticks = MII_ANEGTICKS_GIGE;
283 ifmedia_add(&sc->mii_pdata->mii_media,
284 IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
286 printf("1000baseSX-FDX, ");
288 * 2.5G support is a software enabled feature
289 * on the 5708S and 5709S.
291 if (bce_sc && (bce_sc->bce_phy_flags &
292 BCE_PHY_2_5G_CAPABLE_FLAG)) {
293 ifmedia_add(&sc->mii_pdata->mii_media,
294 IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX,
295 sc->mii_inst), 0, NULL);
296 printf("2500baseSX-FDX, ");
297 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
298 (detect_hs21(bce_sc) != 0)) {
300 * There appears to be certain silicon revision
301 * in IBM HS21 blades that is having issues with
302 * this driver wating for the auto-negotiation to
303 * complete. This happens with a specific chip id
304 * only and when the 1000baseSX-FDX is the only
305 * mode. Workaround this issue since it's unlikely
306 * to be ever addressed.
308 printf("auto-neg workaround, ");
309 bsc->serdes_flags |= BRGPHY_NOANWAIT;
311 ifmedia_add(&sc->mii_pdata->mii_media, IFM_MAKEWORD(IFM_ETHER,
312 IFM_AUTO, 0, sc->mii_inst), 0, NULL);
316 MIIBUS_MEDIAINIT(sc->mii_dev);
321 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
323 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
330 /* Todo: Why is this here? Is it really needed? */
331 PHY_RESET(sc); /* XXX hardware bug work-around */
333 switch (IFM_SUBTYPE(ife->ifm_media)) {
335 brgphy_mii_phy_auto(sc, ife->ifm_media);
342 brgphy_setmedia(sc, ife->ifm_media);
349 /* Bail if autoneg isn't in process. */
350 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
356 * Check to see if we have link. If we do, we don't
357 * need to restart the autonegotiation process.
359 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
360 if (val & BMSR_LINK) {
361 sc->mii_ticks = 0; /* Reset autoneg timer. */
365 /* Announce link loss right after it happens. */
366 if (sc->mii_ticks++ == 0)
369 /* Only retry autonegotiation every mii_anegticks seconds. */
370 if (sc->mii_ticks <= sc->mii_anegticks)
374 /* Retry autonegotiation */
376 brgphy_mii_phy_auto(sc, ife->ifm_media);
380 /* Update the media status. */
384 * Callback if something changed. Note that we need to poke
385 * the DSP on the Broadcom PHYs if the media changes.
387 if (sc->mii_media_active != mii->mii_media_active ||
388 sc->mii_media_status != mii->mii_media_status ||
389 cmd == MII_MEDIACHG) {
390 switch (sc->mii_mpd_oui) {
391 case MII_OUI_BROADCOM:
392 switch (sc->mii_mpd_model) {
393 case MII_MODEL_BROADCOM_BCM5400:
394 bcm5401_load_dspcode(sc);
396 case MII_MODEL_BROADCOM_BCM5401:
397 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
398 bcm5401_load_dspcode(sc);
400 case MII_MODEL_BROADCOM_BCM5411:
401 bcm5411_load_dspcode(sc);
403 case MII_MODEL_BROADCOM_BCM54K2:
404 bcm54k2_load_dspcode(sc);
410 mii_phy_update(sc, cmd);
414 /****************************************************************************/
415 /* Sets the PHY link speed. */
419 /****************************************************************************/
421 brgphy_setmedia(struct mii_softc *sc, int media)
425 switch (IFM_SUBTYPE(media)) {
441 if ((media & IFM_FDX) != 0) {
442 bmcr |= BRGPHY_BMCR_FDX;
443 gig = BRGPHY_1000CTL_AFD;
445 gig = BRGPHY_1000CTL_AHD;
448 /* Force loopback to disconnect PHY from Ethernet medium. */
449 brgphy_enable_loopback(sc);
451 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
452 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
454 if (IFM_SUBTYPE(media) != IFM_1000_T &&
455 IFM_SUBTYPE(media) != IFM_1000_SX) {
456 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
460 if (IFM_SUBTYPE(media) == IFM_1000_T) {
461 gig |= BRGPHY_1000CTL_MSE;
462 if ((media & IFM_ETH_MASTER) != 0)
463 gig |= BRGPHY_1000CTL_MSC;
465 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
466 PHY_WRITE(sc, BRGPHY_MII_BMCR,
467 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
470 /****************************************************************************/
471 /* Set the media status based on the PHY settings. */
475 /****************************************************************************/
477 brgphy_status(struct mii_softc *sc)
479 struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
480 struct mii_data *mii = sc->mii_pdata;
481 int aux, bmcr, bmsr, val, xstat;
484 mii->mii_media_status = IFM_AVALID;
485 mii->mii_media_active = IFM_ETHER;
487 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
488 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
490 if (bmcr & BRGPHY_BMCR_LOOP) {
491 mii->mii_media_active |= IFM_LOOP;
494 if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
495 (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
496 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
497 /* Erg, still trying, I guess... */
498 mii->mii_media_active |= IFM_NONE;
502 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
504 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS
505 * wedges at least the PHY of BCM5704 (but not others).
507 flowstat = mii_phy_flowstatus(sc);
508 xstat = PHY_READ(sc, BRGPHY_MII_1000STS);
509 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
511 /* If copper link is up, get the negotiated speed/duplex. */
512 if (aux & BRGPHY_AUXSTS_LINK) {
513 mii->mii_media_status |= IFM_ACTIVE;
514 switch (aux & BRGPHY_AUXSTS_AN_RES) {
515 case BRGPHY_RES_1000FD:
516 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break;
517 case BRGPHY_RES_1000HD:
518 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break;
519 case BRGPHY_RES_100FD:
520 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
521 case BRGPHY_RES_100T4:
522 mii->mii_media_active |= IFM_100_T4; break;
523 case BRGPHY_RES_100HD:
524 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break;
525 case BRGPHY_RES_10FD:
526 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
527 case BRGPHY_RES_10HD:
528 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
530 mii->mii_media_active |= IFM_NONE; break;
533 if ((mii->mii_media_active & IFM_FDX) != 0)
534 mii->mii_media_active |= flowstat;
536 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T &&
537 (xstat & BRGPHY_1000STS_MSR) != 0)
538 mii->mii_media_active |= IFM_ETH_MASTER;
541 /* Todo: Add support for flow control. */
542 /* If serdes link is up, get the negotiated speed/duplex. */
543 if (bmsr & BRGPHY_BMSR_LINK) {
544 mii->mii_media_status |= IFM_ACTIVE;
547 /* Check the link speed/duplex based on the PHY type. */
548 if (bsc->serdes_flags & BRGPHY_5706S) {
549 mii->mii_media_active |= IFM_1000_SX;
551 /* If autoneg enabled, read negotiated duplex settings */
552 if (bmcr & BRGPHY_BMCR_AUTOEN) {
553 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
554 if (val & BRGPHY_SERDES_ANAR_FDX)
555 mii->mii_media_active |= IFM_FDX;
557 mii->mii_media_active |= IFM_HDX;
559 } else if (bsc->serdes_flags & BRGPHY_5708S) {
560 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
561 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
563 /* Check for MRBE auto-negotiated speed results. */
564 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
565 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
566 mii->mii_media_active |= IFM_10_FL; break;
567 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
568 mii->mii_media_active |= IFM_100_FX; break;
569 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
570 mii->mii_media_active |= IFM_1000_SX; break;
571 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
572 mii->mii_media_active |= IFM_2500_SX; break;
575 /* Check for MRBE auto-negotiated duplex results. */
576 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
577 mii->mii_media_active |= IFM_FDX;
579 mii->mii_media_active |= IFM_HDX;
580 } else if (bsc->serdes_flags & BRGPHY_5709S) {
581 /* Select GP Status Block of the AN MMD, get autoneg results. */
582 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
583 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
585 /* Restore IEEE0 block (assumed in all brgphy(4) code). */
586 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
588 /* Check for MRBE auto-negotiated speed results. */
589 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
590 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
591 mii->mii_media_active |= IFM_10_FL; break;
592 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
593 mii->mii_media_active |= IFM_100_FX; break;
594 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
595 mii->mii_media_active |= IFM_1000_SX; break;
596 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
597 mii->mii_media_active |= IFM_2500_SX; break;
600 /* Check for MRBE auto-negotiated duplex results. */
601 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
602 mii->mii_media_active |= IFM_FDX;
604 mii->mii_media_active |= IFM_HDX;
610 brgphy_mii_phy_auto(struct mii_softc *sc, int media)
616 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
617 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
618 if ((media & IFM_FLOW) != 0 ||
619 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
620 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP;
621 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar);
622 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
623 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)
624 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
625 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
626 PHY_READ(sc, BRGPHY_MII_1000CTL);
628 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX;
629 if ((media & IFM_FLOW) != 0 ||
630 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
631 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE;
632 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar);
635 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN |
636 BRGPHY_BMCR_STARTNEG);
637 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
640 /* Enable loopback to force the link down. */
642 brgphy_enable_loopback(struct mii_softc *sc)
646 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
647 for (i = 0; i < 15000; i++) {
648 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
654 /* Turn off tap power management on 5401. */
656 bcm5401_load_dspcode(struct mii_softc *sc)
658 static const struct {
662 { BRGPHY_MII_AUXCTL, 0x0c20 },
663 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
664 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
665 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
666 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
667 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
668 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
669 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
670 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
671 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
672 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
677 for (i = 0; dspcode[i].reg != 0; i++)
678 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
683 bcm5411_load_dspcode(struct mii_softc *sc)
685 static const struct {
696 for (i = 0; dspcode[i].reg != 0; i++)
697 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
701 bcm54k2_load_dspcode(struct mii_softc *sc)
703 static const struct {
713 for (i = 0; dspcode[i].reg != 0; i++)
714 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
719 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
721 static const struct {
731 for (i = 0; dspcode[i].reg != 0; i++)
732 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
736 brgphy_fixup_adc_bug(struct mii_softc *sc)
738 static const struct {
742 { BRGPHY_MII_AUXCTL, 0x0c00 },
743 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
744 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
749 for (i = 0; dspcode[i].reg != 0; i++)
750 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
754 brgphy_fixup_adjust_trim(struct mii_softc *sc)
756 static const struct {
760 { BRGPHY_MII_AUXCTL, 0x0c00 },
761 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
762 { BRGPHY_MII_DSP_RW_PORT, 0x110b },
763 { BRGPHY_MII_TEST1, 0x0014 },
764 { BRGPHY_MII_AUXCTL, 0x0400 },
769 for (i = 0; dspcode[i].reg != 0; i++)
770 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
774 brgphy_fixup_ber_bug(struct mii_softc *sc)
776 static const struct {
780 { BRGPHY_MII_AUXCTL, 0x0c00 },
781 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
782 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
783 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
784 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
785 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
786 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
787 { BRGPHY_MII_AUXCTL, 0x0400 },
792 for (i = 0; dspcode[i].reg != 0; i++)
793 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
797 brgphy_fixup_crc_bug(struct mii_softc *sc)
799 static const struct {
803 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 },
811 for (i = 0; dspcode[i].reg != 0; i++)
812 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
816 brgphy_fixup_jitter_bug(struct mii_softc *sc)
818 static const struct {
822 { BRGPHY_MII_AUXCTL, 0x0c00 },
823 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
824 { BRGPHY_MII_DSP_RW_PORT, 0x010b },
825 { BRGPHY_MII_AUXCTL, 0x0400 },
830 for (i = 0; dspcode[i].reg != 0; i++)
831 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
835 brgphy_fixup_disable_early_dac(struct mii_softc *sc)
839 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
840 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
842 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
847 brgphy_ethernet_wirespeed(struct mii_softc *sc)
851 /* Enable Ethernet@WireSpeed. */
852 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
853 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
854 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
858 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
862 /* Set or clear jumbo frame settings in the PHY. */
863 if (mtu > ETHER_MAX_LEN) {
864 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) {
865 /* BCM5401 PHY cannot read-modify-write. */
866 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
868 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
869 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
870 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
871 val | BRGPHY_AUXCTL_LONG_PKT);
874 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
875 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
876 val | BRGPHY_PHY_EXTCTL_HIGH_LA);
878 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
879 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
880 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
881 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
883 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
884 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
885 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
890 brgphy_reset(struct mii_softc *sc)
892 struct bge_softc *bge_sc = NULL;
893 struct bce_softc *bce_sc = NULL;
898 * Perform a reset. Note that at least some Broadcom PHYs default to
899 * being powered down as well as isolated after a reset but don't work
900 * if one or both of these bits are cleared. However, they just work
901 * fine if both bits remain set, so we don't use mii_phy_reset() here.
903 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
905 /* Wait 100ms for it to complete. */
906 for (i = 0; i < 100; i++) {
907 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0)
912 /* Handle any PHY specific procedures following the reset. */
913 switch (sc->mii_mpd_oui) {
914 case MII_OUI_BROADCOM:
915 switch (sc->mii_mpd_model) {
916 case MII_MODEL_BROADCOM_BCM5400:
917 bcm5401_load_dspcode(sc);
919 case MII_MODEL_BROADCOM_BCM5401:
920 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
921 bcm5401_load_dspcode(sc);
923 case MII_MODEL_BROADCOM_BCM5411:
924 bcm5411_load_dspcode(sc);
926 case MII_MODEL_BROADCOM_BCM54K2:
927 bcm54k2_load_dspcode(sc);
931 case MII_OUI_BROADCOM3:
932 switch (sc->mii_mpd_model) {
933 case MII_MODEL_BROADCOM3_BCM5717C:
934 case MII_MODEL_BROADCOM3_BCM5719C:
935 case MII_MODEL_BROADCOM3_BCM5720C:
936 case MII_MODEL_BROADCOM3_BCM57765:
940 case MII_OUI_BROADCOM4:
944 ifp = sc->mii_pdata->mii_ifp;
946 /* Find the driver associated with this PHY. */
947 if (mii_phy_mac_match(sc, "bge"))
948 bge_sc = mii_phy_mac_softc(sc);
949 else if (mii_phy_mac_match(sc, "bce"))
950 bce_sc = mii_phy_mac_softc(sc);
953 /* Fix up various bugs */
954 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
955 brgphy_fixup_5704_a0_bug(sc);
956 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
957 brgphy_fixup_adc_bug(sc);
958 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
959 brgphy_fixup_adjust_trim(sc);
960 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
961 brgphy_fixup_ber_bug(sc);
962 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
963 brgphy_fixup_crc_bug(sc);
964 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
965 brgphy_fixup_jitter_bug(sc);
967 if (bge_sc->bge_flags & BGE_FLAG_JUMBO)
968 brgphy_jumbo_settings(sc, if_getmtu(ifp));
970 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0)
971 brgphy_ethernet_wirespeed(sc);
973 /* Enable Link LED on Dell boxes */
974 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
975 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
976 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
977 ~BRGPHY_PHY_EXTCTL_3_LED);
980 /* Adjust output voltage (From Linux driver) */
981 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
982 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
984 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
985 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
987 /* Store autoneg capabilities/results in digital block (Page 0) */
988 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
989 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
990 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
991 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
993 /* Enable fiber mode and autodetection */
994 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
995 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
996 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
997 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
999 /* Enable parallel detection */
1000 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
1001 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
1002 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
1004 /* Advertise 2.5G support through next page during autoneg */
1005 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1006 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
1007 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
1008 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
1010 /* Increase TX signal amplitude */
1011 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
1012 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
1013 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
1014 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1015 BRGPHY_5708S_TX_MISC_PG5);
1016 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
1017 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
1018 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1019 BRGPHY_5708S_DIG_PG0);
1022 /* Backplanes use special driver/pre-driver/pre-emphasis values. */
1023 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
1024 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
1025 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1026 BRGPHY_5708S_TX_MISC_PG5);
1027 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1028 bce_sc->bce_port_hw_cfg &
1029 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1030 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1031 BRGPHY_5708S_DIG_PG0);
1033 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
1034 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1036 /* Select the SerDes Digital block of the AN MMD. */
1037 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
1038 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
1039 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
1040 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
1041 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
1043 /* Select the Over 1G block of the AN MMD. */
1044 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
1046 /* Enable autoneg "Next Page" to advertise 2.5G support. */
1047 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
1048 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1049 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1051 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1052 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
1054 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
1055 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
1057 /* Enable MRBE speed autoneg. */
1058 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
1059 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
1060 BRGPHY_MRBE_MSG_PG5_NP_T2;
1061 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
1063 /* Select the Clause 73 User B0 block of the AN MMD. */
1064 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
1066 /* Enable MRBE speed autoneg. */
1067 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
1068 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
1069 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
1070 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
1072 /* Restore IEEE0 block (assumed in all brgphy(4) code). */
1073 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
1074 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1075 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1076 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1077 brgphy_fixup_disable_early_dac(sc);
1079 brgphy_jumbo_settings(sc, if_getmtu(ifp));
1080 brgphy_ethernet_wirespeed(sc);
1082 brgphy_fixup_ber_bug(sc);
1083 brgphy_jumbo_settings(sc, if_getmtu(ifp));
1084 brgphy_ethernet_wirespeed(sc);