sys/dev/mii/brgphy.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-4-Clause
   3  *
   4  * Copyright (c) 2000
   5  *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Bill Paul.
  18  * 4. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  32  * THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <sys/cdefs.h>
  36 __FBSDID("$FreeBSD$");
  37
  38 /*
  39  * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
  40  */
  41
  42 #include <sys/param.h>
  43 #include <sys/systm.h>
  44 #include <sys/kernel.h>
  45 #include <sys/module.h>
  46 #include <sys/socket.h>
  47 #include <sys/bus.h>
  48 #include <sys/taskqueue.h>
  49
  50 #include <net/if.h>
  51 #include <net/if_var.h>
  52 #include <net/ethernet.h>
  53 #include <net/if_media.h>
  54
  55 #include <dev/mii/mii.h>
  56 #include <dev/mii/miivar.h>
  57 #include "miidevs.h"
  58
  59 #include <dev/mii/brgphyreg.h>
  60 #include <net/if_arp.h>
  61 #include <machine/bus.h>
  62 #include <dev/bge/if_bgereg.h>
  63 #include <dev/bce/if_bcereg.h>
  64
  65 #include <dev/pci/pcireg.h>
  66 #include <dev/pci/pcivar.h>
  67
  68 #include "miibus_if.h"
  69
  70 static int brgphy_probe(device_t);
  71 static int brgphy_attach(device_t);
  72
  73 struct brgphy_softc {
  74         struct mii_softc mii_sc;
  75         int serdes_flags;       /* Keeps track of the serdes type used */
  76 #define BRGPHY_5706S            0x0001
  77 #define BRGPHY_5708S            0x0002
  78 #define BRGPHY_NOANWAIT         0x0004
  79 #define BRGPHY_5709S            0x0008
  80         int bce_phy_flags;      /* PHY flags transferred from the MAC driver */
  81 };
  82
  83 static device_method_t brgphy_methods[] = {
  84         /* device interface */
  85         DEVMETHOD(device_probe,         brgphy_probe),
  86         DEVMETHOD(device_attach,        brgphy_attach),
  87         DEVMETHOD(device_detach,        mii_phy_detach),
  88         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  89         DEVMETHOD_END
  90 };
  91
  92 static devclass_t brgphy_devclass;
  93
  94 static driver_t brgphy_driver = {
  95         "brgphy",
  96         brgphy_methods,
  97         sizeof(struct brgphy_softc)
  98 };
  99
 100 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
 101
 102 static int      brgphy_service(struct mii_softc *, struct mii_data *, int);
 103 static void     brgphy_setmedia(struct mii_softc *, int);
 104 static void     brgphy_status(struct mii_softc *);
 105 static void     brgphy_mii_phy_auto(struct mii_softc *, int);
 106 static void     brgphy_reset(struct mii_softc *);
 107 static void     brgphy_enable_loopback(struct mii_softc *);
 108 static void     bcm5401_load_dspcode(struct mii_softc *);
 109 static void     bcm5411_load_dspcode(struct mii_softc *);
 110 static void     bcm54k2_load_dspcode(struct mii_softc *);
 111 static void     brgphy_fixup_5704_a0_bug(struct mii_softc *);
 112 static void     brgphy_fixup_adc_bug(struct mii_softc *);
 113 static void     brgphy_fixup_adjust_trim(struct mii_softc *);
 114 static void     brgphy_fixup_ber_bug(struct mii_softc *);
 115 static void     brgphy_fixup_crc_bug(struct mii_softc *);
 116 static void     brgphy_fixup_jitter_bug(struct mii_softc *);
 117 static void     brgphy_ethernet_wirespeed(struct mii_softc *);
 118 static void     brgphy_jumbo_settings(struct mii_softc *, u_long);
 119
 120 static const struct mii_phydesc brgphys[] = {
 121         MII_PHY_DESC(BROADCOM, BCM5400),
 122         MII_PHY_DESC(BROADCOM, BCM5401),
 123         MII_PHY_DESC(BROADCOM, BCM5402),
 124         MII_PHY_DESC(BROADCOM, BCM5411),
 125         MII_PHY_DESC(BROADCOM, BCM5404),
 126         MII_PHY_DESC(BROADCOM, BCM5424),
 127         MII_PHY_DESC(BROADCOM, BCM54K2),
 128         MII_PHY_DESC(BROADCOM, BCM5701),
 129         MII_PHY_DESC(BROADCOM, BCM5703),
 130         MII_PHY_DESC(BROADCOM, BCM5704),
 131         MII_PHY_DESC(BROADCOM, BCM5705),
 132         MII_PHY_DESC(BROADCOM, BCM5706),
 133         MII_PHY_DESC(BROADCOM, BCM5714),
 134         MII_PHY_DESC(BROADCOM, BCM5421),
 135         MII_PHY_DESC(BROADCOM, BCM5750),
 136         MII_PHY_DESC(BROADCOM, BCM5752),
 137         MII_PHY_DESC(BROADCOM, BCM5780),
 138         MII_PHY_DESC(BROADCOM, BCM5708C),
 139         MII_PHY_DESC(BROADCOM, BCM5466),
 140         MII_PHY_DESC(BROADCOM2, BCM5478),
 141         MII_PHY_DESC(BROADCOM2, BCM5488),
 142         MII_PHY_DESC(BROADCOM2, BCM5482),
 143         MII_PHY_DESC(BROADCOM2, BCM5708S),
 144         MII_PHY_DESC(BROADCOM2, BCM5709C),
 145         MII_PHY_DESC(BROADCOM2, BCM5709S),
 146         MII_PHY_DESC(BROADCOM2, BCM5709CAX),
 147         MII_PHY_DESC(BROADCOM2, BCM5722),
 148         MII_PHY_DESC(BROADCOM2, BCM5755),
 149         MII_PHY_DESC(BROADCOM2, BCM5754),
 150         MII_PHY_DESC(BROADCOM2, BCM5761),
 151         MII_PHY_DESC(BROADCOM2, BCM5784),
 152 #ifdef notyet   /* better handled by ukphy(4) until WARs are implemented */
 153         MII_PHY_DESC(BROADCOM2, BCM5785),
 154 #endif
 155         MII_PHY_DESC(BROADCOM3, BCM54618SE),
 156         MII_PHY_DESC(BROADCOM3, BCM5717C),
 157         MII_PHY_DESC(BROADCOM3, BCM5719C),
 158         MII_PHY_DESC(BROADCOM3, BCM5720C),
 159         MII_PHY_DESC(BROADCOM3, BCM57765),
 160         MII_PHY_DESC(BROADCOM3, BCM57780),
 161         MII_PHY_DESC(BROADCOM4, BCM5725C),
 162         MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
 163         MII_PHY_END
 164 };
 165
 166 static const struct mii_phy_funcs brgphy_funcs = {
 167         brgphy_service,
 168         brgphy_status,
 169         brgphy_reset
 170 };
 171
 172 static const struct hs21_type {
 173         const uint32_t id;
 174         const char *prod;
 175 } hs21_type_lists[] = {
 176         { 0x57081021, "IBM eServer BladeCenter HS21" },
 177         { 0x57081011, "IBM eServer BladeCenter HS21 -[8853PAU]-" },
 178 };
 179
 180 static int
 181 detect_hs21(struct bce_softc *bce_sc)
 182 {
 183         char *sysenv;
 184         int found, i;
 185
 186         found = 0;
 187         sysenv = kern_getenv("smbios.system.product");
 188         if (sysenv == NULL)
 189                 return (found);
 190         for (i = 0; i < nitems(hs21_type_lists); i++) {
 191                 if (bce_sc->bce_chipid == hs21_type_lists[i].id &&
 192                     strncmp(sysenv, hs21_type_lists[i].prod,
 193                     strlen(hs21_type_lists[i].prod)) == 0) {
 194                         found++;
 195                         break;
 196                 }
 197         }
 198         freeenv(sysenv);
 199         return (found);
 200 }
 201
 202 /* Search for our PHY in the list of known PHYs */
 203 static int
 204 brgphy_probe(device_t dev)
 205 {
 206
 207         return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
 208 }
 209
 210 /* Attach the PHY to the MII bus */
 211 static int
 212 brgphy_attach(device_t dev)
 213 {
 214         struct brgphy_softc *bsc;
 215         struct bge_softc *bge_sc = NULL;
 216         struct bce_softc *bce_sc = NULL;
 217         struct mii_softc *sc;
 218
 219         bsc = device_get_softc(dev);
 220         sc = &bsc->mii_sc;
 221
 222         mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
 223             &brgphy_funcs, 0);
 224
 225         bsc->serdes_flags = 0;
 226
 227         /* Find the MAC driver associated with this PHY. */
 228         if (mii_dev_mac_match(dev, "bge"))
 229                 bge_sc = mii_dev_mac_softc(dev);
 230         else if (mii_dev_mac_match(dev, "bce"))
 231                 bce_sc = mii_dev_mac_softc(dev);
 232
 233         /* Handle any special cases based on the PHY ID */
 234         switch (sc->mii_mpd_oui) {
 235         case MII_OUI_BROADCOM:
 236                 switch (sc->mii_mpd_model) {
 237                 case MII_MODEL_BROADCOM_BCM5706:
 238                 case MII_MODEL_BROADCOM_BCM5714:
 239                         /*
 240                          * The 5464 PHY used in the 5706 supports both copper
 241                          * and fiber interfaces over GMII.  Need to check the
 242                          * shadow registers to see which mode is actually
 243                          * in effect, and therefore whether we have 5706C or
 244                          * 5706S.
 245                          */
 246                         PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
 247                                 BRGPHY_SHADOW_1C_MODE_CTRL);
 248                         if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
 249                                 BRGPHY_SHADOW_1C_ENA_1000X) {
 250                                 bsc->serdes_flags |= BRGPHY_5706S;
 251                                 sc->mii_flags |= MIIF_HAVEFIBER;
 252                         }
 253                         break;
 254                 }
 255                 break;
 256         case MII_OUI_BROADCOM2:
 257                 switch (sc->mii_mpd_model) {
 258                 case MII_MODEL_BROADCOM2_BCM5708S:
 259                         bsc->serdes_flags |= BRGPHY_5708S;
 260                         sc->mii_flags |= MIIF_HAVEFIBER;
 261                         break;
 262                 case MII_MODEL_BROADCOM2_BCM5709S:
 263                         /*
 264                          * XXX
 265                          * 5720S and 5709S shares the same PHY id.
 266                          * Assume 5720S PHY if parent device is bge(4).
 267                          */
 268                         if (bge_sc != NULL)
 269                                 bsc->serdes_flags |= BRGPHY_5708S;
 270                         else
 271                                 bsc->serdes_flags |= BRGPHY_5709S;
 272                         sc->mii_flags |= MIIF_HAVEFIBER;
 273                         break;
 274                 }
 275                 break;
 276         }
 277
 278         PHY_RESET(sc);
 279
 280         /* Read the PHY's capabilities. */
 281         sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
 282         if (sc->mii_capabilities & BMSR_EXTSTAT)
 283                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 284         device_printf(dev, " ");
 285
 286         /* Add the supported media types */
 287         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 288                 mii_phy_add_media(sc);
 289                 printf("\n");
 290         } else {
 291                 sc->mii_anegticks = MII_ANEGTICKS_GIGE;
 292                 ifmedia_add(&sc->mii_pdata->mii_media,
 293                     IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
 294                     0, NULL);
 295                 printf("1000baseSX-FDX, ");
 296                 /*
 297                  * 2.5G support is a software enabled feature
 298                  * on the 5708S and 5709S.
 299                  */
 300                 if (bce_sc && (bce_sc->bce_phy_flags &
 301                     BCE_PHY_2_5G_CAPABLE_FLAG)) {
 302                         ifmedia_add(&sc->mii_pdata->mii_media,
 303                             IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX,
 304                             sc->mii_inst), 0, NULL);
 305                         printf("2500baseSX-FDX, ");
 306                 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
 307                     (detect_hs21(bce_sc) != 0)) {
 308                         /*
 309                          * There appears to be certain silicon revision
 310                          * in IBM HS21 blades that is having issues with
 311                          * this driver wating for the auto-negotiation to
 312                          * complete. This happens with a specific chip id
 313                          * only and when the 1000baseSX-FDX is the only
 314                          * mode. Workaround this issue since it's unlikely
 315                          * to be ever addressed.
 316                          */
 317                         printf("auto-neg workaround, ");
 318                         bsc->serdes_flags |= BRGPHY_NOANWAIT;
 319                 }
 320                 ifmedia_add(&sc->mii_pdata->mii_media, IFM_MAKEWORD(IFM_ETHER,
 321                     IFM_AUTO, 0, sc->mii_inst), 0, NULL);
 322                 printf("auto\n");
 323         }
 324
 325         MIIBUS_MEDIAINIT(sc->mii_dev);
 326         return (0);
 327 }
 328
 329 static int
 330 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 331 {
 332         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 333         int val;
 334
 335         switch (cmd) {
 336         case MII_POLLSTAT:
 337                 break;
 338         case MII_MEDIACHG:
 339                 /* Todo: Why is this here?  Is it really needed? */
 340                 PHY_RESET(sc);  /* XXX hardware bug work-around */
 341
 342                 switch (IFM_SUBTYPE(ife->ifm_media)) {
 343                 case IFM_AUTO:
 344                         brgphy_mii_phy_auto(sc, ife->ifm_media);
 345                         break;
 346                 case IFM_2500_SX:
 347                 case IFM_1000_SX:
 348                 case IFM_1000_T:
 349                 case IFM_100_TX:
 350                 case IFM_10_T:
 351                         brgphy_setmedia(sc, ife->ifm_media);
 352                         break;
 353                 default:
 354                         return (EINVAL);
 355                 }
 356                 break;
 357         case MII_TICK:
 358                 /* Bail if autoneg isn't in process. */
 359                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
 360                         sc->mii_ticks = 0;
 361                         break;
 362                 }
 363
 364                 /*
 365                  * Check to see if we have link.  If we do, we don't
 366                  * need to restart the autonegotiation process.
 367                  */
 368                 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
 369                 if (val & BMSR_LINK) {
 370                         sc->mii_ticks = 0;      /* Reset autoneg timer. */
 371                         break;
 372                 }
 373
 374                 /* Announce link loss right after it happens. */
 375                 if (sc->mii_ticks++ == 0)
 376                         break;
 377
 378                 /* Only retry autonegotiation every mii_anegticks seconds. */
 379                 if (sc->mii_ticks <= sc->mii_anegticks)
 380                         break;
 381
 382
 383                 /* Retry autonegotiation */
 384                 sc->mii_ticks = 0;
 385                 brgphy_mii_phy_auto(sc, ife->ifm_media);
 386                 break;
 387         }
 388
 389         /* Update the media status. */
 390         PHY_STATUS(sc);
 391
 392         /*
 393          * Callback if something changed. Note that we need to poke
 394          * the DSP on the Broadcom PHYs if the media changes.
 395          */
 396         if (sc->mii_media_active != mii->mii_media_active ||
 397             sc->mii_media_status != mii->mii_media_status ||
 398             cmd == MII_MEDIACHG) {
 399                 switch (sc->mii_mpd_oui) {
 400                 case MII_OUI_BROADCOM:
 401                         switch (sc->mii_mpd_model) {
 402                         case MII_MODEL_BROADCOM_BCM5400:
 403                                 bcm5401_load_dspcode(sc);
 404                                 break;
 405                         case MII_MODEL_BROADCOM_BCM5401:
 406                                 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
 407                                         bcm5401_load_dspcode(sc);
 408                                 break;
 409                         case MII_MODEL_BROADCOM_BCM5411:
 410                                 bcm5411_load_dspcode(sc);
 411                                 break;
 412                         case MII_MODEL_BROADCOM_BCM54K2:
 413                                 bcm54k2_load_dspcode(sc);
 414                                 break;
 415                         }
 416                         break;
 417                 }
 418         }
 419         mii_phy_update(sc, cmd);
 420         return (0);
 421 }
 422
 423 /****************************************************************************/
 424 /* Sets the PHY link speed.                                                 */
 425 /*                                                                          */
 426 /* Returns:                                                                 */
 427 /*   None                                                                   */
 428 /****************************************************************************/
 429 static void
 430 brgphy_setmedia(struct mii_softc *sc, int media)
 431 {
 432         int bmcr = 0, gig;
 433
 434         switch (IFM_SUBTYPE(media)) {
 435         case IFM_2500_SX:
 436                 break;
 437         case IFM_1000_SX:
 438         case IFM_1000_T:
 439                 bmcr = BRGPHY_S1000;
 440                 break;
 441         case IFM_100_TX:
 442                 bmcr = BRGPHY_S100;
 443                 break;
 444         case IFM_10_T:
 445         default:
 446                 bmcr = BRGPHY_S10;
 447                 break;
 448         }
 449
 450         if ((media & IFM_FDX) != 0) {
 451                 bmcr |= BRGPHY_BMCR_FDX;
 452                 gig = BRGPHY_1000CTL_AFD;
 453         } else {
 454                 gig = BRGPHY_1000CTL_AHD;
 455         }
 456
 457         /* Force loopback to disconnect PHY from Ethernet medium. */
 458         brgphy_enable_loopback(sc);
 459
 460         PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
 461         PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
 462
 463         if (IFM_SUBTYPE(media) != IFM_1000_T &&
 464             IFM_SUBTYPE(media) != IFM_1000_SX) {
 465                 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
 466                 return;
 467         }
 468
 469         if (IFM_SUBTYPE(media) == IFM_1000_T) {
 470                 gig |= BRGPHY_1000CTL_MSE;
 471                 if ((media & IFM_ETH_MASTER) != 0)
 472                         gig |= BRGPHY_1000CTL_MSC;
 473         }
 474         PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
 475         PHY_WRITE(sc, BRGPHY_MII_BMCR,
 476             bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
 477 }
 478
 479 /****************************************************************************/
 480 /* Set the media status based on the PHY settings.                          */
 481 /*                                                                          */
 482 /* Returns:                                                                 */
 483 /*   None                                                                   */
 484 /****************************************************************************/
 485 static void
 486 brgphy_status(struct mii_softc *sc)
 487 {
 488         struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
 489         struct mii_data *mii = sc->mii_pdata;
 490         int aux, bmcr, bmsr, val, xstat;
 491         u_int flowstat;
 492
 493         mii->mii_media_status = IFM_AVALID;
 494         mii->mii_media_active = IFM_ETHER;
 495
 496         bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
 497         bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
 498
 499         if (bmcr & BRGPHY_BMCR_LOOP) {
 500                 mii->mii_media_active |= IFM_LOOP;
 501         }
 502
 503         if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
 504             (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
 505             (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
 506                 /* Erg, still trying, I guess... */
 507                 mii->mii_media_active |= IFM_NONE;
 508                 return;
 509         }
 510
 511         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 512                 /*
 513                  * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS
 514                  * wedges at least the PHY of BCM5704 (but not others).
 515                  */
 516                 flowstat = mii_phy_flowstatus(sc);
 517                 xstat = PHY_READ(sc, BRGPHY_MII_1000STS);
 518                 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
 519
 520                 /* If copper link is up, get the negotiated speed/duplex. */
 521                 if (aux & BRGPHY_AUXSTS_LINK) {
 522                         mii->mii_media_status |= IFM_ACTIVE;
 523                         switch (aux & BRGPHY_AUXSTS_AN_RES) {
 524                         case BRGPHY_RES_1000FD:
 525                                 mii->mii_media_active |= IFM_1000_T | IFM_FDX;  break;
 526                         case BRGPHY_RES_1000HD:
 527                                 mii->mii_media_active |= IFM_1000_T | IFM_HDX;  break;
 528                         case BRGPHY_RES_100FD:
 529                                 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
 530                         case BRGPHY_RES_100T4:
 531                                 mii->mii_media_active |= IFM_100_T4; break;
 532                         case BRGPHY_RES_100HD:
 533                                 mii->mii_media_active |= IFM_100_TX | IFM_HDX;  break;
 534                         case BRGPHY_RES_10FD:
 535                                 mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
 536                         case BRGPHY_RES_10HD:
 537                                 mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
 538                         default:
 539                                 mii->mii_media_active |= IFM_NONE; break;
 540                         }
 541
 542                         if ((mii->mii_media_active & IFM_FDX) != 0)
 543                                 mii->mii_media_active |= flowstat;
 544
 545                         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T &&
 546                             (xstat & BRGPHY_1000STS_MSR) != 0)
 547                                 mii->mii_media_active |= IFM_ETH_MASTER;
 548                 }
 549         } else {
 550                 /* Todo: Add support for flow control. */
 551                 /* If serdes link is up, get the negotiated speed/duplex. */
 552                 if (bmsr & BRGPHY_BMSR_LINK) {
 553                         mii->mii_media_status |= IFM_ACTIVE;
 554                 }
 555
 556                 /* Check the link speed/duplex based on the PHY type. */
 557                 if (bsc->serdes_flags & BRGPHY_5706S) {
 558                         mii->mii_media_active |= IFM_1000_SX;
 559
 560                         /* If autoneg enabled, read negotiated duplex settings */
 561                         if (bmcr & BRGPHY_BMCR_AUTOEN) {
 562                                 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
 563                                 if (val & BRGPHY_SERDES_ANAR_FDX)
 564                                         mii->mii_media_active |= IFM_FDX;
 565                                 else
 566                                         mii->mii_media_active |= IFM_HDX;
 567                         }
 568                 } else if (bsc->serdes_flags & BRGPHY_5708S) {
 569                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
 570                         xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
 571
 572                         /* Check for MRBE auto-negotiated speed results. */
 573                         switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
 574                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
 575                                 mii->mii_media_active |= IFM_10_FL; break;
 576                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
 577                                 mii->mii_media_active |= IFM_100_FX; break;
 578                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
 579                                 mii->mii_media_active |= IFM_1000_SX; break;
 580                         case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
 581                                 mii->mii_media_active |= IFM_2500_SX; break;
 582                         }
 583
 584                         /* Check for MRBE auto-negotiated duplex results. */
 585                         if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
 586                                 mii->mii_media_active |= IFM_FDX;
 587                         else
 588                                 mii->mii_media_active |= IFM_HDX;
 589                 } else if (bsc->serdes_flags & BRGPHY_5709S) {
 590                         /* Select GP Status Block of the AN MMD, get autoneg results. */
 591                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
 592                         xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
 593
 594                         /* Restore IEEE0 block (assumed in all brgphy(4) code). */
 595                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
 596
 597                         /* Check for MRBE auto-negotiated speed results. */
 598                         switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
 599                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
 600                                         mii->mii_media_active |= IFM_10_FL; break;
 601                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
 602                                         mii->mii_media_active |= IFM_100_FX; break;
 603                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
 604                                         mii->mii_media_active |= IFM_1000_SX; break;
 605                                 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
 606                                         mii->mii_media_active |= IFM_2500_SX; break;
 607                         }
 608
 609                         /* Check for MRBE auto-negotiated duplex results. */
 610                         if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
 611                                 mii->mii_media_active |= IFM_FDX;
 612                         else
 613                                 mii->mii_media_active |= IFM_HDX;
 614                 }
 615         }
 616 }
 617
 618 static void
 619 brgphy_mii_phy_auto(struct mii_softc *sc, int media)
 620 {
 621         int anar, ktcr = 0;
 622
 623         PHY_RESET(sc);
 624
 625         if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
 626                 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
 627                 if ((media & IFM_FLOW) != 0 ||
 628                     (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
 629                         anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP;
 630                 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar);
 631                 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
 632                 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)
 633                         ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
 634                 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
 635                 PHY_READ(sc, BRGPHY_MII_1000CTL);
 636         } else {
 637                 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX;
 638                 if ((media & IFM_FLOW) != 0 ||
 639                     (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
 640                         anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE;
 641                 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar);
 642         }
 643
 644         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN |
 645             BRGPHY_BMCR_STARTNEG);
 646         PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
 647 }
 648
 649 /* Enable loopback to force the link down. */
 650 static void
 651 brgphy_enable_loopback(struct mii_softc *sc)
 652 {
 653         int i;
 654
 655         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
 656         for (i = 0; i < 15000; i++) {
 657                 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
 658                         break;
 659                 DELAY(10);
 660         }
 661 }
 662
 663 /* Turn off tap power management on 5401. */
 664 static void
 665 bcm5401_load_dspcode(struct mii_softc *sc)
 666 {
 667         static const struct {
 668                 int             reg;
 669                 uint16_t        val;
 670         } dspcode[] = {
 671                 { BRGPHY_MII_AUXCTL,            0x0c20 },
 672                 { BRGPHY_MII_DSP_ADDR_REG,      0x0012 },
 673                 { BRGPHY_MII_DSP_RW_PORT,       0x1804 },
 674                 { BRGPHY_MII_DSP_ADDR_REG,      0x0013 },
 675                 { BRGPHY_MII_DSP_RW_PORT,       0x1204 },
 676                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 677                 { BRGPHY_MII_DSP_RW_PORT,       0x0132 },
 678                 { BRGPHY_MII_DSP_ADDR_REG,      0x8006 },
 679                 { BRGPHY_MII_DSP_RW_PORT,       0x0232 },
 680                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 681                 { BRGPHY_MII_DSP_RW_PORT,       0x0a20 },
 682                 { 0,                            0 },
 683         };
 684         int i;
 685
 686         for (i = 0; dspcode[i].reg != 0; i++)
 687                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 688         DELAY(40);
 689 }
 690
 691 static void
 692 bcm5411_load_dspcode(struct mii_softc *sc)
 693 {
 694         static const struct {
 695                 int             reg;
 696                 uint16_t        val;
 697         } dspcode[] = {
 698                 { 0x1c,                         0x8c23 },
 699                 { 0x1c,                         0x8ca3 },
 700                 { 0x1c,                         0x8c23 },
 701                 { 0,                            0 },
 702         };
 703         int i;
 704
 705         for (i = 0; dspcode[i].reg != 0; i++)
 706                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 707 }
 708
 709 void
 710 bcm54k2_load_dspcode(struct mii_softc *sc)
 711 {
 712         static const struct {
 713                 int             reg;
 714                 uint16_t        val;
 715         } dspcode[] = {
 716                 { 4,                            0x01e1 },
 717                 { 9,                            0x0300 },
 718                 { 0,                            0 },
 719         };
 720         int i;
 721
 722         for (i = 0; dspcode[i].reg != 0; i++)
 723                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 724
 725 }
 726
 727 static void
 728 brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
 729 {
 730         static const struct {
 731                 int             reg;
 732                 uint16_t        val;
 733         } dspcode[] = {
 734                 { 0x1c,                         0x8d68 },
 735                 { 0x1c,                         0x8d68 },
 736                 { 0,                            0 },
 737         };
 738         int i;
 739
 740         for (i = 0; dspcode[i].reg != 0; i++)
 741                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 742 }
 743
 744 static void
 745 brgphy_fixup_adc_bug(struct mii_softc *sc)
 746 {
 747         static const struct {
 748                 int             reg;
 749                 uint16_t        val;
 750         } dspcode[] = {
 751                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 752                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 753                 { BRGPHY_MII_DSP_RW_PORT,       0x2aaa },
 754                 { 0,                            0 },
 755         };
 756         int i;
 757
 758         for (i = 0; dspcode[i].reg != 0; i++)
 759                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 760 }
 761
 762 static void
 763 brgphy_fixup_adjust_trim(struct mii_softc *sc)
 764 {
 765         static const struct {
 766                 int             reg;
 767                 uint16_t        val;
 768         } dspcode[] = {
 769                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 770                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 771                 { BRGPHY_MII_DSP_RW_PORT,       0x110b },
 772                 { BRGPHY_MII_TEST1,                     0x0014 },
 773                 { BRGPHY_MII_AUXCTL,            0x0400 },
 774                 { 0,                            0 },
 775         };
 776         int i;
 777
 778         for (i = 0; dspcode[i].reg != 0; i++)
 779                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 780 }
 781
 782 static void
 783 brgphy_fixup_ber_bug(struct mii_softc *sc)
 784 {
 785         static const struct {
 786                 int             reg;
 787                 uint16_t        val;
 788         } dspcode[] = {
 789                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 790                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 791                 { BRGPHY_MII_DSP_RW_PORT,       0x310b },
 792                 { BRGPHY_MII_DSP_ADDR_REG,      0x201f },
 793                 { BRGPHY_MII_DSP_RW_PORT,       0x9506 },
 794                 { BRGPHY_MII_DSP_ADDR_REG,      0x401f },
 795                 { BRGPHY_MII_DSP_RW_PORT,       0x14e2 },
 796                 { BRGPHY_MII_AUXCTL,            0x0400 },
 797                 { 0,                            0 },
 798         };
 799         int i;
 800
 801         for (i = 0; dspcode[i].reg != 0; i++)
 802                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 803 }
 804
 805 static void
 806 brgphy_fixup_crc_bug(struct mii_softc *sc)
 807 {
 808         static const struct {
 809                 int             reg;
 810                 uint16_t        val;
 811         } dspcode[] = {
 812                 { BRGPHY_MII_DSP_RW_PORT,       0x0a75 },
 813                 { 0x1c,                         0x8c68 },
 814                 { 0x1c,                         0x8d68 },
 815                 { 0x1c,                         0x8c68 },
 816                 { 0,                            0 },
 817         };
 818         int i;
 819
 820         for (i = 0; dspcode[i].reg != 0; i++)
 821                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 822 }
 823
 824 static void
 825 brgphy_fixup_jitter_bug(struct mii_softc *sc)
 826 {
 827         static const struct {
 828                 int             reg;
 829                 uint16_t        val;
 830         } dspcode[] = {
 831                 { BRGPHY_MII_AUXCTL,            0x0c00 },
 832                 { BRGPHY_MII_DSP_ADDR_REG,      0x000a },
 833                 { BRGPHY_MII_DSP_RW_PORT,       0x010b },
 834                 { BRGPHY_MII_AUXCTL,            0x0400 },
 835                 { 0,                            0 },
 836         };
 837         int i;
 838
 839         for (i = 0; dspcode[i].reg != 0; i++)
 840                 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
 841 }
 842
 843 static void
 844 brgphy_fixup_disable_early_dac(struct mii_softc *sc)
 845 {
 846         uint32_t val;
 847
 848         PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
 849         val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
 850         val &= ~(1 << 8);
 851         PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
 852
 853 }
 854
 855 static void
 856 brgphy_ethernet_wirespeed(struct mii_softc *sc)
 857 {
 858         uint32_t        val;
 859
 860         /* Enable Ethernet@WireSpeed. */
 861         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
 862         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 863         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
 864 }
 865
 866 static void
 867 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
 868 {
 869         uint32_t        val;
 870
 871         /* Set or clear jumbo frame settings in the PHY. */
 872         if (mtu > ETHER_MAX_LEN) {
 873                 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) {
 874                         /* BCM5401 PHY cannot read-modify-write. */
 875                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
 876                 } else {
 877                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 878                         val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 879                         PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 880                             val | BRGPHY_AUXCTL_LONG_PKT);
 881                 }
 882
 883                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 884                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 885                     val | BRGPHY_PHY_EXTCTL_HIGH_LA);
 886         } else {
 887                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
 888                 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
 889                 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
 890                     val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
 891
 892                 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
 893                 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 894                         val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
 895         }
 896 }
 897
 898 static void
 899 brgphy_reset(struct mii_softc *sc)
 900 {
 901         struct bge_softc *bge_sc = NULL;
 902         struct bce_softc *bce_sc = NULL;
 903         if_t ifp;
 904         int i, val;
 905
 906         /*
 907          * Perform a reset.  Note that at least some Broadcom PHYs default to
 908          * being powered down as well as isolated after a reset but don't work
 909          * if one or both of these bits are cleared.  However, they just work
 910          * fine if both bits remain set, so we don't use mii_phy_reset() here.
 911          */
 912         PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
 913
 914         /* Wait 100ms for it to complete. */
 915         for (i = 0; i < 100; i++) {
 916                 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0)
 917                         break;
 918                 DELAY(1000);
 919         }
 920
 921         /* Handle any PHY specific procedures following the reset. */
 922         switch (sc->mii_mpd_oui) {
 923         case MII_OUI_BROADCOM:
 924                 switch (sc->mii_mpd_model) {
 925                 case MII_MODEL_BROADCOM_BCM5400:
 926                         bcm5401_load_dspcode(sc);
 927                         break;
 928                 case MII_MODEL_BROADCOM_BCM5401:
 929                         if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
 930                                 bcm5401_load_dspcode(sc);
 931                         break;
 932                 case MII_MODEL_BROADCOM_BCM5411:
 933                         bcm5411_load_dspcode(sc);
 934                         break;
 935                 case MII_MODEL_BROADCOM_BCM54K2:
 936                         bcm54k2_load_dspcode(sc);
 937                         break;
 938                 }
 939                 break;
 940         case MII_OUI_BROADCOM3:
 941                 switch (sc->mii_mpd_model) {
 942                 case MII_MODEL_BROADCOM3_BCM5717C:
 943                 case MII_MODEL_BROADCOM3_BCM5719C:
 944                 case MII_MODEL_BROADCOM3_BCM5720C:
 945                 case MII_MODEL_BROADCOM3_BCM57765:
 946                         return;
 947                 }
 948                 break;
 949         case MII_OUI_BROADCOM4:
 950                 return;
 951         }
 952
 953         ifp = sc->mii_pdata->mii_ifp;
 954
 955         /* Find the driver associated with this PHY. */
 956         if (mii_phy_mac_match(sc, "bge"))
 957                 bge_sc = mii_phy_mac_softc(sc);
 958         else if (mii_phy_mac_match(sc, "bce"))
 959                 bce_sc = mii_phy_mac_softc(sc);
 960
 961         if (bge_sc) {
 962                 /* Fix up various bugs */
 963                 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
 964                         brgphy_fixup_5704_a0_bug(sc);
 965                 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
 966                         brgphy_fixup_adc_bug(sc);
 967                 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
 968                         brgphy_fixup_adjust_trim(sc);
 969                 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
 970                         brgphy_fixup_ber_bug(sc);
 971                 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
 972                         brgphy_fixup_crc_bug(sc);
 973                 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
 974                         brgphy_fixup_jitter_bug(sc);
 975
 976                 if (bge_sc->bge_flags & BGE_FLAG_JUMBO)
 977                         brgphy_jumbo_settings(sc, if_getmtu(ifp));
 978
 979                 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0)
 980                         brgphy_ethernet_wirespeed(sc);
 981
 982                 /* Enable Link LED on Dell boxes */
 983                 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
 984                         PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
 985                             PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
 986                             ~BRGPHY_PHY_EXTCTL_3_LED);
 987                 }
 988
 989                 /* Adjust output voltage (From Linux driver) */
 990                 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
 991                         PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
 992         } else if (bce_sc) {
 993                 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
 994                         (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
 995
 996                         /* Store autoneg capabilities/results in digital block (Page 0) */
 997                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
 998                         PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
 999                                 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
1000                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
1001
1002                         /* Enable fiber mode and autodetection */
1003                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
1004                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
1005                                 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
1006                                 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
1007
1008                         /* Enable parallel detection */
1009                         PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
1010                                 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
1011                                 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
1012
1013                         /* Advertise 2.5G support through next page during autoneg */
1014                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1015                                 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
1016                                         PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
1017                                         BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
1018
1019                         /* Increase TX signal amplitude */
1020                         if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
1021                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
1022                             (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
1023                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1024                                         BRGPHY_5708S_TX_MISC_PG5);
1025                                 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
1026                                         PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
1027                                 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1028                                         BRGPHY_5708S_DIG_PG0);
1029                         }
1030
1031                         /* Backplanes use special driver/pre-driver/pre-emphasis values. */
1032                         if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
1033                                 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
1034                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1035                                                 BRGPHY_5708S_TX_MISC_PG5);
1036                                         PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
1037                                                 bce_sc->bce_port_hw_cfg &
1038                                                 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
1039                                         PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
1040                                                 BRGPHY_5708S_DIG_PG0);
1041                         }
1042                 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
1043                         (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
1044
1045                         /* Select the SerDes Digital block of the AN MMD. */
1046                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
1047                         val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
1048                         val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
1049                         val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
1050                         PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
1051
1052                         /* Select the Over 1G block of the AN MMD. */
1053                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
1054
1055                         /* Enable autoneg "Next Page" to advertise 2.5G support. */
1056                         val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
1057                         if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1058                                 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1059                         else
1060                                 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
1061                         PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
1062
1063                         /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
1064                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
1065
1066                         /* Enable MRBE speed autoneg. */
1067                         val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
1068                         val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
1069                             BRGPHY_MRBE_MSG_PG5_NP_T2;
1070                         PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
1071
1072                         /* Select the Clause 73 User B0 block of the AN MMD. */
1073                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
1074
1075                         /* Enable MRBE speed autoneg. */
1076                         PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
1077                             BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
1078                             BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
1079                             BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
1080
1081                         /* Restore IEEE0 block (assumed in all brgphy(4) code). */
1082                         PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
1083         } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
1084                         if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
1085                                 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
1086                                 brgphy_fixup_disable_early_dac(sc);
1087
1088                         brgphy_jumbo_settings(sc, if_getmtu(ifp));
1089                         brgphy_ethernet_wirespeed(sc);
1090                 } else {
1091                         brgphy_fixup_ber_bug(sc);
1092                         brgphy_jumbo_settings(sc, if_getmtu(ifp));
1093                         brgphy_ethernet_wirespeed(sc);
1094                 }
1095         }
1096 }