3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Driver for the Cicada/Vitesse CS/VSC8xxx 10/100/1000 copper PHY.
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
48 #include <net/if_arp.h>
49 #include <net/if_media.h>
51 #include <dev/mii/mii.h>
52 #include <dev/mii/miivar.h>
55 #include <dev/mii/ciphyreg.h>
57 #include "miibus_if.h"
59 #include <machine/bus.h>
61 static int ciphy_probe(device_t);
62 static int ciphy_attach(device_t);
64 static device_method_t ciphy_methods[] = {
65 /* device interface */
66 DEVMETHOD(device_probe, ciphy_probe),
67 DEVMETHOD(device_attach, ciphy_attach),
68 DEVMETHOD(device_detach, mii_phy_detach),
69 DEVMETHOD(device_shutdown, bus_generic_shutdown),
73 static devclass_t ciphy_devclass;
75 static driver_t ciphy_driver = {
78 sizeof(struct mii_softc)
81 DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0);
83 static int ciphy_service(struct mii_softc *, struct mii_data *, int);
84 static void ciphy_status(struct mii_softc *);
85 static void ciphy_reset(struct mii_softc *);
86 static void ciphy_fixup(struct mii_softc *);
88 static const struct mii_phydesc ciphys[] = {
89 MII_PHY_DESC(xxCICADA, CS8201),
90 MII_PHY_DESC(xxCICADA, CS8201A),
91 MII_PHY_DESC(xxCICADA, CS8201B),
92 MII_PHY_DESC(xxCICADA, CS8204),
93 MII_PHY_DESC(xxCICADA, VSC8211),
94 MII_PHY_DESC(xxCICADA, VSC8221),
95 MII_PHY_DESC(xxCICADA, CS8244),
96 MII_PHY_DESC(xxVITESSE, VSC8601),
97 MII_PHY_DESC(xxVITESSE, VSC8641),
101 static const struct mii_phy_funcs ciphy_funcs = {
108 ciphy_probe(device_t dev)
111 return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT));
115 ciphy_attach(device_t dev)
118 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
124 ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
126 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
134 ciphy_fixup(sc); /* XXX hardware bug work-around */
136 switch (IFM_SUBTYPE(ife->ifm_media)) {
140 * If we're already in auto mode, just return.
142 if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
145 (void)mii_phy_auto(sc);
156 if ((ife->ifm_media & IFM_FDX) != 0) {
157 speed |= CIPHY_BMCR_FDX;
158 gig = CIPHY_1000CTL_AFD;
160 gig = CIPHY_1000CTL_AHD;
162 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
163 gig |= CIPHY_1000CTL_MSE;
164 if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
165 gig |= CIPHY_1000CTL_MSC;
167 CIPHY_BMCR_AUTOEN | CIPHY_BMCR_STARTNEG;
170 PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
171 PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
172 PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
175 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
184 * Only used for autonegotiation.
186 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
190 * Check to see if we have link. If we do, we don't
191 * need to restart the autonegotiation process. Read
192 * the BMSR twice in case it's latched.
194 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
198 /* Announce link loss right after it happens. */
199 if (++sc->mii_ticks == 0)
202 * Only retry autonegotiation every mii_anegticks seconds.
204 if (sc->mii_ticks <= sc->mii_anegticks)
212 /* Update the media status. */
216 * Callback if something changed. Note that we need to poke
217 * apply fixups for certain PHY revs.
219 if (sc->mii_media_active != mii->mii_media_active ||
220 sc->mii_media_status != mii->mii_media_status ||
221 cmd == MII_MEDIACHG) {
224 mii_phy_update(sc, cmd);
229 ciphy_status(struct mii_softc *sc)
231 struct mii_data *mii = sc->mii_pdata;
234 mii->mii_media_status = IFM_AVALID;
235 mii->mii_media_active = IFM_ETHER;
237 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
239 if (bmsr & BMSR_LINK)
240 mii->mii_media_status |= IFM_ACTIVE;
242 bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
244 if (bmcr & CIPHY_BMCR_LOOP)
245 mii->mii_media_active |= IFM_LOOP;
247 if (bmcr & CIPHY_BMCR_AUTOEN) {
248 if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
249 /* Erg, still trying, I guess... */
250 mii->mii_media_active |= IFM_NONE;
255 bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
256 switch (bmsr & CIPHY_AUXCSR_SPEED) {
258 mii->mii_media_active |= IFM_10_T;
261 mii->mii_media_active |= IFM_100_TX;
263 case CIPHY_SPEED1000:
264 mii->mii_media_active |= IFM_1000_T;
267 device_printf(sc->mii_dev, "unknown PHY speed %x\n",
268 bmsr & CIPHY_AUXCSR_SPEED);
272 if (bmsr & CIPHY_AUXCSR_FDX)
273 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
275 mii->mii_media_active |= IFM_HDX;
277 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
278 (PHY_READ(sc, CIPHY_MII_1000STS) & CIPHY_1000STS_MSR) != 0)
279 mii->mii_media_active |= IFM_ETH_MASTER;
283 ciphy_reset(struct mii_softc *sc)
290 #define PHY_SETBIT(x, y, z) \
291 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
292 #define PHY_CLRBIT(x, y, z) \
293 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
296 ciphy_fixup(struct mii_softc *sc)
299 uint16_t status, speed;
302 model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
303 status = PHY_READ(sc, CIPHY_MII_AUXCSR);
304 speed = status & CIPHY_AUXCSR_SPEED;
306 if (mii_phy_mac_match(sc, "nfe")) {
307 /* need to set for 2.5V RGMII for NVIDIA adapters */
308 val = PHY_READ(sc, CIPHY_MII_ECTL1);
309 val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL);
310 val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII);
311 PHY_WRITE(sc, CIPHY_MII_ECTL1, val);
313 val = PHY_READ(sc, CIPHY_MII_AUXCSR);
314 val |= CIPHY_AUXCSR_MDPPS;
315 PHY_WRITE(sc, CIPHY_MII_AUXCSR, val);
316 val = PHY_READ(sc, CIPHY_MII_10BTCSR);
317 val |= CIPHY_10BTCSR_ECHO;
318 PHY_WRITE(sc, CIPHY_MII_10BTCSR, val);
322 case MII_MODEL_xxCICADA_CS8204:
323 case MII_MODEL_xxCICADA_CS8201:
325 /* Turn off "aux mode" (whatever that means) */
326 PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
329 * Work around speed polling bug in VT3119/VT3216
330 * when using MII in full duplex mode.
332 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
333 (status & CIPHY_AUXCSR_FDX)) {
334 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
336 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
339 /* Enable link/activity LED blink. */
340 PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
344 case MII_MODEL_xxCICADA_CS8201A:
345 case MII_MODEL_xxCICADA_CS8201B:
348 * Work around speed polling bug in VT3119/VT3216
349 * when using MII in full duplex mode.
351 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
352 (status & CIPHY_AUXCSR_FDX)) {
353 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
355 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
359 case MII_MODEL_xxCICADA_VSC8211:
360 case MII_MODEL_xxCICADA_VSC8221:
361 case MII_MODEL_xxCICADA_CS8244:
362 case MII_MODEL_xxVITESSE_VSC8601:
363 case MII_MODEL_xxVITESSE_VSC8641:
366 device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n",