3 * Principal Author: Parag Patel
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Additional Copyright (c) 2001 by Traakan Software under same licence.
30 * Secondary Author: Matthew Jacob
34 * SPDX-License-Identifier: BSD-3-Clause
36 * Derived by information released by Intel under the following license:
38 * Copyright (c) 1999 - 2001, Intel Corporation
40 * All rights reserved.
42 * Redistribution and use in source and binary forms, with or without
43 * modification, are permitted provided that the following conditions are met:
45 * 1. Redistributions of source code must retain the above copyright notice,
46 * this list of conditions and the following disclaimer.
48 * 2. Redistributions in binary form must reproduce the above copyright notice,
49 * this list of conditions and the following disclaimer in the
50 * documentation and/or other materials provided with the distribution.
52 * 3. Neither the name of Intel Corporation nor the names of its contributors
53 * may be used to endorse or promote products derived from this software
54 * without specific prior written permission.
56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
59 * ARE DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
60 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
61 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
62 * LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
63 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
65 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
70 * Marvell E1000 PHY registers
73 #define E1000_MAX_REG_ADDRESS 0x1F
75 #define E1000_CR 0x00 /* control register */
76 #define E1000_CR_SPEED_SELECT_MSB 0x0040
77 #define E1000_CR_COLL_TEST_ENABLE 0x0080
78 #define E1000_CR_FULL_DUPLEX 0x0100
79 #define E1000_CR_RESTART_AUTO_NEG 0x0200
80 #define E1000_CR_ISOLATE 0x0400
81 #define E1000_CR_POWER_DOWN 0x0800
82 #define E1000_CR_AUTO_NEG_ENABLE 0x1000
83 #define E1000_CR_SPEED_SELECT_LSB 0x2000
84 #define E1000_CR_LOOPBACK 0x4000
85 #define E1000_CR_RESET 0x8000
87 #define E1000_CR_SPEED_1000 0x0040
88 #define E1000_CR_SPEED_100 0x2000
89 #define E1000_CR_SPEED_10 0x0000
91 #define E1000_SR 0x01 /* status register */
92 #define E1000_SR_EXTENDED 0x0001
93 #define E1000_SR_JABBER_DETECT 0x0002
94 #define E1000_SR_LINK_STATUS 0x0004
95 #define E1000_SR_AUTO_NEG 0x0008
96 #define E1000_SR_REMOTE_FAULT 0x0010
97 #define E1000_SR_AUTO_NEG_COMPLETE 0x0020
98 #define E1000_SR_PREAMBLE_SUPPRESS 0x0040
99 #define E1000_SR_EXTENDED_STATUS 0x0100
100 #define E1000_SR_100T2 0x0200
101 #define E1000_SR_100T2_FD 0x0400
102 #define E1000_SR_10T 0x0800
103 #define E1000_SR_10T_FD 0x1000
104 #define E1000_SR_100TX 0x2000
105 #define E1000_SR_100TX_FD 0x4000
106 #define E1000_SR_100T4 0x8000
108 #define E1000_ID1 0x02 /* ID register 1 */
109 #define E1000_ID2 0x03 /* ID register 2 */
110 #define E1000_ID_88E1000 0x01410C50
111 #define E1000_ID_88E1000S 0x01410C40
112 #define E1000_ID_88E1011 0x01410C20
113 #define E1000_ID_MASK 0xFFFFFFF0
115 #define E1000_AR 0x04 /* autonegotiation advertise reg */
116 #define E1000_AR_SELECTOR_FIELD 0x0001
117 #define E1000_AR_10T 0x0020
118 #define E1000_AR_10T_FD 0x0040
119 #define E1000_AR_100TX 0x0080
120 #define E1000_AR_100TX_FD 0x0100
121 #define E1000_AR_100T4 0x0200
122 #define E1000_AR_PAUSE 0x0400
123 #define E1000_AR_ASM_DIR 0x0800
124 #define E1000_AR_REMOTE_FAULT 0x2000
125 #define E1000_AR_NEXT_PAGE 0x8000
126 #define E1000_AR_SPEED_MASK 0x01E0
128 /* Autonegotiation register bits for fiber cards (Alaska Only!) */
129 #define E1000_FA_1000X_FD 0x0020
130 #define E1000_FA_1000X 0x0040
131 #define E1000_FA_SYM_PAUSE 0x0080
132 #define E1000_FA_ASYM_PAUSE 0x0100
133 #define E1000_FA_FAULT1 0x1000
134 #define E1000_FA_FAULT2 0x2000
135 #define E1000_FA_NEXT_PAGE 0x8000
137 #define E1000_LPAR 0x05 /* autoneg link partner abilities reg */
138 #define E1000_LPAR_SELECTOR_FIELD 0x0001
139 #define E1000_LPAR_10T 0x0020
140 #define E1000_LPAR_10T_FD 0x0040
141 #define E1000_LPAR_100TX 0x0080
142 #define E1000_LPAR_100TX_FD 0x0100
143 #define E1000_LPAR_100T4 0x0200
144 #define E1000_LPAR_PAUSE 0x0400
145 #define E1000_LPAR_ASM_DIR 0x0800
146 #define E1000_LPAR_REMOTE_FAULT 0x2000
147 #define E1000_LPAR_ACKNOWLEDGE 0x4000
148 #define E1000_LPAR_NEXT_PAGE 0x8000
150 /* autoneg link partner ability register bits for fiber cards (Alaska Only!) */
151 #define E1000_FPAR_1000X_FD 0x0020
152 #define E1000_FPAR_1000X 0x0040
153 #define E1000_FPAR_SYM_PAUSE 0x0080
154 #define E1000_FPAR_ASYM_PAUSE 0x0100
155 #define E1000_FPAR_FAULT1 0x1000
156 #define E1000_FPAR_FAULT2 0x2000
157 #define E1000_FPAR_ACK 0x4000
158 #define E1000_FPAR_NEXT_PAGE 0x8000
160 #define E1000_ER 0x06 /* autoneg expansion reg */
161 #define E1000_ER_LP_NWAY 0x0001
162 #define E1000_ER_PAGE_RXD 0x0002
163 #define E1000_ER_NEXT_PAGE 0x0004
164 #define E1000_ER_LP_NEXT_PAGE 0x0008
165 #define E1000_ER_PAR_DETECT_FAULT 0x0100
167 #define E1000_NPTX 0x07 /* autoneg next page TX */
168 #define E1000_NPTX_MSG_CODE_FIELD 0x0001
169 #define E1000_NPTX_TOGGLE 0x0800
170 #define E1000_NPTX_ACKNOWLDGE2 0x1000
171 #define E1000_NPTX_MSG_PAGE 0x2000
172 #define E1000_NPTX_NEXT_PAGE 0x8000
174 #define E1000_RNPR 0x08 /* autoneg link-partner (?) next page */
175 #define E1000_RNPR_MSG_CODE_FIELD 0x0001
176 #define E1000_RNPR_TOGGLE 0x0800
177 #define E1000_RNPR_ACKNOWLDGE2 0x1000
178 #define E1000_RNPR_MSG_PAGE 0x2000
179 #define E1000_RNPR_ACKNOWLDGE 0x4000
180 #define E1000_RNPR_NEXT_PAGE 0x8000
182 #define E1000_1GCR 0x09 /* 1000T (1G) control reg */
183 #define E1000_1GCR_ASYM_PAUSE 0x0080
184 #define E1000_1GCR_1000T 0x0100
185 #define E1000_1GCR_1000T_FD 0x0200
186 #define E1000_1GCR_REPEATER_DTE 0x0400
187 #define E1000_1GCR_MS_VALUE 0x0800
188 #define E1000_1GCR_MS_ENABLE 0x1000
189 #define E1000_1GCR_TEST_MODE_NORMAL 0x0000
190 #define E1000_1GCR_TEST_MODE_1 0x2000
191 #define E1000_1GCR_TEST_MODE_2 0x4000
192 #define E1000_1GCR_TEST_MODE_3 0x6000
193 #define E1000_1GCR_TEST_MODE_4 0x8000
194 #define E1000_1GCR_SPEED_MASK 0x0300
196 #define E1000_1GSR 0x0A /* 1000T (1G) status reg */
197 #define E1000_1GSR_IDLE_ERROR_CNT 0x0000
198 #define E1000_1GSR_ASYM_PAUSE_DIR 0x0100
199 #define E1000_1GSR_LP 0x0400
200 #define E1000_1GSR_LP_FD 0x0800
201 #define E1000_1GSR_REMOTE_RX_STATUS 0x1000
202 #define E1000_1GSR_LOCAL_RX_STATUS 0x2000
203 #define E1000_1GSR_MS_CONFIG_RES 0x4000
204 #define E1000_1GSR_MS_CONFIG_FAULT 0x8000
206 #define E1000_ESR 0x0F /* IEEE extended status reg */
207 #define E1000_ESR_1000T 0x1000
208 #define E1000_ESR_1000T_FD 0x2000
209 #define E1000_ESR_1000X 0x4000
210 #define E1000_ESR_1000X_FD 0x8000
212 #define E1000_TX_POLARITY_MASK 0x0100
213 #define E1000_TX_NORMAL_POLARITY 0
215 #define E1000_AUTO_POLARITY_DISABLE 0x0010
217 #define E1000_SCR 0x10 /* special control register */
218 #define E1000_SCR_JABBER_DISABLE 0x0001
219 #define E1000_SCR_POLARITY_REVERSAL 0x0002
220 #define E1000_SCR_SQE_TEST 0x0004
221 #define E1000_SCR_INT_FIFO_DISABLE 0x0008
222 #define E1000_SCR_CLK125_DISABLE 0x0010
223 #define E1000_SCR_MDI_MANUAL_MODE 0x0000
224 #define E1000_SCR_MDIX_MANUAL_MODE 0x0020
225 #define E1000_SCR_AUTO_X_1000T 0x0040
226 #define E1000_SCR_AUTO_X_MODE 0x0060
227 #define E1000_SCR_10BT_EXT_ENABLE 0x0080
228 #define E1000_SCR_MII_5BIT_ENABLE 0x0100
229 #define E1000_SCR_SCRAMBLER_DISABLE 0x0200
230 #define E1000_SCR_FORCE_LINK_GOOD 0x0400
231 #define E1000_SCR_ASSERT_CRS_ON_TX 0x0800
232 #define E1000_SCR_RX_FIFO_DEPTH_6 0x0000
233 #define E1000_SCR_RX_FIFO_DEPTH_8 0x1000
234 #define E1000_SCR_RX_FIFO_DEPTH_10 0x2000
235 #define E1000_SCR_RX_FIFO_DEPTH_12 0x3000
236 #define E1000_SCR_TX_FIFO_DEPTH_6 0x0000
237 #define E1000_SCR_TX_FIFO_DEPTH_8 0x4000
238 #define E1000_SCR_TX_FIFO_DEPTH_10 0x8000
239 #define E1000_SCR_TX_FIFO_DEPTH_12 0xC000
242 #define E1000_SCR_AUTO_MDIX 0x0030
243 #define E1000_SCR_SIGDET_POLARITY 0x0040
244 #define E1000_SCR_EXT_DISTANCE 0x0080
245 #define E1000_SCR_FEFI_DISABLE 0x0100
246 #define E1000_SCR_NLP_GEN_DISABLE 0x0800
247 #define E1000_SCR_LPNP 0x1000
248 #define E1000_SCR_NLP_CHK_DISABLE 0x2000
249 #define E1000_SCR_EN_DETECT 0x4000
251 #define E1000_SCR_EN_DETECT_MASK 0x0300
253 /* 88E1112 page 1 fiber specific control */
254 #define E1000_SCR_FIB_TX_DIS 0x0008
255 #define E1000_SCR_FIB_SIGDET_POLARITY 0x0200
256 #define E1000_SCR_FIB_FORCE_LINK 0x0400
259 #define E1000_SCR_MODE_MASK 0x0380
260 #define E1000_SCR_MODE_AUTO 0x0180
261 #define E1000_SCR_MODE_COPPER 0x0280
262 #define E1000_SCR_MODE_1000BX 0x0380
265 #define E1000_SCR_POWER_DOWN 0x0004
266 /* 88E1116, 88E1149 page 2 */
267 #define E1000_SCR_RGMII_POWER_UP 0x0008
269 /* 88E1116, 88E1149 page 3 */
270 #define E1000_SCR_LED_STAT0_MASK 0x000F
271 #define E1000_SCR_LED_STAT1_MASK 0x00F0
272 #define E1000_SCR_LED_INIT_MASK 0x0F00
273 #define E1000_SCR_LED_LOS_MASK 0xF000
274 #define E1000_SCR_LED_STAT0(x) ((x) & E1000_SCR_LED_STAT0_MASK)
275 #define E1000_SCR_LED_STAT1(x) ((x) & E1000_SCR_LED_STAT1_MASK)
276 #define E1000_SCR_LED_INIT(x) ((x) & E1000_SCR_LED_INIT_MASK)
277 #define E1000_SCR_LED_LOS(x) ((x) & E1000_SCR_LED_LOS_MASK)
279 #define E1000_SSR 0x11 /* special status register */
280 #define E1000_SSR_JABBER 0x0001
281 #define E1000_SSR_REV_POLARITY 0x0002
282 #define E1000_SSR_MDIX 0x0020
283 #define E1000_SSR_LINK 0x0400
284 #define E1000_SSR_SPD_DPLX_RESOLVED 0x0800
285 #define E1000_SSR_PAGE_RCVD 0x1000
286 #define E1000_SSR_DUPLEX 0x2000
287 #define E1000_SSR_SPEED 0xC000
288 #define E1000_SSR_10MBS 0x0000
289 #define E1000_SSR_100MBS 0x4000
290 #define E1000_SSR_1000MBS 0x8000
292 #define E1000_IER 0x12 /* interrupt enable reg */
293 #define E1000_IER_JABBER 0x0001
294 #define E1000_IER_POLARITY_CHANGE 0x0002
295 #define E1000_IER_MDIX_CHANGE 0x0040
296 #define E1000_IER_FIFO_OVER_UNDERUN 0x0080
297 #define E1000_IER_FALSE_CARRIER 0x0100
298 #define E1000_IER_SYMBOL_ERROR 0x0200
299 #define E1000_IER_LINK_STAT_CHANGE 0x0400
300 #define E1000_IER_AUTO_NEG_COMPLETE 0x0800
301 #define E1000_IER_PAGE_RECEIVED 0x1000
302 #define E1000_IER_DUPLEX_CHANGED 0x2000
303 #define E1000_IER_SPEED_CHANGED 0x4000
304 #define E1000_IER_AUTO_NEG_ERR 0x8000
306 /* 88E1116, 88E1149 page 3, LED timer control. */
307 #define E1000_PULSE_MASK 0x7000
308 #define E1000_PULSE_NO_STR 0 /* no pulse stretching */
309 #define E1000_PULSE_21MS 1 /* 21 ms to 42 ms */
310 #define E1000_PULSE_42MS 2 /* 42 ms to 84 ms */
311 #define E1000_PULSE_84MS 3 /* 84 ms to 170 ms */
312 #define E1000_PULSE_170MS 4 /* 170 ms to 340 ms */
313 #define E1000_PULSE_340MS 5 /* 340 ms to 670 ms */
314 #define E1000_PULSE_670MS 6 /* 670 ms to 1300 ms */
315 #define E1000_PULSE_1300MS 7 /* 1300 ms to 2700 ms */
316 #define E1000_PULSE_DUR(x) ((x) & E1000_PULSE_MASK)
318 #define E1000_BLINK_MASK 0x0700
319 #define E1000_BLINK_42MS 0 /* 42 ms */
320 #define E1000_BLINK_84MS 1 /* 84 ms */
321 #define E1000_BLINK_170MS 2 /* 170 ms */
322 #define E1000_BLINK_340MS 3 /* 340 ms */
323 #define E1000_BLINK_670MS 4 /* 670 ms */
324 #define E1000_BLINK_RATE(x) ((x) & E1000_BLINK_MASK)
326 #define E1000_ISR 0x13 /* interrupt status reg */
327 #define E1000_ISR_JABBER 0x0001
328 #define E1000_ISR_POLARITY_CHANGE 0x0002
329 #define E1000_ISR_MDIX_CHANGE 0x0040
330 #define E1000_ISR_FIFO_OVER_UNDERUN 0x0080
331 #define E1000_ISR_FALSE_CARRIER 0x0100
332 #define E1000_ISR_SYMBOL_ERROR 0x0200
333 #define E1000_ISR_LINK_STAT_CHANGE 0x0400
334 #define E1000_ISR_AUTO_NEG_COMPLETE 0x0800
335 #define E1000_ISR_PAGE_RECEIVED 0x1000
336 #define E1000_ISR_DUPLEX_CHANGED 0x2000
337 #define E1000_ISR_SPEED_CHANGED 0x4000
338 #define E1000_ISR_AUTO_NEG_ERR 0x8000
340 #define E1000_ESCR 0x14 /* extended special control reg */
341 #define E1000_ESCR_FIBER_LOOPBACK 0x4000
342 #define E1000_ESCR_DOWN_NO_IDLE 0x8000
343 #define E1000_ESCR_TX_CLK_2_5 0x0060
344 #define E1000_ESCR_TX_CLK_25 0x0070
345 #define E1000_ESCR_TX_CLK_0 0x0000
347 #define E1000_RECR 0x15 /* RX error counter reg */
349 #define E1000_EADR 0x16 /* extended address reg */
351 #define E1000_LCR 0x18 /* LED control reg */
352 #define E1000_LCR_LED_TX 0x0001
353 #define E1000_LCR_LED_RX 0x0002
354 #define E1000_LCR_LED_DUPLEX 0x0004
355 #define E1000_LCR_LINK 0x0008
356 #define E1000_LCR_BLINK_42MS 0x0000
357 #define E1000_LCR_BLINK_84MS 0x0100
358 #define E1000_LCR_BLINK_170MS 0x0200
359 #define E1000_LCR_BLINK_340MS 0x0300
360 #define E1000_LCR_BLINK_670MS 0x0400
361 #define E1000_LCR_PULSE_OFF 0x0000
362 #define E1000_LCR_PULSE_21_42MS 0x1000
363 #define E1000_LCR_PULSE_42_84MS 0x2000
364 #define E1000_LCR_PULSE_84_170MS 0x3000
365 #define E1000_LCR_PULSE_170_340MS 0x4000
366 #define E1000_LCR_PULSE_340_670MS 0x5000
367 #define E1000_LCR_PULSE_670_13S 0x6000
368 #define E1000_LCR_PULSE_13_26S 0x7000
370 /* The following register is found only on the 88E1011 Alaska PHY */
371 #define E1000_ESSR 0x1B /* Extended PHY specific sts */
372 #define E1000_ESSR_FIBER_LINK 0x2000
373 #define E1000_ESSR_GMII_COPPER 0x000f
374 #define E1000_ESSR_GMII_FIBER 0x0007
375 #define E1000_ESSR_TBI_COPPER 0x000d
376 #define E1000_ESSR_TBI_FIBER 0x0005