sys/dev/mii/jmphyreg.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2008, Pyun YongHyeon
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice unmodified, this list of conditions, and the following
  12  *    disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  * $FreeBSD$
  30  */
  31
  32 #ifndef _DEV_MII_JMPHYREG_H_
  33 #define _DEV_MII_JMPHYREG_H_
  34
  35 /*
  36  * Registers for the JMicron JMC250 Gigabit PHY.
  37  */
  38
  39 /* PHY specific status register. */
  40 #define JMPHY_SSR                       0x11
  41 #define JMPHY_SSR_SPEED_1000            0x8000
  42 #define JMPHY_SSR_SPEED_100             0x4000
  43 #define JMPHY_SSR_SPEED_10              0x0000
  44 #define JMPHY_SSR_SPEED_MASK            0xC000
  45 #define JMPHY_SSR_DUPLEX                0x2000
  46 #define JMPHY_SSR_SPD_DPLX_RESOLVED     0x0800
  47 #define JMPHY_SSR_LINK_UP               0x0400
  48 #define JMPHY_SSR_MDI_XOVER             0x0040
  49 #define JMPHY_SSR_INV_POLARITY          0x0002
  50
  51 /* PHY specific cable length status register. */
  52 #define JMPHY_SCL                       0x17
  53 #define JMPHY_SCL_CHAN_D_MASK           0xF000
  54 #define JMPHY_SCL_CHAN_C_MASK           0x0F00
  55 #define JMPHY_SCL_CHAN_B_MASK           0x00F0
  56 #define JMPHY_SCL_CHAN_A_MASK           0x000F
  57 #define JMPHY_SCL_LEN_35                0
  58 #define JMPHY_SCL_LEN_40                1
  59 #define JMPHY_SCL_LEN_50                2
  60 #define JMPHY_SCL_LEN_60                3
  61 #define JMPHY_SCL_LEN_70                4
  62 #define JMPHY_SCL_LEN_80                5
  63 #define JMPHY_SCL_LEN_90                6
  64 #define JMPHY_SCL_LEN_100               7
  65 #define JMPHY_SCL_LEN_110               8
  66 #define JMPHY_SCL_LEN_120               9
  67 #define JMPHY_SCL_LEN_130               10
  68 #define JMPHY_SCL_LEN_140               11
  69 #define JMPHY_SCL_LEN_150               12
  70 #define JMPHY_SCL_LEN_160               13
  71 #define JMPHY_SCL_LEN_170               14
  72 #define JMPHY_SCL_RSVD                  15
  73
  74 /* PHY specific LED control register 1. */
  75 #define JMPHY_LED_CTL1                  0x18
  76 #define JMPHY_LED_BLINK_42MS            0x0000
  77 #define JMPHY_LED_BLINK_84MS            0x2000
  78 #define JMPHY_LED_BLINK_170MS           0x4000
  79 #define JMPHY_LED_BLINK_340MS           0x6000
  80 #define JMPHY_LED_BLINK_670MS           0x8000
  81 #define JMPHY_LED_BLINK_MASK            0xE000
  82 #define JMPHY_LED_FLP_GAP_MASK          0x1F00
  83 #define JMPHY_LED_FLP_GAP_DEFULT        0x1000
  84 #define JMPHY_LED2_POLARITY_MASK        0x0030
  85 #define JMPHY_LED1_POLARITY_MASK        0x000C
  86 #define JMPHY_LED0_POLARITY_MASK        0x0003
  87 #define JMPHY_LED_ON_LO_OFF_HI          0
  88 #define JMPHY_LED_ON_HI_OFF_HI          1
  89 #define JMPHY_LED_ON_LO_OFF_TS          2
  90 #define JMPHY_LED_ON_HI_OFF_TS          3
  91
  92 /* PHY specific LED control register 2. */
  93 #define JMPHY_LED_CTL2                  0x19
  94 #define JMPHY_LED_NO_STRETCH            0x0000
  95 #define JMPHY_LED_STRETCH_42MS          0x2000
  96 #define JMPHY_LED_STRETCH_84MS          0x4000
  97 #define JMPHY_LED_STRETCH_170MS         0x6000
  98 #define JMPHY_LED_STRETCH_340MS         0x8000
  99 #define JMPHY_LED_STRETCH_670MS         0xB000
 100 #define JMPHY_LED_STRETCH_1300MS        0xC000
 101 #define JMPHY_LED_STRETCH_2700MS        0xE000
 102 #define JMPHY_LED2_MODE_MASK            0x0F00
 103 #define JMPHY_LED1_MODE_MASK            0x00F0
 104 #define JMPHY_LED0_MODE_MASK            0x000F
 105
 106 /* PHY specific test mode control register. */
 107 #define JMPHY_TMCTL                     0x1A
 108 #define JMPHY_TMCTL_SLEEP_ENB           0x1000
 109
 110 /* PHY specific configuration register. */
 111 #define JMPHY_SPEC_ADDR                 0x1E
 112 #define JMPHY_SPEC_ADDR_READ            0x4000
 113 #define JMPHY_SPEC_ADDR_WRITE           0x8000
 114
 115 #define JMPHY_SPEC_DATA                 0x1F
 116
 117 #define JMPHY_EXT_COMM_2                0x32
 118
 119 #endif  /* _DEV_MII_JMPHYREG_H_ */