2 * Copyright (c) 2014,2019 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * Micrel KSZ8081/KSZ9021/KSZ9031 Gigabit Ethernet Transceiver
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/errno.h>
43 #include <sys/module.h>
45 #include <sys/malloc.h>
47 #include <machine/bus.h>
50 #include <net/if_media.h>
52 #include <dev/mii/mii.h>
53 #include <dev/mii/miivar.h>
56 #include "miibus_if.h"
58 #include <dev/fdt/fdt_common.h>
59 #include <dev/ofw/openfirm.h>
60 #include <dev/ofw/ofw_bus.h>
61 #include <dev/ofw/ofw_bus_subr.h>
62 #include <dev/mii/mii_fdt.h>
64 #define MII_KSZPHY_EXTREG 0x0b
65 #define KSZPHY_EXTREG_WRITE (1 << 15)
66 #define MII_KSZPHY_EXTREG_WRITE 0x0c
67 #define MII_KSZPHY_EXTREG_READ 0x0d
68 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
69 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
70 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
72 #define MII_KSZ9031_MMD_ACCESS_CTRL 0x0d
73 #define MII_KSZ9031_MMD_ACCESS_DATA 0x0e
74 #define MII_KSZ9031_MMD_DATA_NOINC (1 << 14)
75 #define MII_KSZ9031_CONTROL_PAD_SKEW 0x4
76 #define MII_KSZ9031_RX_DATA_PAD_SKEW 0x5
77 #define MII_KSZ9031_TX_DATA_PAD_SKEW 0x6
78 #define MII_KSZ9031_CLOCK_PAD_SKEW 0x8
80 #define MII_KSZ8081_PHYCTL2 0x1f
82 #define PS_TO_REG(p) ((p) / 200)
84 static int micphy_probe(device_t);
85 static int micphy_attach(device_t);
86 static void micphy_reset(struct mii_softc *);
87 static int micphy_service(struct mii_softc *, struct mii_data *, int);
89 static device_method_t micphy_methods[] = {
90 /* device interface */
91 DEVMETHOD(device_probe, micphy_probe),
92 DEVMETHOD(device_attach, micphy_attach),
93 DEVMETHOD(device_detach, mii_phy_detach),
94 DEVMETHOD(device_shutdown, bus_generic_shutdown),
98 static devclass_t micphy_devclass;
100 static driver_t micphy_driver = {
103 sizeof(struct mii_softc)
106 DRIVER_MODULE(micphy, miibus, micphy_driver, micphy_devclass, 0, 0);
108 static const struct mii_phydesc micphys[] = {
109 MII_PHY_DESC(MICREL, KSZ8081),
110 MII_PHY_DESC(MICREL, KSZ9021),
111 MII_PHY_DESC(MICREL, KSZ9031),
115 static const struct mii_phy_funcs micphy_funcs = {
122 ksz9031_read(struct mii_softc *sc, uint32_t devaddr, uint32_t reg)
124 /* Set up device address and register. */
125 PHY_WRITE(sc, MII_KSZ9031_MMD_ACCESS_CTRL, devaddr);
126 PHY_WRITE(sc, MII_KSZ9031_MMD_ACCESS_DATA, reg);
128 /* Select register data for MMD and read the value. */
129 PHY_WRITE(sc, MII_KSZ9031_MMD_ACCESS_CTRL,
130 MII_KSZ9031_MMD_DATA_NOINC | devaddr);
132 return (PHY_READ(sc, MII_KSZ9031_MMD_ACCESS_DATA));
136 ksz9031_write(struct mii_softc *sc, uint32_t devaddr, uint32_t reg,
140 /* Set up device address and register. */
141 PHY_WRITE(sc, MII_KSZ9031_MMD_ACCESS_CTRL, devaddr);
142 PHY_WRITE(sc, MII_KSZ9031_MMD_ACCESS_DATA, reg);
144 /* Select register data for MMD and write the value. */
145 PHY_WRITE(sc, MII_KSZ9031_MMD_ACCESS_CTRL,
146 MII_KSZ9031_MMD_DATA_NOINC | devaddr);
147 PHY_WRITE(sc, MII_KSZ9031_MMD_ACCESS_DATA, val);
151 ksz9021_read(struct mii_softc *sc, uint32_t reg)
154 PHY_WRITE(sc, MII_KSZPHY_EXTREG, reg);
156 return (PHY_READ(sc, MII_KSZPHY_EXTREG_READ));
160 ksz9021_write(struct mii_softc *sc, uint32_t reg, uint32_t val)
163 PHY_WRITE(sc, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | reg);
164 PHY_WRITE(sc, MII_KSZPHY_EXTREG_WRITE, val);
168 ksz90x1_load_values(struct mii_softc *sc, phandle_t node,
169 uint32_t dev, uint32_t reg, char *field1, uint32_t f1mask, int f1off,
170 char *field2, uint32_t f2mask, int f2off, char *field3, uint32_t f3mask,
171 int f3off, char *field4, uint32_t f4mask, int f4off)
173 pcell_t dts_value[1];
177 if (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ9031)
178 val = ksz9031_read(sc, dev, reg);
180 val = ksz9021_read(sc, reg);
182 if ((len = OF_getproplen(node, field1)) > 0) {
183 OF_getencprop(node, field1, dts_value, len);
184 val &= ~(f1mask << f1off);
185 val |= (PS_TO_REG(dts_value[0]) & f1mask) << f1off;
188 if (field2 != NULL && (len = OF_getproplen(node, field2)) > 0) {
189 OF_getencprop(node, field2, dts_value, len);
190 val &= ~(f2mask << f2off);
191 val |= (PS_TO_REG(dts_value[0]) & f2mask) << f2off;
194 if (field3 != NULL && (len = OF_getproplen(node, field3)) > 0) {
195 OF_getencprop(node, field3, dts_value, len);
196 val &= ~(f3mask << f3off);
197 val |= (PS_TO_REG(dts_value[0]) & f3mask) << f3off;
200 if (field4 != NULL && (len = OF_getproplen(node, field4)) > 0) {
201 OF_getencprop(node, field4, dts_value, len);
202 val &= ~(f4mask << f4off);
203 val |= (PS_TO_REG(dts_value[0]) & f4mask) << f4off;
206 if (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ9031)
207 ksz9031_write(sc, dev, reg, val);
209 ksz9021_write(sc, reg, val);
213 ksz9031_load_values(struct mii_softc *sc, phandle_t node)
216 ksz90x1_load_values(sc, node, 2, MII_KSZ9031_CONTROL_PAD_SKEW,
217 "txen-skew-ps", 0xf, 0, "rxdv-skew-ps", 0xf, 4,
218 NULL, 0, 0, NULL, 0, 0);
219 ksz90x1_load_values(sc, node, 2, MII_KSZ9031_RX_DATA_PAD_SKEW,
220 "rxd0-skew-ps", 0xf, 0, "rxd1-skew-ps", 0xf, 4,
221 "rxd2-skew-ps", 0xf, 8, "rxd3-skew-ps", 0xf, 12);
222 ksz90x1_load_values(sc, node, 2, MII_KSZ9031_TX_DATA_PAD_SKEW,
223 "txd0-skew-ps", 0xf, 0, "txd1-skew-ps", 0xf, 4,
224 "txd2-skew-ps", 0xf, 8, "txd3-skew-ps", 0xf, 12);
225 ksz90x1_load_values(sc, node, 2, MII_KSZ9031_CLOCK_PAD_SKEW,
226 "rxc-skew-ps", 0x1f, 0, "txc-skew-ps", 0x1f, 5,
227 NULL, 0, 0, NULL, 0, 0);
231 ksz9021_load_values(struct mii_softc *sc, phandle_t node)
234 ksz90x1_load_values(sc, node, 0, MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
235 "txen-skew-ps", 0xf, 0, "txc-skew-ps", 0xf, 4,
236 "rxdv-skew-ps", 0xf, 8, "rxc-skew-ps", 0xf, 12);
237 ksz90x1_load_values(sc, node, 0, MII_KSZPHY_RX_DATA_PAD_SKEW,
238 "rxd0-skew-ps", 0xf, 0, "rxd1-skew-ps", 0xf, 4,
239 "rxd2-skew-ps", 0xf, 8, "rxd3-skew-ps", 0xf, 12);
240 ksz90x1_load_values(sc, node, 0, MII_KSZPHY_TX_DATA_PAD_SKEW,
241 "txd0-skew-ps", 0xf, 0, "txd1-skew-ps", 0xf, 4,
242 "txd2-skew-ps", 0xf, 8, "txd3-skew-ps", 0xf, 12);
246 micphy_probe(device_t dev)
249 return (mii_phy_dev_probe(dev, micphys, BUS_PROBE_DEFAULT));
253 micphy_attach(device_t dev)
255 mii_fdt_phy_config_t *cfg;
256 struct mii_softc *sc;
261 sc = device_get_softc(dev);
263 mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &micphy_funcs, 1);
264 mii_phy_setmedia(sc);
266 /* Nothing further to configure for 8081 model. */
267 if (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ8081)
270 miibus = device_get_parent(dev);
271 parent = device_get_parent(miibus);
273 if ((node = ofw_bus_get_node(parent)) == -1)
276 cfg = mii_fdt_get_config(dev);
278 if (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ9031)
279 ksz9031_load_values(sc, cfg->phynode);
281 ksz9021_load_values(sc, cfg->phynode);
287 micphy_reset(struct mii_softc *sc)
292 * The 8081 has no "sticky bits" that survive a soft reset; several bits
293 * in the Phy Control Register 2 must be preserved across the reset.
294 * These bits are set up by the bootloader; they control how the phy
295 * interfaces to the board (such as clock frequency and LED behavior).
297 if (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ8081)
298 reg = PHY_READ(sc, MII_KSZ8081_PHYCTL2);
300 if (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ8081)
301 PHY_WRITE(sc, MII_KSZ8081_PHYCTL2, reg);
305 micphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
313 mii_phy_setmedia(sc);
317 if (mii_phy_tick(sc) == EJUSTRETURN)
322 /* Update the media status. */
325 /* Callback if something changed. */
326 mii_phy_update(sc, cmd);