2 * Copyright (c) 2001 Wind River Systems
4 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
37 * Driver for the National Semiconductor DP83891 and DP83861
39 * Datasheet available at: http://www.national.com/ds/DP/DP83861.pdf
41 * The DP83891 is the older NatSemi gigE PHY which isn't being sold
42 * anymore. The DP83861 is its replacement, which is an 'enhanced'
43 * firmware driven component. The major difference between the
44 * two is that the 83891 can't generate interrupts, while the
45 * 83861 can. (I think it wasn't originally designed to do this, but
46 * it can now thanks to firmware updates.) The 83861 also allows
47 * access to its internal RAM via indirect register access.
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/malloc.h>
54 #include <sys/socket.h>
57 #include <machine/clock.h>
60 #include <net/if_media.h>
62 #include <dev/mii/mii.h>
63 #include <dev/mii/miivar.h>
64 #include <dev/mii/miidevs.h>
66 #include <dev/mii/nsgphyreg.h>
68 #include "miibus_if.h"
71 static const char rcsid[] =
75 static int nsgphy_probe (device_t);
76 static int nsgphy_attach (device_t);
77 static int nsgphy_detach (device_t);
79 static device_method_t nsgphy_methods[] = {
80 /* device interface */
81 DEVMETHOD(device_probe, nsgphy_probe),
82 DEVMETHOD(device_attach, nsgphy_attach),
83 DEVMETHOD(device_detach, nsgphy_detach),
84 DEVMETHOD(device_shutdown, bus_generic_shutdown),
88 static devclass_t nsgphy_devclass;
90 static driver_t nsgphy_driver = {
93 sizeof(struct mii_softc)
96 DRIVER_MODULE(nsgphy, miibus, nsgphy_driver, nsgphy_devclass, 0, 0);
98 static int nsgphy_service(struct mii_softc *, struct mii_data *,int);
99 static void nsgphy_status(struct mii_softc *);
100 static int nsgphy_mii_phy_auto(struct mii_softc *, int);
101 extern void mii_phy_auto_timeout(void *);
104 nsgphy_probe(device_t dev)
106 struct mii_attach_args *ma;
108 ma = device_get_ivars(dev);
110 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_NATSEMI) {
111 if (MII_MODEL(ma->mii_id2) == MII_MODEL_NATSEMI_DP83891) {
112 device_set_desc(dev, MII_STR_NATSEMI_DP83891);
115 if (MII_MODEL(ma->mii_id2) == MII_MODEL_NATSEMI_DP83861) {
116 device_set_desc(dev, MII_STR_NATSEMI_DP83861);
125 nsgphy_attach(device_t dev)
127 struct mii_softc *sc;
128 struct mii_attach_args *ma;
129 struct mii_data *mii;
130 const char *sep = "";
132 sc = device_get_softc(dev);
133 ma = device_get_ivars(dev);
134 sc->mii_dev = device_get_parent(dev);
135 mii = device_get_softc(sc->mii_dev);
136 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
138 sc->mii_inst = mii->mii_instance;
139 sc->mii_phy = ma->mii_phyno;
140 sc->mii_service = nsgphy_service;
143 sc->mii_flags |= MIIF_NOISOLATE;
146 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
147 #define PRINT(s) printf("%s%s", sep, s); sep = ", "
149 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
152 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
153 BMCR_LOOP|BMCR_S100);
158 device_printf(dev, " ");
159 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst),
160 BMCR_S1000|BMCR_FDX);
161 PRINT("1000baseTX-FDX");
162 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
165 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) |
166 (BMSR_10TFDX|BMSR_10THDX)) & ma->mii_capmask;
167 if (sc->mii_capabilities & BMSR_EXTSTAT)
168 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
169 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
171 PRINT("100baseTX-FDX");
172 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst), BMCR_S100);
174 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
176 PRINT("10baseT-FDX");
177 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst), BMCR_S10);
179 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
185 MIIBUS_MEDIAINIT(sc->mii_dev);
190 nsgphy_detach(device_t dev)
192 struct mii_softc *sc;
193 struct mii_data *mii;
195 sc = device_get_softc(dev);
196 mii = device_get_softc(device_get_parent(dev));
197 if (sc->mii_flags & MIIF_DOINGAUTO)
198 untimeout(mii_phy_auto_timeout, sc, sc->mii_auto_ch);
200 LIST_REMOVE(sc, mii_list);
206 nsgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
208 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
214 * If we're not polling our PHY instance, just return.
216 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
222 * If the media indicates a different PHY instance,
225 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
226 reg = PHY_READ(sc, MII_BMCR);
227 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
232 * If the interface is not up, don't do anything.
234 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
238 switch (IFM_SUBTYPE(ife->ifm_media)) {
242 * If we're already in auto mode, just return.
244 if (PHY_READ(sc, MII_BMCR) & BMCR_AUTOEN)
247 (void) nsgphy_mii_phy_auto(sc, 0);
250 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
251 PHY_WRITE(sc, MII_BMCR,
252 BMCR_FDX|BMCR_SPEED1);
254 PHY_WRITE(sc, MII_BMCR,
257 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA);
260 * When setting the link manually, one side must
261 * be the master and the other the slave. However
262 * ifmedia doesn't give us a good way to specify
263 * this, so we fake it by using one of the LINK
264 * flags. If LINK0 is set, we program the PHY to
265 * be a master, otherwise it's a slave.
267 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
268 PHY_WRITE(sc, MII_100T2CR,
269 GTCR_MAN_MS|GTCR_ADV_MS);
271 PHY_WRITE(sc, MII_100T2CR, GTCR_MAN_MS);
276 * XXX Not supported as a manual setting right now.
280 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
284 * BMCR data is stored in the ifmedia entry.
286 PHY_WRITE(sc, MII_ANAR, mii_anar(ife->ifm_media));
287 PHY_WRITE(sc, MII_BMCR, ife->ifm_data);
294 * If we're not currently selected, just return.
296 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
300 * Is the interface even up?
302 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
306 * Only used for autonegotiation.
308 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
312 * Check to see if we have link.
314 reg = PHY_READ(sc, NSGPHY_MII_PHYSUP);
315 if (reg & NSGPHY_PHYSUP_LNKSTS)
319 * Only retry autonegotiation every 5 seconds.
320 * Actually, for gigE PHYs, we should wait longer, since
321 * 5 seconds is the mimimum time the documentation
322 * says to wait for a 1000mbps link to be established.
324 if (++sc->mii_ticks != 10)
330 if (nsgphy_mii_phy_auto(sc, 0) == EJUSTRETURN)
335 /* Update the media status. */
338 /* Callback if something changed. */
339 mii_phy_update(sc, cmd);
344 nsgphy_status(struct mii_softc *sc)
346 struct mii_data *mii = sc->mii_pdata;
347 int bmsr, bmcr, physup, anlpar, gstat;
349 mii->mii_media_status = IFM_AVALID;
350 mii->mii_media_active = IFM_ETHER;
352 bmsr = PHY_READ(sc, MII_BMSR);
354 physup = PHY_READ(sc, NSGPHY_MII_PHYSUP);
356 if (physup & NSGPHY_PHYSUP_LNKSTS)
357 mii->mii_media_status |= IFM_ACTIVE;
359 bmcr = PHY_READ(sc, MII_BMCR);
361 if (bmcr & BMCR_LOOP)
362 mii->mii_media_active |= IFM_LOOP;
364 if (bmcr & BMCR_AUTOEN) {
366 * The media status bits are only valid if autonegotiation
367 * has completed (or it's disabled).
369 if ((bmsr & BMSR_ACOMP) == 0) {
370 /* Erg, still trying, I guess... */
371 mii->mii_media_active |= IFM_NONE;
374 anlpar = PHY_READ(sc, MII_ANLPAR);
375 gstat = PHY_READ(sc, MII_100T2SR);
376 if (gstat & GTSR_LP_1000TFDX)
377 mii->mii_media_active |= IFM_1000_T|IFM_FDX;
378 else if (gstat & GTSR_LP_1000THDX)
379 mii->mii_media_active |= IFM_1000_T|IFM_HDX;
380 else if (anlpar & ANLPAR_T4)
381 mii->mii_media_active |= IFM_100_T4;
382 else if (anlpar & ANLPAR_TX_FD)
383 mii->mii_media_active |= IFM_100_TX|IFM_FDX;
384 else if (anlpar & ANLPAR_TX)
385 mii->mii_media_active |= IFM_100_TX;
386 else if (anlpar & ANLPAR_10_FD)
387 mii->mii_media_active |= IFM_10_T|IFM_FDX;
388 else if (anlpar & ANLPAR_10)
389 mii->mii_media_active |= IFM_10_T|IFM_HDX;
391 mii->mii_media_active |= IFM_NONE;
395 switch(bmcr & (BMCR_SPEED1|BMCR_SPEED0)) {
397 mii->mii_media_active |= IFM_1000_T;
400 mii->mii_media_active |= IFM_100_TX;
403 mii->mii_media_active |= IFM_10_T;
410 mii->mii_media_active |= IFM_FDX;
412 mii->mii_media_active |= IFM_HDX;
419 nsgphy_mii_phy_auto(struct mii_softc *mii, int waitfor)
421 int bmsr, ktcr = 0, i;
423 if ((mii->mii_flags & MIIF_DOINGAUTO) == 0) {
425 PHY_WRITE(mii, MII_BMCR, 0);
427 ktcr = PHY_READ(mii, MII_100T2CR);
428 PHY_WRITE(mii, MII_100T2CR, ktcr |
429 (GTCR_ADV_1000TFDX|GTCR_ADV_1000THDX));
430 ktcr = PHY_READ(mii, MII_100T2CR);
432 PHY_WRITE(mii, MII_ANAR,
433 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
435 PHY_WRITE(mii, MII_BMCR,
436 BMCR_AUTOEN | BMCR_STARTNEG);
440 /* Wait 500ms for it to complete. */
441 for (i = 0; i < 500; i++) {
442 if ((bmsr = PHY_READ(mii, MII_BMSR)) & BMSR_ACOMP)
446 if ((bmsr & BMSR_ACOMP) == 0)
447 printf("%s: autonegotiation failed to complete\n",
448 mii->mii_dev.dv_xname);
453 * Don't need to worry about clearing MIIF_DOINGAUTO.
454 * If that's set, a timeout is pending, and it will
461 * Just let it finish asynchronously. This is for the benefit of
462 * the tick handler driving autonegotiation. Don't want 500ms
463 * delays all the time while the system is running!
465 if ((mii->mii_flags & MIIF_DOINGAUTO) == 0) {
466 mii->mii_flags |= MIIF_DOINGAUTO;
467 mii->mii_auto_ch = timeout(mii_phy_auto_timeout, mii, hz >> 1);
469 return (EJUSTRETURN);