3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY.
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/taskqueue.h>
49 #include <net/if_var.h>
50 #include <net/if_arp.h>
51 #include <net/if_media.h>
53 #include <dev/mii/mii.h>
54 #include <dev/mii/miivar.h>
57 #include <dev/mii/rgephyreg.h>
59 #include "miibus_if.h"
61 #include <machine/bus.h>
62 #include <dev/rl/if_rlreg.h>
64 static int rgephy_probe(device_t);
65 static int rgephy_attach(device_t);
67 static device_method_t rgephy_methods[] = {
68 /* device interface */
69 DEVMETHOD(device_probe, rgephy_probe),
70 DEVMETHOD(device_attach, rgephy_attach),
71 DEVMETHOD(device_detach, mii_phy_detach),
72 DEVMETHOD(device_shutdown, bus_generic_shutdown),
76 static devclass_t rgephy_devclass;
78 static driver_t rgephy_driver = {
81 sizeof(struct mii_softc)
84 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
86 static int rgephy_service(struct mii_softc *, struct mii_data *, int);
87 static void rgephy_status(struct mii_softc *);
88 static int rgephy_mii_phy_auto(struct mii_softc *, int);
89 static void rgephy_reset(struct mii_softc *);
90 static void rgephy_loop(struct mii_softc *);
91 static void rgephy_load_dspcode(struct mii_softc *);
93 static const struct mii_phydesc rgephys[] = {
94 MII_PHY_DESC(REALTEK, RTL8169S),
95 MII_PHY_DESC(REALTEK, RTL8251),
99 static const struct mii_phy_funcs rgephy_funcs = {
106 rgephy_probe(device_t dev)
109 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT));
113 rgephy_attach(device_t dev)
115 struct mii_softc *sc;
118 sc = device_get_softc(dev);
120 if (mii_dev_mac_match(dev, "re"))
121 flags |= MIIF_PHYPRIV0;
122 mii_phy_dev_attach(dev, flags, &rgephy_funcs, 0);
124 /* RTL8169S do not report auto-sense; add manually. */
125 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) &
127 if (sc->mii_capabilities & BMSR_EXTSTAT)
128 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
129 device_printf(dev, " ");
130 mii_phy_add_media(sc);
133 * Allow IFM_FLAG0 to be set indicating that auto-negotiation with
134 * manual configuration, which is used to work around issues with
135 * certain setups by default, should not be triggered as it may in
136 * turn cause harm in some edge cases.
138 sc->mii_pdata->mii_media.ifm_mask |= IFM_FLAG0;
142 MIIBUS_MEDIAINIT(sc->mii_dev);
147 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
149 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
150 int reg, speed, gig, anar;
157 PHY_RESET(sc); /* XXX hardware bug work-around */
159 anar = PHY_READ(sc, RGEPHY_MII_ANAR);
160 anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP |
161 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
162 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10);
164 switch (IFM_SUBTYPE(ife->ifm_media)) {
168 * If we're already in auto mode, just return.
170 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
173 (void)rgephy_mii_phy_auto(sc, ife->ifm_media);
176 speed = RGEPHY_S1000;
180 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX;
184 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10;
186 if ((ife->ifm_media & IFM_FLOW) != 0 &&
187 (mii->mii_media.ifm_media & IFM_FLAG0) != 0)
190 if ((ife->ifm_media & IFM_FDX) != 0) {
191 speed |= RGEPHY_BMCR_FDX;
192 gig = RGEPHY_1000CTL_AFD;
193 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10);
194 if ((ife->ifm_media & IFM_FLOW) != 0 ||
195 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
197 RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
199 gig = RGEPHY_1000CTL_AHD;
201 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD);
203 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
204 gig |= RGEPHY_1000CTL_MSE;
205 if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
206 gig |= RGEPHY_1000CTL_MSC;
209 anar &= ~RGEPHY_ANAR_ASP;
211 if ((mii->mii_media.ifm_media & IFM_FLAG0) == 0)
213 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG;
215 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
216 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
217 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
220 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
229 * Only used for autonegotiation.
231 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
237 * Check to see if we have link. If we do, we don't
238 * need to restart the autonegotiation process.
240 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 &&
241 sc->mii_mpd_rev >= 2) {
243 reg = PHY_READ(sc, RGEPHY_MII_SSR);
244 if (reg & RGEPHY_SSR_LINK) {
249 reg = PHY_READ(sc, RL_GMEDIASTAT);
250 if (reg & RL_GMEDIASTAT_LINK) {
256 /* Announce link loss right after it happens. */
257 if (sc->mii_ticks++ == 0)
260 /* Only retry autonegotiation every mii_anegticks seconds. */
261 if (sc->mii_ticks <= sc->mii_anegticks)
265 rgephy_mii_phy_auto(sc, ife->ifm_media);
269 /* Update the media status. */
273 * Callback if something changed. Note that we need to poke
274 * the DSP on the RealTek PHYs if the media changes.
277 if (sc->mii_media_active != mii->mii_media_active ||
278 sc->mii_media_status != mii->mii_media_status ||
279 cmd == MII_MEDIACHG) {
280 rgephy_load_dspcode(sc);
282 mii_phy_update(sc, cmd);
287 rgephy_status(struct mii_softc *sc)
289 struct mii_data *mii = sc->mii_pdata;
293 mii->mii_media_status = IFM_AVALID;
294 mii->mii_media_active = IFM_ETHER;
296 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev >= 2) {
297 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
298 if (ssr & RGEPHY_SSR_LINK)
299 mii->mii_media_status |= IFM_ACTIVE;
301 bmsr = PHY_READ(sc, RL_GMEDIASTAT);
302 if (bmsr & RL_GMEDIASTAT_LINK)
303 mii->mii_media_status |= IFM_ACTIVE;
306 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
308 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
309 if (bmcr & RGEPHY_BMCR_ISO) {
310 mii->mii_media_active |= IFM_NONE;
311 mii->mii_media_status = 0;
315 if (bmcr & RGEPHY_BMCR_LOOP)
316 mii->mii_media_active |= IFM_LOOP;
318 if (bmcr & RGEPHY_BMCR_AUTOEN) {
319 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
320 /* Erg, still trying, I guess... */
321 mii->mii_media_active |= IFM_NONE;
326 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev >= 2) {
327 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
328 switch (ssr & RGEPHY_SSR_SPD_MASK) {
329 case RGEPHY_SSR_S1000:
330 mii->mii_media_active |= IFM_1000_T;
332 case RGEPHY_SSR_S100:
333 mii->mii_media_active |= IFM_100_TX;
336 mii->mii_media_active |= IFM_10_T;
339 mii->mii_media_active |= IFM_NONE;
342 if (ssr & RGEPHY_SSR_FDX)
343 mii->mii_media_active |= IFM_FDX;
345 mii->mii_media_active |= IFM_HDX;
347 bmsr = PHY_READ(sc, RL_GMEDIASTAT);
348 if (bmsr & RL_GMEDIASTAT_1000MBPS)
349 mii->mii_media_active |= IFM_1000_T;
350 else if (bmsr & RL_GMEDIASTAT_100MBPS)
351 mii->mii_media_active |= IFM_100_TX;
352 else if (bmsr & RL_GMEDIASTAT_10MBPS)
353 mii->mii_media_active |= IFM_10_T;
355 mii->mii_media_active |= IFM_NONE;
356 if (bmsr & RL_GMEDIASTAT_FDX)
357 mii->mii_media_active |= IFM_FDX;
359 mii->mii_media_active |= IFM_HDX;
362 if ((mii->mii_media_active & IFM_FDX) != 0)
363 mii->mii_media_active |= mii_phy_flowstatus(sc);
365 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
366 (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0)
367 mii->mii_media_active |= IFM_ETH_MASTER;
371 rgephy_mii_phy_auto(struct mii_softc *sc, int media)
378 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
379 if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
380 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
381 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
383 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
384 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD);
386 PHY_WRITE(sc, RGEPHY_MII_BMCR,
387 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
390 return (EJUSTRETURN);
394 rgephy_loop(struct mii_softc *sc)
398 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 &&
399 sc->mii_mpd_rev < 2) {
400 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
404 for (i = 0; i < 15000; i++) {
405 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) {
407 device_printf(sc->mii_dev, "looped %d\n", i);
415 #define PHY_SETBIT(x, y, z) \
416 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
417 #define PHY_CLRBIT(x, y, z) \
418 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
421 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
422 * existing revisions of the 8169S/8110S chips need to be tuned in
423 * order to reliably negotiate a 1000Mbps link. This is only needed
424 * for rev 0 and rev 1 of the PHY. Later versions work without
428 rgephy_load_dspcode(struct mii_softc *sc)
432 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 ||
433 sc->mii_mpd_rev >= 2)
436 PHY_WRITE(sc, 31, 0x0001);
437 PHY_WRITE(sc, 21, 0x1000);
438 PHY_WRITE(sc, 24, 0x65C7);
439 PHY_CLRBIT(sc, 4, 0x0800);
440 val = PHY_READ(sc, 4) & 0xFFF;
441 PHY_WRITE(sc, 4, val);
442 PHY_WRITE(sc, 3, 0x00A1);
443 PHY_WRITE(sc, 2, 0x0008);
444 PHY_WRITE(sc, 1, 0x1020);
445 PHY_WRITE(sc, 0, 0x1000);
446 PHY_SETBIT(sc, 4, 0x0800);
447 PHY_CLRBIT(sc, 4, 0x0800);
448 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
449 PHY_WRITE(sc, 4, val);
450 PHY_WRITE(sc, 3, 0xFF41);
451 PHY_WRITE(sc, 2, 0xDE60);
452 PHY_WRITE(sc, 1, 0x0140);
453 PHY_WRITE(sc, 0, 0x0077);
454 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
455 PHY_WRITE(sc, 4, val);
456 PHY_WRITE(sc, 3, 0xDF01);
457 PHY_WRITE(sc, 2, 0xDF20);
458 PHY_WRITE(sc, 1, 0xFF95);
459 PHY_WRITE(sc, 0, 0xFA00);
460 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
461 PHY_WRITE(sc, 4, val);
462 PHY_WRITE(sc, 3, 0xFF41);
463 PHY_WRITE(sc, 2, 0xDE20);
464 PHY_WRITE(sc, 1, 0x0140);
465 PHY_WRITE(sc, 0, 0x00BB);
466 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
467 PHY_WRITE(sc, 4, val);
468 PHY_WRITE(sc, 3, 0xDF01);
469 PHY_WRITE(sc, 2, 0xDF20);
470 PHY_WRITE(sc, 1, 0xFF95);
471 PHY_WRITE(sc, 0, 0xBF00);
472 PHY_SETBIT(sc, 4, 0x0800);
473 PHY_CLRBIT(sc, 4, 0x0800);
474 PHY_WRITE(sc, 31, 0x0000);
480 rgephy_reset(struct mii_softc *sc)
484 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev == 3) {
486 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
487 if ((ssr & RGEPHY_SSR_ALDPS) != 0) {
488 ssr &= ~RGEPHY_SSR_ALDPS;
489 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr);
493 if (sc->mii_mpd_rev >= 2) {
494 pcr = PHY_READ(sc, RGEPHY_MII_PCR);
495 if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) {
496 pcr &= ~RGEPHY_PCR_MDI_MASK;
497 pcr |= RGEPHY_PCR_MDIX_AUTO;
498 PHY_WRITE(sc, RGEPHY_MII_PCR, pcr);
504 rgephy_load_dspcode(sc);