2 * Copyright (c) 1999 Michael Smith
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #define MLX_BLKSIZE 512 /* fixed feature */
32 * Selected command codes.
34 #define MLX_CMD_ENQUIRY_OLD 0x05
35 #define MLX_CMD_ENQUIRY 0x53
36 #define MLX_CMD_ENQUIRY2 0x1c
37 #define MLX_CMD_ENQSYSDRIVE 0x19
38 #define MLX_CMD_READSG 0xb6
39 #define MLX_CMD_WRITESG 0xb7
40 #define MLX_CMD_READSG_OLD 0x82
41 #define MLX_CMD_WRITESG_OLD 0x83
42 #define MLX_CMD_FLUSH 0x0a
43 #define MLX_CMD_LOGOP 0x72
44 #define MLX_CMD_REBUILDASYNC 0x16
45 #define MLX_CMD_CHECKASYNC 0x1e
46 #define MLX_CMD_REBUILDSTAT 0x0c
47 #define MLX_CMD_STOPCHANNEL 0x13
48 #define MLX_CMD_STARTCHANNEL 0x12
49 #define MLX_CMD_READ_CONFIG 0x4e
50 #define MLX_CMD_DIRECT_CDB 0x04
51 #define MLX_CMD_DEVICE_STATE 0x50
55 #define MLX_CFG_BASE0 0x10 /* first region */
56 #define MLX_CFG_BASE1 0x14 /* second region (type 3 only) */
61 #define MLX_STATUS_OK 0x0000
62 #define MLX_STATUS_RDWROFFLINE 0x0002 /* read/write claims drive is offline */
63 #define MLX_STATUS_WEDGED 0xdead /* controller not listening */
64 #define MLX_STATUS_LOST 0xbeef /* never came back */
65 #define MLX_STATUS_BUSY 0xffff /* command is in controller */
68 * Accessor defines for the V3 interface.
70 #define MLX_V3_MAILBOX 0x00
71 #define MLX_V3_STATUS_IDENT 0x0d
72 #define MLX_V3_STATUS 0x0e
73 #define MLX_V3_IDBR 0x40
74 #define MLX_V3_ODBR 0x41
75 #define MLX_V3_IER 0x43
76 #define MLX_V3_FWERROR 0x3f
77 #define MLX_V3_FWERROR_PARAM1 0x00
78 #define MLX_V3_FWERROR_PARAM2 0x01
80 #define MLX_V3_PUT_MAILBOX(sc, idx, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_MAILBOX + idx, val)
81 #define MLX_V3_GET_STATUS_IDENT(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_STATUS_IDENT)
82 #define MLX_V3_GET_STATUS(sc) bus_space_read_2 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_STATUS)
83 #define MLX_V3_GET_IDBR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_IDBR)
84 #define MLX_V3_PUT_IDBR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_IDBR, val)
85 #define MLX_V3_GET_ODBR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_ODBR)
86 #define MLX_V3_PUT_ODBR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_ODBR, val)
87 #define MLX_V3_PUT_IER(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_IER, val)
88 #define MLX_V3_GET_FWERROR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_FWERROR)
89 #define MLX_V3_PUT_FWERROR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_FWERROR, val)
90 #define MLX_V3_GET_FWERROR_PARAM1(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_FWERROR_PARAM1)
91 #define MLX_V3_GET_FWERROR_PARAM2(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_FWERROR_PARAM2)
93 #define MLX_V3_IDB_FULL (1<<0) /* mailbox is full */
94 #define MLX_V3_IDB_INIT_BUSY (1<<1) /* initialisation in progress */
96 #define MLX_V3_IDB_SACK (1<<1) /* acknowledge status read */
98 #define MLX_V3_ODB_SAVAIL (1<<0) /* status is available */
100 #define MLX_V3_FWERROR_PEND (1<<2) /* firmware error pending */
103 * Accessor defines for the V4 interface.
105 #define MLX_V4_MAILBOX 0x1000
106 #define MLX_V4_MAILBOX_LENGTH 16
107 #define MLX_V4_STATUS_IDENT 0x1018
108 #define MLX_V4_STATUS 0x101a
109 #define MLX_V4_IDBR 0x0020
110 #define MLX_V4_ODBR 0x002c
111 #define MLX_V4_IER 0x0034
112 #define MLX_V4_FWERROR 0x103f
113 #define MLX_V4_FWERROR_PARAM1 0x1000
114 #define MLX_V4_FWERROR_PARAM2 0x1001
116 /* use longword access? */
117 #define MLX_V4_PUT_MAILBOX(sc, idx, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V4_MAILBOX + idx, val)
118 #define MLX_V4_GET_STATUS_IDENT(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_STATUS_IDENT)
119 #define MLX_V4_GET_STATUS(sc) bus_space_read_2 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_STATUS)
120 #define MLX_V4_GET_IDBR(sc) bus_space_read_4 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_IDBR)
121 #define MLX_V4_PUT_IDBR(sc, val) bus_space_write_4(sc->mlx_btag, sc->mlx_bhandle, MLX_V4_IDBR, val)
122 #define MLX_V4_GET_ODBR(sc) bus_space_read_4 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_ODBR)
123 #define MLX_V4_PUT_ODBR(sc, val) bus_space_write_4(sc->mlx_btag, sc->mlx_bhandle, MLX_V4_ODBR, val)
124 #define MLX_V4_PUT_IER(sc, val) bus_space_write_4(sc->mlx_btag, sc->mlx_bhandle, MLX_V4_IER, val)
125 #define MLX_V4_GET_FWERROR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_FWERROR)
126 #define MLX_V4_PUT_FWERROR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V4_FWERROR, val)
127 #define MLX_V4_GET_FWERROR_PARAM1(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_FWERROR_PARAM1)
128 #define MLX_V4_GET_FWERROR_PARAM2(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_FWERROR_PARAM2)
130 #define MLX_V4_IDB_FULL (1<<0) /* mailbox is full */
131 #define MLX_V4_IDB_INIT_BUSY (1<<1) /* initialisation in progress */
133 #define MLX_V4_IDB_HWMBOX_CMD (1<<0) /* posted hardware mailbox command */
134 #define MLX_V4_IDB_SACK (1<<1) /* acknowledge status read */
135 #define MLX_V4_IDB_MEMMBOX_CMD (1<<4) /* posted memory mailbox command */
137 #define MLX_V4_ODB_HWSAVAIL (1<<0) /* status is available for hardware mailbox */
138 #define MLX_V4_ODB_MEMSAVAIL (1<<1) /* status is available for memory mailbox */
140 #define MLX_V4_ODB_HWMBOX_ACK (1<<0) /* ack status read from hardware mailbox */
141 #define MLX_V4_ODB_MEMMBOX_ACK (1<<1) /* ack status read from memory mailbox */
143 #define MLX_V4_IER_MASK 0xfb /* message unit interrupt mask */
144 #define MLX_V4_IER_DISINT (1<<2) /* interrupt disable bit */
146 #define MLX_V4_FWERROR_PEND (1<<2) /* firmware error pending */
149 * Accessor defines for the V5 interface
151 #define MLX_V5_MAILBOX 0x50
152 #define MLX_V5_MAILBOX_LENGTH 16
153 #define MLX_V5_STATUS_IDENT 0x5d
154 #define MLX_V5_STATUS 0x5e
155 #define MLX_V5_IDBR 0x60
156 #define MLX_V5_ODBR 0x61
157 #define MLX_V5_IER 0x34
158 #define MLX_V5_FWERROR 0x63
159 #define MLX_V5_FWERROR_PARAM1 0x50
160 #define MLX_V5_FWERROR_PARAM2 0x51
162 #define MLX_V5_PUT_MAILBOX(sc, idx, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V5_MAILBOX + idx, val)
163 #define MLX_V5_GET_STATUS_IDENT(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_STATUS_IDENT)
164 #define MLX_V5_GET_STATUS(sc) bus_space_read_2 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_STATUS)
165 #define MLX_V5_GET_IDBR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_IDBR)
166 #define MLX_V5_PUT_IDBR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V5_IDBR, val)
167 #define MLX_V5_GET_ODBR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_ODBR)
168 #define MLX_V5_PUT_ODBR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V5_ODBR, val)
169 #define MLX_V5_PUT_IER(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V5_IER, val)
170 #define MLX_V5_GET_FWERROR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_FWERROR)
171 #define MLX_V5_PUT_FWERROR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V5_FWERROR, val)
172 #define MLX_V5_GET_FWERROR_PARAM1(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_FWERROR_PARAM1)
173 #define MLX_V5_GET_FWERROR_PARAM2(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_FWERROR_PARAM2)
175 #define MLX_V5_IDB_EMPTY (1<<0) /* mailbox is empty */
176 #define MLX_V5_IDB_INIT_DONE (1<<1) /* initialisation has completed */
178 #define MLX_V5_IDB_HWMBOX_CMD (1<<0) /* posted hardware mailbox command */
179 #define MLX_V5_IDB_SACK (1<<1) /* acknowledge status read */
180 #define MLX_V5_IDB_RESET (1<<3) /* reset request */
181 #define MLX_V5_IDB_MEMMBOX_CMD (1<<4) /* posted memory mailbox command */
183 #define MLX_V5_ODB_HWSAVAIL (1<<0) /* status is available for hardware mailbox */
184 #define MLX_V5_ODB_MEMSAVAIL (1<<1) /* status is available for memory mailbox */
186 #define MLX_V5_ODB_HWMBOX_ACK (1<<0) /* ack status read from hardware mailbox */
187 #define MLX_V5_ODB_MEMMBOX_ACK (1<<1) /* ack status read from memory mailbox */
189 #define MLX_V5_IER_DISINT (1<<2) /* interrupt disable bit */
191 #define MLX_V5_FWERROR_PEND (1<<2) /* firmware error pending */
196 * Scatter-gather list format, type 1, kind 00.
205 * Command result buffers, as placed in system memory by the controller.
208 struct mlx_enquiry_old /* MLX_CMD_ENQUIRY_OLD */
210 u_int8_t me_num_sys_drvs;
212 u_int32_t me_drvsize[8];
213 u_int16_t me_flash_age;
214 u_int8_t me_status_flags;
215 u_int8_t me_free_state_change_count;
218 u_int8_t me_rebuild_flag;
219 u_int8_t me_max_commands;
220 u_int8_t me_offline_sd_count;
222 u_int8_t me_critical_sd_count;
224 u_int8_t me_dead_count;
226 u_int8_t me_rebuild_count;
227 u_int8_t me_misc_flags;
232 } __packed me_dead[20];
235 struct mlx_enquiry /* MLX_CMD_ENQUIRY */
237 u_int8_t me_num_sys_drvs;
239 u_int32_t me_drvsize[32];
240 u_int16_t me_flash_age;
241 u_int8_t me_status_flags;
242 #define MLX_ENQ_SFLAG_DEFWRERR (1<<0) /* deferred write error indicator */
243 #define MLX_ENQ_SFLAG_BATTLOW (1<<1) /* battery low */
247 u_int8_t me_rebuild_flag;
248 u_int8_t me_max_commands;
249 u_int8_t me_offline_sd_count;
251 u_int16_t me_event_log_seq_num;
252 u_int8_t me_critical_sd_count;
254 u_int8_t me_dead_count;
256 u_int8_t me_rebuild_count;
257 u_int8_t me_misc_flags;
258 #define MLX_ENQ_MISC_BBU (1<<3) /* battery backup present */
263 } __packed me_dead[20];
266 struct mlx_enquiry2 /* MLX_CMD_ENQUIRY2 */
268 u_int32_t me_hardware_id;
269 u_int32_t me_firmware_id;
271 u_int8_t me_configured_channels;
272 u_int8_t me_actual_channels;
273 u_int8_t me_max_targets;
274 u_int8_t me_max_tags;
275 u_int8_t me_max_sys_drives;
276 u_int8_t me_max_arms;
277 u_int8_t me_max_spans;
280 u_int32_t me_mem_size;
281 u_int32_t me_cache_size;
282 u_int32_t me_flash_size;
283 u_int32_t me_nvram_size;
284 u_int16_t me_mem_type;
285 u_int16_t me_clock_speed;
286 u_int16_t me_mem_speed;
287 u_int16_t me_hardware_speed;
289 u_int16_t me_max_commands;
292 u_int16_t me_max_iod;
293 u_int16_t me_max_comb;
296 u_int8_t me_scsi_timeout;
298 u_int16_t me_min_freelines;
300 u_int8_t me_rate_const;
302 u_int16_t me_physblk;
305 u_int16_t me_blocking_factor;
306 u_int16_t me_cacheline;
307 u_int8_t me_scsi_cap;
309 u_int16_t me_firmware_build;
310 u_int8_t me_fault_mgmt_type;
312 u_int32_t me_firmware_features;
316 struct mlx_enq_sys_drive /* MLX_CMD_ENQSYSDRIVE returns an array of 32 of these */
320 u_int8_t sd_raidlevel;
324 struct mlx_eventlog_entry /* MLX_CMD_LOGOP/MLX_LOGOP_GET */
333 u_char el_errorcode:7;
336 u_char el_sensekey:4;
340 u_char el_filemark:1;
341 u_int8_t el_information[4];
342 u_int8_t el_addsense;
349 #define MLX_LOGOP_GET 0x00 /* operation codes for MLX_CMD_LOGOP */
350 #define MLX_LOGMSG_SENSE 0x00 /* log message contents codes */
352 struct mlx_rebuild_stat /* MLX_CMD_REBUILDSTAT */
356 u_int32_t rb_remaining;
362 #define MLX_CF2_ACTV_NEG (1<<1)
363 #define MLX_CF2_NORSTRTRY (1<<7)
364 #define MLX_CF2_STRGWRK (1<<8)
365 #define MLX_CF2_HPSUPP (1<<9)
366 #define MLX_CF2_NODISCN (1<<10)
367 #define MLX_CF2_ARM (1<<13)
368 #define MLX_CF2_OFM (1<<15)
369 #define MLX_CF2_AEMI (MLX_CF2_ARM | MLX_CF2_OFM)
371 u_int8_t cf_oem_model;
372 u_int8_t cf_physical_sector;
373 u_int8_t cf_logical_sector;
374 u_int8_t cf_blockfactor;
376 #define MLX_CF2_READAH (1<<0)
377 #define MLX_CF2_BIOSDLY (1<<1)
378 #define MLX_CF2_REASS1S (1<<4)
379 #define MLX_CF2_FUAENABL (1<<6)
380 #define MLX_CF2_R5ALLS (1<<7)
383 u_int8_t cf_blocks_per_cache_line;
384 u_int8_t cf_blocks_per_stripe;
385 u_int8_t cf_scsi_param_0;
386 u_int8_t cf_scsi_param_1;
387 u_int8_t cf_scsi_param_2;
388 u_int8_t cf_scsi_param_3;
389 u_int8_t cf_scsi_param_4;
390 u_int8_t cf_scsi_param_5;
391 u_int8_t cf_scsi_initiator_id;
393 u_int8_t cf_startup_mode;
394 u_int8_t cf_simultaneous_spinup_devices;
395 u_int8_t cf_delay_between_spinups;
397 u_int16_t cf_checksum;
400 struct mlx_sys_drv_span
402 u_int32_t sp_start_lba;
410 u_int8_t sd_ext_status;
413 u_int8_t sd_raidlevel;
414 #define MLX_SYS_DRV_WRITEBACK (1<<7)
415 #define MLX_SYS_DRV_RAID0 0
416 #define MLX_SYS_DRV_RAID1 1
417 #define MLX_SYS_DRV_RAID3 3
418 #define MLX_SYS_DRV_RAID5 5
419 #define MLX_SYS_DRV_RAID6 6
420 #define MLX_SYS_DRV_JBOD 7
421 u_int8_t sd_valid_arms;
422 u_int8_t sd_valid_spans;
423 u_int8_t sd_init_state;
424 #define MLX_SYS_DRV_INITTED 0x81;
425 struct mlx_sys_drv_span sd_span[4];
431 #define MLX_PHYS_DRV_PRESENT (1<<0)
433 #define MLX_PHYS_DRV_OTHER 0x00
434 #define MLX_PHYS_DRV_DISK 0x01
435 #define MLX_PHYS_DRV_SEQUENTIAL 0x02
436 #define MLX_PHYS_DRV_CDROM 0x03
437 #define MLX_PHYS_DRV_FAST20 (1<<3)
438 #define MLX_PHYS_DRV_SYNC (1<<4)
439 #define MLX_PHYS_DRV_FAST (1<<5)
440 #define MLX_PHYS_DRV_WIDE (1<<6)
441 #define MLX_PHYS_DRV_TAG (1<<7)
443 #define MLX_PHYS_DRV_DEAD 0x00
444 #define MLX_PHYS_DRV_WRONLY 0x02
445 #define MLX_PHYS_DRV_ONLINE 0x03
446 #define MLX_PHYS_DRV_STANDBY 0x10
450 u_int32_t pd_config_size;
455 u_int8_t cc_num_sys_drives;
457 struct mlx_sys_drv cc_sys_drives[32];
458 struct mlx_phys_drv cc_phys_drives[5 * 16];
463 u_int8_t dcdb_target:4;
464 u_int8_t dcdb_channel:4;
466 #define MLX_DCDB_NO_DATA 0x00
467 #define MLX_DCDB_DATA_IN 0x01
468 #define MLX_DCDB_DATA_OUT 0x02
469 #define MLX_DCDB_EARLY_STATUS (1<<2)
470 #define MLX_DCDB_TIMEOUT_10S 0x10
471 #define MLX_DCDB_TIMEOUT_60S 0x20
472 #define MLX_DCDB_TIMEOUT_20M 0x30
473 #define MLX_DCDB_TIMEOUT_24H 0x40
474 #define MLX_DCDB_NO_AUTO_SENSE (1<<6)
475 #define MLX_DCDB_DISCONNECT (1<<7)
476 u_int16_t dcdb_datasize;
477 u_int32_t dcdb_physaddr;
478 u_int8_t dcdb_cdb_length:4;
479 u_int8_t dcdb_datasize_high:4;
480 u_int8_t dcdb_sense_length;
481 u_int8_t dcdb_cdb[12];
482 u_int8_t dcdb_sense[64];
483 u_int8_t dcdb_status;
487 struct mlx_bbtable_entry
489 u_int32_t bbt_block_number;
492 u_int8_t bbt_entry_type;
493 u_int8_t bbt_system_drive:5;
499 * Inlines to build various command structures
502 mlx_make_type1(struct mlx_command *mc,
510 mc->mc_mailbox[0x0] = code;
511 mc->mc_mailbox[0x2] = f1 & 0xff;
512 mc->mc_mailbox[0x3] = (((f2 >> 24) & 0x3) << 6) | ((f1 >> 8) & 0x3f);
513 mc->mc_mailbox[0x4] = f2 & 0xff;
514 mc->mc_mailbox[0x5] = (f2 >> 8) & 0xff;
515 mc->mc_mailbox[0x6] = (f2 >> 16) & 0xff;
516 mc->mc_mailbox[0x7] = f3;
517 mc->mc_mailbox[0x8] = f4 & 0xff;
518 mc->mc_mailbox[0x9] = (f4 >> 8) & 0xff;
519 mc->mc_mailbox[0xa] = (f4 >> 16) & 0xff;
520 mc->mc_mailbox[0xb] = (f4 >> 24) & 0xff;
521 mc->mc_mailbox[0xc] = f5;
525 mlx_make_type2(struct mlx_command *mc,
536 mc->mc_mailbox[0x0] = code;
537 mc->mc_mailbox[0x2] = f1;
538 mc->mc_mailbox[0x3] = f2;
539 mc->mc_mailbox[0x4] = f3;
540 mc->mc_mailbox[0x5] = f4;
541 mc->mc_mailbox[0x6] = f5;
542 mc->mc_mailbox[0x7] = f6;
543 mc->mc_mailbox[0x8] = f7 & 0xff;
544 mc->mc_mailbox[0x9] = (f7 >> 8) & 0xff;
545 mc->mc_mailbox[0xa] = (f7 >> 16) & 0xff;
546 mc->mc_mailbox[0xb] = (f7 >> 24) & 0xff;
547 mc->mc_mailbox[0xc] = f8;
551 mlx_make_type3(struct mlx_command *mc,
561 mc->mc_mailbox[0x0] = code;
562 mc->mc_mailbox[0x2] = f1;
563 mc->mc_mailbox[0x3] = f2;
564 mc->mc_mailbox[0x4] = f3 & 0xff;
565 mc->mc_mailbox[0x5] = (f3 >> 8) & 0xff;
566 mc->mc_mailbox[0x6] = f4;
567 mc->mc_mailbox[0x7] = f5;
568 mc->mc_mailbox[0x8] = f6 & 0xff;
569 mc->mc_mailbox[0x9] = (f6 >> 8) & 0xff;
570 mc->mc_mailbox[0xa] = (f6 >> 16) & 0xff;
571 mc->mc_mailbox[0xb] = (f6 >> 24) & 0xff;
572 mc->mc_mailbox[0xc] = f7;
576 mlx_make_type4(struct mlx_command *mc,
583 mc->mc_mailbox[0x0] = code;
584 mc->mc_mailbox[0x2] = f1 & 0xff;
585 mc->mc_mailbox[0x3] = (f1 >> 8) & 0xff;
586 mc->mc_mailbox[0x4] = f2 & 0xff;
587 mc->mc_mailbox[0x5] = (f2 >> 8) & 0xff;
588 mc->mc_mailbox[0x6] = (f2 >> 16) & 0xff;
589 mc->mc_mailbox[0x7] = (f2 >> 24) & 0xff;
590 mc->mc_mailbox[0x8] = f3 & 0xff;
591 mc->mc_mailbox[0x9] = (f3 >> 8) & 0xff;
592 mc->mc_mailbox[0xa] = (f3 >> 16) & 0xff;
593 mc->mc_mailbox[0xb] = (f3 >> 24) & 0xff;
594 mc->mc_mailbox[0xc] = f4;
598 mlx_make_type5(struct mlx_command *mc,
606 mc->mc_mailbox[0x0] = code;
607 mc->mc_mailbox[0x2] = f1;
608 mc->mc_mailbox[0x3] = f2;
609 mc->mc_mailbox[0x4] = f3 & 0xff;
610 mc->mc_mailbox[0x5] = (f3 >> 8) & 0xff;
611 mc->mc_mailbox[0x6] = (f3 >> 16) & 0xff;
612 mc->mc_mailbox[0x7] = (f3 >> 24) & 0xff;
613 mc->mc_mailbox[0x8] = f4 & 0xff;
614 mc->mc_mailbox[0x9] = (f4 >> 8) & 0xff;
615 mc->mc_mailbox[0xa] = (f4 >> 16) & 0xff;
616 mc->mc_mailbox[0xb] = (f4 >> 24) & 0xff;
617 mc->mc_mailbox[0xc] = f5;