2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008, 2014 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
46 #include <linux/device.h>
47 #include <dev/mlx4/device.h>
48 #include <dev/mlx4/driver.h>
49 #include <dev/mlx4/doorbell.h>
50 #include <dev/mlx4/cmd.h>
52 #define DRV_NAME "mlx4_core"
53 #define PFX DRV_NAME ": "
54 #define DRV_VERSION "2.1.6"
56 #define DRV_STACK_NAME "Linux-MLNX_OFED"
57 #define DRV_STACK_VERSION "2.1"
58 #define DRV_NAME_FOR_FW DRV_STACK_NAME","DRV_STACK_VERSION
60 #define MLX4_FS_UDP_UC_EN (1 << 1)
61 #define MLX4_FS_TCP_UC_EN (1 << 2)
62 #define MLX4_FS_NUM_OF_L2_ADDR 8
63 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
64 #define MLX4_FS_NUM_MCG (1 << 17)
66 struct mlx4_set_port_prio2tc_context {
70 struct mlx4_port_scheduler_tc_cfg_be {
73 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
77 struct mlx4_set_port_scheduler_context {
78 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
82 MLX4_HCR_BASE = 0x80680,
83 MLX4_HCR_SIZE = 0x0001c,
84 MLX4_CLR_INT_SIZE = 0x00008,
85 MLX4_SLAVE_COMM_BASE = 0x0,
86 MLX4_COMM_PAGESIZE = 0x1000,
87 MLX4_CLOCK_SIZE = 0x00008
91 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
92 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
93 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
94 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE)/16 - 2),
98 MLX4_NUM_PDS = 1 << 15
102 MLX4_CMPT_TYPE_QP = 0,
103 MLX4_CMPT_TYPE_SRQ = 1,
104 MLX4_CMPT_TYPE_CQ = 2,
105 MLX4_CMPT_TYPE_EQ = 3,
110 MLX4_CMPT_SHIFT = 24,
111 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
114 enum mlx4_mpt_state {
115 MLX4_MPT_DISABLED = 0,
120 #define MLX4_COMM_TIME 10000
126 MLX4_COMM_CMD_VHCR_EN,
127 MLX4_COMM_CMD_VHCR_POST,
128 MLX4_COMM_CMD_FLR = 254
131 /*The flag indicates that the slave should delay the RESET cmd*/
132 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
133 /*indicates how many retries will be done if we are in the middle of FLR*/
134 #define NUM_OF_RESET_RETRIES 10
135 #define SLEEP_TIME_IN_RESET (2 * 1000)
149 MLX4_NUM_OF_RESOURCE_TYPE
152 enum mlx4_alloc_mode {
154 RES_OP_RESERVE_AND_MAP,
158 enum mlx4_res_tracker_free_type {
160 RES_TR_FREE_SLAVES_ONLY,
161 RES_TR_FREE_STRUCTS_ONLY,
165 *Virtual HCR structures.
166 * mlx4_vhcr is the sw representation, in machine endianness
168 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
169 * to FW to go through communication channel.
170 * It is big endian, and has the same structure as the physical HCR
171 * used by command interface
184 struct mlx4_vhcr_cmd {
196 struct mlx4_cmd_info {
201 bool encode_slave_id;
203 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
204 struct mlx4_cmd_mailbox *inbox);
205 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
206 struct mlx4_cmd_mailbox *inbox,
207 struct mlx4_cmd_mailbox *outbox,
208 struct mlx4_cmd_info *cmd);
212 MLX4_DEBUG_MASK_CMD_TIME = 0x100,
215 #ifdef CONFIG_MLX4_DEBUG
216 extern int mlx4_debug_level;
217 #else /* CONFIG_MLX4_DEBUG */
218 #define mlx4_debug_level (0)
219 #endif /* CONFIG_MLX4_DEBUG */
221 #define mlx4_dbg(mdev, format, arg...) \
223 if (mlx4_debug_level) \
224 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
227 #define mlx4_err(mdev, format, arg...) \
228 dev_err(&mdev->pdev->dev, format, ##arg)
229 #define mlx4_info(mdev, format, arg...) \
230 dev_info(&mdev->pdev->dev, format, ##arg)
231 #define mlx4_warn(mdev, format, arg...) \
232 dev_warn(&mdev->pdev->dev, format, ##arg)
234 extern int mlx4_log_num_mgm_entry_size;
235 extern int log_mtts_per_seg;
236 extern int mlx4_blck_lb;
237 extern int mlx4_set_4k_mtu;
239 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
240 #define ALL_SLAVES 0xff
250 unsigned long *table;
254 unsigned long **bits;
255 unsigned int *num_free;
262 struct mlx4_icm_table {
270 struct mlx4_icm **icm;
273 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
274 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
275 #define MLX4_MPT_FLAG_MIO (1 << 17)
276 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
277 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
278 #define MLX4_MPT_FLAG_REGION (1 << 8)
280 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
281 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
282 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
284 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
286 #define MLX4_MPT_STATUS_SW 0xF0
287 #define MLX4_MPT_STATUS_HW 0x00
290 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
292 struct mlx4_mpt_entry {
306 __be32 first_byte_offset;
310 * Must be packed because start is 64 bits but only aligned to 32 bits.
312 struct mlx4_eq_context {
326 __be32 mtt_base_addr_l;
328 __be32 consumer_index;
329 __be32 producer_index;
333 struct mlx4_cq_context {
337 __be32 logsize_usrpage;
345 __be32 mtt_base_addr_l;
346 __be32 last_notified_index;
347 __be32 solicit_producer_index;
348 __be32 consumer_index;
349 __be32 producer_index;
354 struct mlx4_srq_context {
355 __be32 state_logsize_srqn;
359 __be32 pg_offset_cqn;
364 __be32 mtt_base_addr_l;
366 __be16 limit_watermark;
375 struct mlx4_dev *dev;
376 void __iomem *doorbell;
382 struct mlx4_buf_list *page_list;
386 struct mlx4_slave_eqe {
392 struct mlx4_slave_event_eq_info {
397 struct mlx4_profile {
404 unsigned num_mtt_segs;
412 struct mlx4_icm *fw_icm;
413 struct mlx4_icm *aux_icm;
428 MLX4_MCAST_CONFIG = 0,
429 MLX4_MCAST_DISABLE = 1,
430 MLX4_MCAST_ENABLE = 2,
433 #define VLAN_FLTR_SIZE 128
435 struct mlx4_vlan_fltr {
436 __be32 entry[VLAN_FLTR_SIZE];
439 struct mlx4_mcast_entry {
440 struct list_head list;
444 struct mlx4_promisc_qp {
445 struct list_head list;
449 struct mlx4_steer_index {
450 struct list_head list;
452 struct list_head duplicates;
455 #define MLX4_EVENT_TYPES_NUM 64
457 struct mlx4_slave_state {
465 u16 mtu[MLX4_MAX_PORTS + 1];
466 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
467 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
468 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
469 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
470 /* event type to eq number lookup */
471 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
475 /*initialized via the kzalloc*/
476 u8 is_slave_going_down;
478 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
481 #define MLX4_VGT 4095
485 struct mlx4_vport_state {
494 struct mlx4_vf_admin_state {
495 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
498 struct mlx4_vport_oper_state {
499 struct mlx4_vport_state state;
503 struct mlx4_vf_oper_state {
504 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
509 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
512 struct resource_allocator {
513 spinlock_t alloc_lock;
516 int res_port_rsvd[MLX4_MAX_PORTS];
520 int res_port_free[MLX4_MAX_PORTS];
527 struct mlx4_resource_tracker {
529 /* tree for each resources */
530 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
531 /* num_of_slave's lists, one per slave */
532 struct slave_list *slave_list;
533 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
536 #define SLAVE_EVENT_EQ_SIZE 128
537 struct mlx4_slave_event_eq {
541 spinlock_t event_lock;
542 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
545 struct mlx4_master_qp0_state {
546 int proxy_qp0_active;
551 struct mlx4_mfunc_master_ctx {
552 struct mlx4_slave_state *slave_state;
553 struct mlx4_vf_admin_state *vf_admin;
554 struct mlx4_vf_oper_state *vf_oper;
555 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
556 int init_port_ref[MLX4_MAX_PORTS + 1];
557 u16 max_mtu[MLX4_MAX_PORTS + 1];
558 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
559 struct mlx4_resource_tracker res_tracker;
560 struct workqueue_struct *comm_wq;
561 struct work_struct comm_work;
562 struct work_struct arm_comm_work;
563 struct work_struct slave_event_work;
564 struct work_struct slave_flr_event_work;
565 spinlock_t slave_state_lock;
566 __be32 comm_arm_bit_vector[4];
567 struct mlx4_eqe cmd_eqe;
568 struct mlx4_slave_event_eq slave_eq;
569 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
573 struct mlx4_comm __iomem *comm;
574 struct mlx4_vhcr_cmd *vhcr;
577 struct mlx4_mfunc_master_ctx master;
580 #define MGM_QPN_MASK 0x00FFFFFF
581 #define MGM_BLCK_LB_BIT 30
584 __be32 next_gid_index;
585 __be32 members_count;
588 __be32 qp[MLX4_MAX_QP_PER_MGM];
592 struct pci_pool *pool;
594 struct mutex hcr_mutex;
595 struct mutex slave_cmd_mutex;
596 struct semaphore poll_sem;
597 struct semaphore event_sem;
599 spinlock_t context_lock;
601 struct mlx4_cmd_context *context;
609 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
610 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
612 struct mlx4_vf_immed_vlan_work {
613 struct work_struct work;
614 struct mlx4_priv *priv;
626 struct mlx4_uar_table {
627 struct mlx4_bitmap bitmap;
630 struct mlx4_mr_table {
631 struct mlx4_bitmap mpt_bitmap;
632 struct mlx4_buddy mtt_buddy;
635 struct mlx4_icm_table mtt_table;
636 struct mlx4_icm_table dmpt_table;
639 struct mlx4_cq_table {
640 struct mlx4_bitmap bitmap;
642 rwlock_t cq_table_lock;
643 struct radix_tree_root tree;
644 struct mlx4_icm_table table;
645 struct mlx4_icm_table cmpt_table;
648 struct mlx4_eq_table {
649 struct mlx4_bitmap bitmap;
651 void __iomem *clr_int;
652 void __iomem **uar_map;
655 struct mlx4_icm_table table;
656 struct mlx4_icm_table cmpt_table;
661 struct mlx4_srq_table {
662 struct mlx4_bitmap bitmap;
664 struct radix_tree_root tree;
665 struct mlx4_icm_table table;
666 struct mlx4_icm_table cmpt_table;
669 struct mlx4_qp_table {
670 struct mlx4_bitmap bitmap;
674 struct mlx4_icm_table qp_table;
675 struct mlx4_icm_table auxc_table;
676 struct mlx4_icm_table altc_table;
677 struct mlx4_icm_table rdmarc_table;
678 struct mlx4_icm_table cmpt_table;
681 struct mlx4_mcg_table {
683 struct mlx4_bitmap bitmap;
684 struct mlx4_icm_table table;
687 struct mlx4_catas_err {
689 struct timer_list timer;
690 struct list_head list;
693 #define MLX4_MAX_MAC_NUM 128
694 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
696 struct mlx4_mac_table {
697 __be64 entries[MLX4_MAX_MAC_NUM];
698 int refs[MLX4_MAX_MAC_NUM];
704 #define MLX4_MAX_VLAN_NUM 128
705 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
707 struct mlx4_vlan_table {
708 __be32 entries[MLX4_MAX_VLAN_NUM];
709 int refs[MLX4_MAX_VLAN_NUM];
715 #define SET_PORT_GEN_ALL_VALID 0x7
716 #define SET_PORT_PROMISC_SHIFT 31
717 #define SET_PORT_MC_PROMISC_SHIFT 30
720 MCAST_DIRECT_ONLY = 0,
726 struct mlx4_set_port_general_context {
739 struct mlx4_set_port_rqp_calc_context {
757 struct mlx4_hca_info {
758 struct mlx4_dev *dev;
759 struct device_attribute firmware_attr;
760 struct device_attribute hca_attr;
761 struct device_attribute board_attr;
764 struct mlx4_port_info {
765 struct mlx4_dev *dev;
768 struct device_attribute port_attr;
769 enum mlx4_port_type tmp_type;
770 char dev_mtu_name[16];
771 struct device_attribute port_mtu_attr;
772 struct mlx4_mac_table mac_table;
773 struct mlx4_vlan_table vlan_table;
778 struct mlx4_dev *dev;
779 u8 do_sense_port[MLX4_MAX_PORTS + 1];
780 u8 sense_allowed[MLX4_MAX_PORTS + 1];
781 struct delayed_work sense_poll;
784 struct mlx4_msix_ctl {
786 struct mutex pool_lock;
790 struct list_head promisc_qps[MLX4_NUM_STEERS];
791 struct list_head steer_entries[MLX4_NUM_STEERS];
795 MLX4_PCI_DEV_IS_VF = 1 << 0,
796 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
799 struct mlx4_roce_gid_entry {
803 struct counter_index {
804 struct list_head list;
808 struct mlx4_counters {
809 struct mlx4_bitmap bitmap;
810 struct list_head global_port_list[MLX4_MAX_PORTS];
811 struct list_head vf_list[MLX4_MAX_NUM_VF][MLX4_MAX_PORTS];
823 struct list_head dev_list;
824 struct list_head ctx_list;
829 struct list_head pgdir_list;
830 struct mutex pgdir_mutex;
834 struct mlx4_mfunc mfunc;
836 struct mlx4_bitmap pd_bitmap;
837 struct mlx4_bitmap xrcd_bitmap;
838 struct mlx4_uar_table uar_table;
839 struct mlx4_mr_table mr_table;
840 struct mlx4_cq_table cq_table;
841 struct mlx4_eq_table eq_table;
842 struct mlx4_srq_table srq_table;
843 struct mlx4_qp_table qp_table;
844 struct mlx4_mcg_table mcg_table;
845 struct mlx4_counters counters_table;
847 struct mlx4_catas_err catas_err;
849 void __iomem *clr_base;
851 struct mlx4_uar driver_uar;
853 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
854 struct mlx4_hca_info hca_info;
855 struct mlx4_sense sense;
856 struct mutex port_mutex;
857 struct mlx4_msix_ctl msix_ctl;
858 struct mlx4_steer *steer;
859 struct list_head bf_list;
860 struct mutex bf_mutex;
861 struct io_mapping *bf_mapping;
862 void __iomem *clock_mapping;
865 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
866 __be64 slave_node_guids[MLX4_MFUNC_MAX];
867 struct mlx4_roce_gid_entry roce_gids[MLX4_MAX_PORTS][128];
868 atomic_t opreq_count;
869 struct work_struct opreq_task;
872 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
874 return container_of(dev, struct mlx4_priv, dev);
877 #define MLX4_SENSE_RANGE (HZ * 3)
879 extern struct workqueue_struct *mlx4_wq;
881 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
882 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
883 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt,
884 int align, u32 skip_mask);
885 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
887 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
888 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
889 u32 reserved_bot, u32 resetrved_top);
890 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
892 int mlx4_reset(struct mlx4_dev *dev);
894 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
895 void mlx4_free_eq_table(struct mlx4_dev *dev);
897 int mlx4_init_pd_table(struct mlx4_dev *dev);
898 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
899 int mlx4_init_uar_table(struct mlx4_dev *dev);
900 int mlx4_init_mr_table(struct mlx4_dev *dev);
901 int mlx4_init_eq_table(struct mlx4_dev *dev);
902 int mlx4_init_cq_table(struct mlx4_dev *dev);
903 int mlx4_init_qp_table(struct mlx4_dev *dev);
904 int mlx4_init_srq_table(struct mlx4_dev *dev);
905 int mlx4_init_mcg_table(struct mlx4_dev *dev);
907 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
908 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
909 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
910 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
911 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
912 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
913 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
914 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
915 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
916 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
917 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
918 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
919 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
920 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
921 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
922 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
923 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
924 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index);
925 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
926 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
927 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
929 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
930 struct mlx4_vhcr *vhcr,
931 struct mlx4_cmd_mailbox *inbox,
932 struct mlx4_cmd_mailbox *outbox,
933 struct mlx4_cmd_info *cmd);
934 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
935 struct mlx4_vhcr *vhcr,
936 struct mlx4_cmd_mailbox *inbox,
937 struct mlx4_cmd_mailbox *outbox,
938 struct mlx4_cmd_info *cmd);
939 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
940 struct mlx4_vhcr *vhcr,
941 struct mlx4_cmd_mailbox *inbox,
942 struct mlx4_cmd_mailbox *outbox,
943 struct mlx4_cmd_info *cmd);
944 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
945 struct mlx4_vhcr *vhcr,
946 struct mlx4_cmd_mailbox *inbox,
947 struct mlx4_cmd_mailbox *outbox,
948 struct mlx4_cmd_info *cmd);
949 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
950 struct mlx4_vhcr *vhcr,
951 struct mlx4_cmd_mailbox *inbox,
952 struct mlx4_cmd_mailbox *outbox,
953 struct mlx4_cmd_info *cmd);
954 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
955 struct mlx4_vhcr *vhcr,
956 struct mlx4_cmd_mailbox *inbox,
957 struct mlx4_cmd_mailbox *outbox,
958 struct mlx4_cmd_info *cmd);
959 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
960 struct mlx4_vhcr *vhcr,
961 struct mlx4_cmd_mailbox *inbox,
962 struct mlx4_cmd_mailbox *outbox,
963 struct mlx4_cmd_info *cmd);
964 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
965 int *base, u8 flags);
966 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
967 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
968 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
969 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
970 int start_index, int npages, u64 *page_list);
971 int __mlx4_counter_alloc(struct mlx4_dev *dev, int slave, int port, u32 *idx);
972 void __mlx4_counter_free(struct mlx4_dev *dev, int slave, int port, u32 idx);
974 int __mlx4_slave_counters_free(struct mlx4_dev *dev, int slave);
975 int __mlx4_clear_if_stat(struct mlx4_dev *dev,
977 u8 mlx4_get_default_counter_index(struct mlx4_dev *dev, int slave, int port);
979 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
980 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
982 void mlx4_start_catas_poll(struct mlx4_dev *dev);
983 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
984 void mlx4_catas_init(void);
985 int mlx4_restart_one(struct pci_dev *pdev);
986 int mlx4_register_device(struct mlx4_dev *dev);
987 void mlx4_unregister_device(struct mlx4_dev *dev);
988 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
989 unsigned long param);
992 struct mlx4_init_hca_param;
994 u64 mlx4_make_profile(struct mlx4_dev *dev,
995 struct mlx4_profile *request,
996 struct mlx4_dev_cap *dev_cap,
997 struct mlx4_init_hca_param *init_hca);
998 void mlx4_master_comm_channel(struct work_struct *work);
999 void mlx4_master_arm_comm_channel(struct work_struct *work);
1000 void mlx4_gen_slave_eqe(struct work_struct *work);
1001 void mlx4_master_handle_slave_flr(struct work_struct *work);
1003 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
1004 struct mlx4_vhcr *vhcr,
1005 struct mlx4_cmd_mailbox *inbox,
1006 struct mlx4_cmd_mailbox *outbox,
1007 struct mlx4_cmd_info *cmd);
1008 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
1009 struct mlx4_vhcr *vhcr,
1010 struct mlx4_cmd_mailbox *inbox,
1011 struct mlx4_cmd_mailbox *outbox,
1012 struct mlx4_cmd_info *cmd);
1013 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
1014 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1015 struct mlx4_cmd_mailbox *outbox,
1016 struct mlx4_cmd_info *cmd);
1017 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1018 struct mlx4_vhcr *vhcr,
1019 struct mlx4_cmd_mailbox *inbox,
1020 struct mlx4_cmd_mailbox *outbox,
1021 struct mlx4_cmd_info *cmd);
1022 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1023 struct mlx4_vhcr *vhcr,
1024 struct mlx4_cmd_mailbox *inbox,
1025 struct mlx4_cmd_mailbox *outbox,
1026 struct mlx4_cmd_info *cmd);
1027 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1028 struct mlx4_vhcr *vhcr,
1029 struct mlx4_cmd_mailbox *inbox,
1030 struct mlx4_cmd_mailbox *outbox,
1031 struct mlx4_cmd_info *cmd);
1032 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1033 struct mlx4_vhcr *vhcr,
1034 struct mlx4_cmd_mailbox *inbox,
1035 struct mlx4_cmd_mailbox *outbox,
1036 struct mlx4_cmd_info *cmd);
1037 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1038 struct mlx4_vhcr *vhcr,
1039 struct mlx4_cmd_mailbox *inbox,
1040 struct mlx4_cmd_mailbox *outbox,
1041 struct mlx4_cmd_info *cmd);
1042 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1043 struct mlx4_vhcr *vhcr,
1044 struct mlx4_cmd_mailbox *inbox,
1045 struct mlx4_cmd_mailbox *outbox,
1046 struct mlx4_cmd_info *cmd);
1047 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1048 struct mlx4_vhcr *vhcr,
1049 struct mlx4_cmd_mailbox *inbox,
1050 struct mlx4_cmd_mailbox *outbox,
1051 struct mlx4_cmd_info *cmd);
1052 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1053 struct mlx4_vhcr *vhcr,
1054 struct mlx4_cmd_mailbox *inbox,
1055 struct mlx4_cmd_mailbox *outbox,
1056 struct mlx4_cmd_info *cmd);
1057 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1058 struct mlx4_vhcr *vhcr,
1059 struct mlx4_cmd_mailbox *inbox,
1060 struct mlx4_cmd_mailbox *outbox,
1061 struct mlx4_cmd_info *cmd);
1062 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1063 struct mlx4_vhcr *vhcr,
1064 struct mlx4_cmd_mailbox *inbox,
1065 struct mlx4_cmd_mailbox *outbox,
1066 struct mlx4_cmd_info *cmd);
1067 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1068 struct mlx4_vhcr *vhcr,
1069 struct mlx4_cmd_mailbox *inbox,
1070 struct mlx4_cmd_mailbox *outbox,
1071 struct mlx4_cmd_info *cmd);
1072 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1073 struct mlx4_vhcr *vhcr,
1074 struct mlx4_cmd_mailbox *inbox,
1075 struct mlx4_cmd_mailbox *outbox,
1076 struct mlx4_cmd_info *cmd);
1077 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1078 struct mlx4_vhcr *vhcr,
1079 struct mlx4_cmd_mailbox *inbox,
1080 struct mlx4_cmd_mailbox *outbox,
1081 struct mlx4_cmd_info *cmd);
1082 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1083 struct mlx4_vhcr *vhcr,
1084 struct mlx4_cmd_mailbox *inbox,
1085 struct mlx4_cmd_mailbox *outbox,
1086 struct mlx4_cmd_info *cmd);
1087 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1088 struct mlx4_vhcr *vhcr,
1089 struct mlx4_cmd_mailbox *inbox,
1090 struct mlx4_cmd_mailbox *outbox,
1091 struct mlx4_cmd_info *cmd);
1092 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1093 struct mlx4_vhcr *vhcr,
1094 struct mlx4_cmd_mailbox *inbox,
1095 struct mlx4_cmd_mailbox *outbox,
1096 struct mlx4_cmd_info *cmd);
1097 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1098 struct mlx4_vhcr *vhcr,
1099 struct mlx4_cmd_mailbox *inbox,
1100 struct mlx4_cmd_mailbox *outbox,
1101 struct mlx4_cmd_info *cmd);
1102 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1103 struct mlx4_vhcr *vhcr,
1104 struct mlx4_cmd_mailbox *inbox,
1105 struct mlx4_cmd_mailbox *outbox,
1106 struct mlx4_cmd_info *cmd);
1107 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1108 struct mlx4_vhcr *vhcr,
1109 struct mlx4_cmd_mailbox *inbox,
1110 struct mlx4_cmd_mailbox *outbox,
1111 struct mlx4_cmd_info *cmd);
1112 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1113 struct mlx4_vhcr *vhcr,
1114 struct mlx4_cmd_mailbox *inbox,
1115 struct mlx4_cmd_mailbox *outbox,
1116 struct mlx4_cmd_info *cmd);
1117 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1118 struct mlx4_vhcr *vhcr,
1119 struct mlx4_cmd_mailbox *inbox,
1120 struct mlx4_cmd_mailbox *outbox,
1121 struct mlx4_cmd_info *cmd);
1122 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1123 struct mlx4_vhcr *vhcr,
1124 struct mlx4_cmd_mailbox *inbox,
1125 struct mlx4_cmd_mailbox *outbox,
1126 struct mlx4_cmd_info *cmd);
1127 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1128 struct mlx4_vhcr *vhcr,
1129 struct mlx4_cmd_mailbox *inbox,
1130 struct mlx4_cmd_mailbox *outbox,
1131 struct mlx4_cmd_info *cmd);
1132 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1133 struct mlx4_vhcr *vhcr,
1134 struct mlx4_cmd_mailbox *inbox,
1135 struct mlx4_cmd_mailbox *outbox,
1136 struct mlx4_cmd_info *cmd);
1138 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1140 int mlx4_cmd_init(struct mlx4_dev *dev);
1141 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1142 int mlx4_multi_func_init(struct mlx4_dev *dev);
1143 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1144 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1145 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1146 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1148 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1149 unsigned long timeout);
1151 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1152 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1154 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1156 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1158 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1160 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1161 enum mlx4_port_type *type);
1162 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1163 enum mlx4_port_type *stype,
1164 enum mlx4_port_type *defaults);
1165 void mlx4_start_sense(struct mlx4_dev *dev);
1166 void mlx4_stop_sense(struct mlx4_dev *dev);
1167 void mlx4_sense_init(struct mlx4_dev *dev);
1168 int mlx4_check_port_params(struct mlx4_dev *dev,
1169 enum mlx4_port_type *port_type);
1170 int mlx4_change_port_types(struct mlx4_dev *dev,
1171 enum mlx4_port_type *port_types);
1173 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1174 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1175 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1176 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1178 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1179 /* resource tracker functions*/
1180 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1181 enum mlx4_resource resource_type,
1182 u64 resource_id, int *slave);
1183 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1184 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1186 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1187 enum mlx4_res_tracker_free_type type);
1189 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1190 struct mlx4_vhcr *vhcr,
1191 struct mlx4_cmd_mailbox *inbox,
1192 struct mlx4_cmd_mailbox *outbox,
1193 struct mlx4_cmd_info *cmd);
1194 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1195 struct mlx4_vhcr *vhcr,
1196 struct mlx4_cmd_mailbox *inbox,
1197 struct mlx4_cmd_mailbox *outbox,
1198 struct mlx4_cmd_info *cmd);
1199 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1200 struct mlx4_vhcr *vhcr,
1201 struct mlx4_cmd_mailbox *inbox,
1202 struct mlx4_cmd_mailbox *outbox,
1203 struct mlx4_cmd_info *cmd);
1204 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1205 struct mlx4_vhcr *vhcr,
1206 struct mlx4_cmd_mailbox *inbox,
1207 struct mlx4_cmd_mailbox *outbox,
1208 struct mlx4_cmd_info *cmd);
1209 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1210 struct mlx4_vhcr *vhcr,
1211 struct mlx4_cmd_mailbox *inbox,
1212 struct mlx4_cmd_mailbox *outbox,
1213 struct mlx4_cmd_info *cmd);
1214 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1215 struct mlx4_vhcr *vhcr,
1216 struct mlx4_cmd_mailbox *inbox,
1217 struct mlx4_cmd_mailbox *outbox,
1218 struct mlx4_cmd_info *cmd);
1219 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1221 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1222 int *gid_tbl_len, int *pkey_tbl_len);
1224 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1225 struct mlx4_vhcr *vhcr,
1226 struct mlx4_cmd_mailbox *inbox,
1227 struct mlx4_cmd_mailbox *outbox,
1228 struct mlx4_cmd_info *cmd);
1230 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1231 struct mlx4_vhcr *vhcr,
1232 struct mlx4_cmd_mailbox *inbox,
1233 struct mlx4_cmd_mailbox *outbox,
1234 struct mlx4_cmd_info *cmd);
1235 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1236 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1237 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1238 int block_mcast_loopback, enum mlx4_protocol prot,
1239 enum mlx4_steer_type steer);
1240 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1241 u8 gid[16], u8 port,
1242 int block_mcast_loopback,
1243 enum mlx4_protocol prot, u64 *reg_id);
1244 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1245 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1246 struct mlx4_vhcr *vhcr,
1247 struct mlx4_cmd_mailbox *inbox,
1248 struct mlx4_cmd_mailbox *outbox,
1249 struct mlx4_cmd_info *cmd);
1250 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1251 struct mlx4_vhcr *vhcr,
1252 struct mlx4_cmd_mailbox *inbox,
1253 struct mlx4_cmd_mailbox *outbox,
1254 struct mlx4_cmd_info *cmd);
1255 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1256 int port, void *buf);
1257 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1258 struct mlx4_vhcr *vhcr,
1259 struct mlx4_cmd_mailbox *inbox,
1260 struct mlx4_cmd_mailbox *outbox,
1261 struct mlx4_cmd_info *cmd);
1262 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1263 struct mlx4_vhcr *vhcr,
1264 struct mlx4_cmd_mailbox *inbox,
1265 struct mlx4_cmd_mailbox *outbox,
1266 struct mlx4_cmd_info *cmd);
1267 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1268 struct mlx4_vhcr *vhcr,
1269 struct mlx4_cmd_mailbox *inbox,
1270 struct mlx4_cmd_mailbox *outbox,
1271 struct mlx4_cmd_info *cmd);
1272 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1273 struct mlx4_vhcr *vhcr,
1274 struct mlx4_cmd_mailbox *inbox,
1275 struct mlx4_cmd_mailbox *outbox,
1276 struct mlx4_cmd_info *cmd);
1277 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1278 struct mlx4_vhcr *vhcr,
1279 struct mlx4_cmd_mailbox *inbox,
1280 struct mlx4_cmd_mailbox *outbox,
1281 struct mlx4_cmd_info *cmd);
1282 int mlx4_MOD_STAT_CFG_wrapper(struct mlx4_dev *dev, int slave,
1283 struct mlx4_vhcr *vhcr,
1284 struct mlx4_cmd_mailbox *inbox,
1285 struct mlx4_cmd_mailbox *outbox,
1286 struct mlx4_cmd_info *cmd);
1288 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1289 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1291 static inline void set_param_l(u64 *arg, u32 val)
1293 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1296 static inline void set_param_h(u64 *arg, u32 val)
1298 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1301 static inline u32 get_param_l(u64 *arg)
1303 return (u32) (*arg & 0xffffffff);
1306 static inline u32 get_param_h(u64 *arg)
1308 return (u32)(*arg >> 32);
1311 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1313 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1316 #define NOT_MASKED_PD_BITS 17
1318 void sys_tune_init(void);
1319 void sys_tune_fini(void);
1321 void mlx4_init_quotas(struct mlx4_dev *dev);
1323 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave);
1324 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave);
1325 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);