2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008, 2014 Mellanox Technologies.
5 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/sched.h>
37 #include <linux/pci.h>
38 #include <linux/errno.h>
39 #include <linux/kernel.h>
41 #include <linux/slab.h>
42 #include <dev/mlx4/cmd.h>
43 #include <dev/mlx4/qp.h>
44 #include <linux/if_ether.h>
45 #include <linux/etherdevice.h>
50 #define MLX4_MAC_VALID (1ull << 63)
53 struct list_head list;
61 struct list_head list;
69 struct list_head list;
84 struct list_head list;
86 enum mlx4_protocol prot;
87 enum mlx4_steer_type steer;
92 RES_QP_BUSY = RES_ANY_BUSY,
94 /* QP number was allocated */
97 /* ICM memory for QP context was mapped */
100 /* QP is in hw ownership */
105 struct res_common com;
110 struct list_head mcg_list;
115 /* saved qp params before VST enforcement in order to restore on VGT */
125 enum res_mtt_states {
126 RES_MTT_BUSY = RES_ANY_BUSY,
130 static inline const char *mtt_states_str(enum res_mtt_states state)
133 case RES_MTT_BUSY: return "RES_MTT_BUSY";
134 case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
135 default: return "Unknown";
140 struct res_common com;
145 enum res_mpt_states {
146 RES_MPT_BUSY = RES_ANY_BUSY,
153 struct res_common com;
159 RES_EQ_BUSY = RES_ANY_BUSY,
165 struct res_common com;
170 RES_CQ_BUSY = RES_ANY_BUSY,
176 struct res_common com;
181 enum res_srq_states {
182 RES_SRQ_BUSY = RES_ANY_BUSY,
188 struct res_common com;
194 enum res_counter_states {
195 RES_COUNTER_BUSY = RES_ANY_BUSY,
196 RES_COUNTER_ALLOCATED,
200 struct res_common com;
204 enum res_xrcdn_states {
205 RES_XRCD_BUSY = RES_ANY_BUSY,
210 struct res_common com;
214 enum res_fs_rule_states {
215 RES_FS_RULE_BUSY = RES_ANY_BUSY,
216 RES_FS_RULE_ALLOCATED,
220 struct res_common com;
224 static int mlx4_is_eth(struct mlx4_dev *dev, int port)
226 return dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
229 static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
231 struct rb_node *node = root->rb_node;
234 struct res_common *res = container_of(node, struct res_common,
237 if (res_id < res->res_id)
238 node = node->rb_left;
239 else if (res_id > res->res_id)
240 node = node->rb_right;
247 static int res_tracker_insert(struct rb_root *root, struct res_common *res)
249 struct rb_node **new = &(root->rb_node), *parent = NULL;
251 /* Figure out where to put new node */
253 struct res_common *this = container_of(*new, struct res_common,
257 if (res->res_id < this->res_id)
258 new = &((*new)->rb_left);
259 else if (res->res_id > this->res_id)
260 new = &((*new)->rb_right);
265 /* Add new node and rebalance tree. */
266 rb_link_node(&res->node, parent, new);
267 rb_insert_color(&res->node, root);
282 static const char *ResourceType(enum mlx4_resource rt)
285 case RES_QP: return "RES_QP";
286 case RES_CQ: return "RES_CQ";
287 case RES_SRQ: return "RES_SRQ";
288 case RES_MPT: return "RES_MPT";
289 case RES_MTT: return "RES_MTT";
290 case RES_MAC: return "RES_MAC";
291 case RES_VLAN: return "RES_VLAN";
292 case RES_EQ: return "RES_EQ";
293 case RES_COUNTER: return "RES_COUNTER";
294 case RES_FS_RULE: return "RES_FS_RULE";
295 case RES_XRCD: return "RES_XRCD";
296 default: return "Unknown resource type !!!";
300 static void rem_slave_vlans(struct mlx4_dev *dev, int slave);
301 static inline int mlx4_grant_resource(struct mlx4_dev *dev, int slave,
302 enum mlx4_resource res_type, int count,
305 struct mlx4_priv *priv = mlx4_priv(dev);
306 struct resource_allocator *res_alloc =
307 &priv->mfunc.master.res_tracker.res_alloc[res_type];
309 int allocated, free, reserved, guaranteed, from_free;
311 spin_lock(&res_alloc->alloc_lock);
312 allocated = (port > 0) ?
313 res_alloc->allocated[(port - 1) * (dev->num_vfs + 1) + slave] :
314 res_alloc->allocated[slave];
315 free = (port > 0) ? res_alloc->res_port_free[port - 1] :
317 reserved = (port > 0) ? res_alloc->res_port_rsvd[port - 1] :
318 res_alloc->res_reserved;
319 guaranteed = res_alloc->guaranteed[slave];
321 if (allocated + count > res_alloc->quota[slave])
324 if (allocated + count <= guaranteed) {
327 /* portion may need to be obtained from free area */
328 if (guaranteed - allocated > 0)
329 from_free = count - (guaranteed - allocated);
333 if (free - from_free > reserved)
338 /* grant the request */
340 res_alloc->allocated[(port - 1) * (dev->num_vfs + 1) + slave] += count;
341 res_alloc->res_port_free[port - 1] -= count;
343 res_alloc->allocated[slave] += count;
344 res_alloc->res_free -= count;
349 spin_unlock(&res_alloc->alloc_lock);
354 static inline void mlx4_release_resource(struct mlx4_dev *dev, int slave,
355 enum mlx4_resource res_type, int count,
358 struct mlx4_priv *priv = mlx4_priv(dev);
359 struct resource_allocator *res_alloc =
360 &priv->mfunc.master.res_tracker.res_alloc[res_type];
362 spin_lock(&res_alloc->alloc_lock);
364 res_alloc->allocated[(port - 1) * (dev->num_vfs + 1) + slave] -= count;
365 res_alloc->res_port_free[port - 1] += count;
367 res_alloc->allocated[slave] -= count;
368 res_alloc->res_free += count;
371 spin_unlock(&res_alloc->alloc_lock);
375 static inline void initialize_res_quotas(struct mlx4_dev *dev,
376 struct resource_allocator *res_alloc,
377 enum mlx4_resource res_type,
378 int vf, int num_instances)
380 res_alloc->guaranteed[vf] = num_instances / (2 * (dev->num_vfs + 1));
381 res_alloc->quota[vf] = (num_instances / 2) + res_alloc->guaranteed[vf];
382 if (vf == mlx4_master_func_num(dev)) {
383 res_alloc->res_free = num_instances;
384 if (res_type == RES_MTT) {
385 /* reserved mtts will be taken out of the PF allocation */
386 res_alloc->res_free += dev->caps.reserved_mtts;
387 res_alloc->guaranteed[vf] += dev->caps.reserved_mtts;
388 res_alloc->quota[vf] += dev->caps.reserved_mtts;
393 void mlx4_init_quotas(struct mlx4_dev *dev)
395 struct mlx4_priv *priv = mlx4_priv(dev);
398 /* quotas for VFs are initialized in mlx4_slave_cap */
399 if (mlx4_is_slave(dev))
402 if (!mlx4_is_mfunc(dev)) {
403 dev->quotas.qp = dev->caps.num_qps - dev->caps.reserved_qps -
404 mlx4_num_reserved_sqps(dev);
405 dev->quotas.cq = dev->caps.num_cqs - dev->caps.reserved_cqs;
406 dev->quotas.srq = dev->caps.num_srqs - dev->caps.reserved_srqs;
407 dev->quotas.mtt = dev->caps.num_mtts - dev->caps.reserved_mtts;
408 dev->quotas.mpt = dev->caps.num_mpts - dev->caps.reserved_mrws;
412 pf = mlx4_master_func_num(dev);
414 priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[pf];
416 priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[pf];
418 priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[pf];
420 priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[pf];
422 priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[pf];
424 int mlx4_init_resource_tracker(struct mlx4_dev *dev)
426 struct mlx4_priv *priv = mlx4_priv(dev);
430 priv->mfunc.master.res_tracker.slave_list =
431 kzalloc(dev->num_slaves * sizeof(struct slave_list),
433 if (!priv->mfunc.master.res_tracker.slave_list)
436 for (i = 0 ; i < dev->num_slaves; i++) {
437 for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
438 INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
439 slave_list[i].res_list[t]);
440 mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
443 mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
445 for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
446 priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
448 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
449 struct resource_allocator *res_alloc =
450 &priv->mfunc.master.res_tracker.res_alloc[i];
451 res_alloc->quota = kmalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
452 res_alloc->guaranteed = kmalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
453 if (i == RES_MAC || i == RES_VLAN)
454 res_alloc->allocated = kzalloc(MLX4_MAX_PORTS *
455 (dev->num_vfs + 1) * sizeof(int),
458 res_alloc->allocated = kzalloc((dev->num_vfs + 1) * sizeof(int), GFP_KERNEL);
460 if (!res_alloc->quota || !res_alloc->guaranteed ||
461 !res_alloc->allocated)
464 spin_lock_init(&res_alloc->alloc_lock);
465 for (t = 0; t < dev->num_vfs + 1; t++) {
468 initialize_res_quotas(dev, res_alloc, RES_QP,
469 t, dev->caps.num_qps -
470 dev->caps.reserved_qps -
471 mlx4_num_reserved_sqps(dev));
474 initialize_res_quotas(dev, res_alloc, RES_CQ,
475 t, dev->caps.num_cqs -
476 dev->caps.reserved_cqs);
479 initialize_res_quotas(dev, res_alloc, RES_SRQ,
480 t, dev->caps.num_srqs -
481 dev->caps.reserved_srqs);
484 initialize_res_quotas(dev, res_alloc, RES_MPT,
485 t, dev->caps.num_mpts -
486 dev->caps.reserved_mrws);
489 initialize_res_quotas(dev, res_alloc, RES_MTT,
490 t, dev->caps.num_mtts -
491 dev->caps.reserved_mtts);
494 if (t == mlx4_master_func_num(dev)) {
495 res_alloc->quota[t] =
496 MLX4_MAX_MAC_NUM - 2 * dev->num_vfs;
497 res_alloc->guaranteed[t] = res_alloc->quota[t];
498 for (j = 0; j < MLX4_MAX_PORTS; j++)
499 res_alloc->res_port_free[j] = MLX4_MAX_MAC_NUM;
501 res_alloc->quota[t] = 2;
502 res_alloc->guaranteed[t] = 2;
506 if (t == mlx4_master_func_num(dev)) {
507 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM;
508 res_alloc->guaranteed[t] = MLX4_MAX_VLAN_NUM / 2;
509 for (j = 0; j < MLX4_MAX_PORTS; j++)
510 res_alloc->res_port_free[j] =
513 res_alloc->quota[t] = MLX4_MAX_VLAN_NUM / 2;
514 res_alloc->guaranteed[t] = 0;
518 res_alloc->quota[t] = dev->caps.max_counters;
519 res_alloc->guaranteed[t] = 0;
520 if (t == mlx4_master_func_num(dev))
521 res_alloc->res_free = res_alloc->quota[t];
526 if (i == RES_MAC || i == RES_VLAN) {
527 for (j = 0; j < MLX4_MAX_PORTS; j++)
528 res_alloc->res_port_rsvd[j] +=
529 res_alloc->guaranteed[t];
531 res_alloc->res_reserved += res_alloc->guaranteed[t];
535 spin_lock_init(&priv->mfunc.master.res_tracker.lock);
539 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
540 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
541 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
542 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
543 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
544 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
545 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
550 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
551 enum mlx4_res_tracker_free_type type)
553 struct mlx4_priv *priv = mlx4_priv(dev);
556 if (priv->mfunc.master.res_tracker.slave_list) {
557 if (type != RES_TR_FREE_STRUCTS_ONLY) {
558 for (i = 0; i < dev->num_slaves; i++) {
559 if (type == RES_TR_FREE_ALL ||
560 dev->caps.function != i)
561 mlx4_delete_all_resources_for_slave(dev, i);
563 /* free master's vlans */
564 i = dev->caps.function;
565 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
566 rem_slave_vlans(dev, i);
567 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
570 if (type != RES_TR_FREE_SLAVES_ONLY) {
571 for (i = 0; i < MLX4_NUM_OF_RESOURCE_TYPE; i++) {
572 kfree(priv->mfunc.master.res_tracker.res_alloc[i].allocated);
573 priv->mfunc.master.res_tracker.res_alloc[i].allocated = NULL;
574 kfree(priv->mfunc.master.res_tracker.res_alloc[i].guaranteed);
575 priv->mfunc.master.res_tracker.res_alloc[i].guaranteed = NULL;
576 kfree(priv->mfunc.master.res_tracker.res_alloc[i].quota);
577 priv->mfunc.master.res_tracker.res_alloc[i].quota = NULL;
579 kfree(priv->mfunc.master.res_tracker.slave_list);
580 priv->mfunc.master.res_tracker.slave_list = NULL;
585 static void update_pkey_index(struct mlx4_dev *dev, int slave,
586 struct mlx4_cmd_mailbox *inbox)
588 u8 sched = *(u8 *)(inbox->buf + 64);
589 u8 orig_index = *(u8 *)(inbox->buf + 35);
591 struct mlx4_priv *priv = mlx4_priv(dev);
594 port = (sched >> 6 & 1) + 1;
596 new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
597 *(u8 *)(inbox->buf + 35) = new_index;
600 static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
603 struct mlx4_qp_context *qp_ctx = inbox->buf + 8;
604 enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf);
605 u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
608 if (MLX4_QP_ST_UD == ts) {
609 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
610 if (mlx4_is_eth(dev, port))
611 qp_ctx->pri_path.mgid_index = mlx4_get_base_gid_ix(dev, slave) | 0x80;
613 qp_ctx->pri_path.mgid_index = 0x80 | slave;
615 } else if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_UC == ts) {
616 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
617 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
618 if (mlx4_is_eth(dev, port)) {
619 qp_ctx->pri_path.mgid_index += mlx4_get_base_gid_ix(dev, slave);
620 qp_ctx->pri_path.mgid_index &= 0x7f;
622 qp_ctx->pri_path.mgid_index = slave & 0x7F;
625 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
626 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
627 if (mlx4_is_eth(dev, port)) {
628 qp_ctx->alt_path.mgid_index += mlx4_get_base_gid_ix(dev, slave);
629 qp_ctx->alt_path.mgid_index &= 0x7f;
631 qp_ctx->alt_path.mgid_index = slave & 0x7F;
637 static int check_counter_index_validity(struct mlx4_dev *dev, int slave, int port, int idx)
639 struct mlx4_priv *priv = mlx4_priv(dev);
640 struct counter_index *counter, *tmp_counter;
643 list_for_each_entry_safe(counter, tmp_counter,
644 &priv->counters_table.global_port_list[port - 1],
646 if (counter->index == idx)
651 list_for_each_entry_safe(counter, tmp_counter,
652 &priv->counters_table.vf_list[slave - 1][port - 1],
654 if (counter->index == idx)
661 static int update_vport_qp_param(struct mlx4_dev *dev,
662 struct mlx4_cmd_mailbox *inbox,
665 struct mlx4_qp_context *qpc = inbox->buf + 8;
666 struct mlx4_vport_oper_state *vp_oper;
667 struct mlx4_priv *priv;
671 port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
672 priv = mlx4_priv(dev);
673 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
674 qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
676 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH &&
677 qpc->pri_path.counter_index != MLX4_SINK_COUNTER_INDEX) {
678 if (check_counter_index_validity(dev, slave, port,
679 qpc->pri_path.counter_index))
683 mlx4_dbg(dev, "%s: QP counter_index %d for slave %d port %d\n",
684 __func__, qpc->pri_path.counter_index, slave, port);
686 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK) &&
687 dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH &&
688 !mlx4_is_qp_reserved(dev, qpn) &&
689 qp_type == MLX4_QP_ST_MLX &&
690 qpc->pri_path.counter_index != 0xFF) {
691 /* disable multicast loopback to qp with same counter */
692 qpc->pri_path.fl |= MLX4_FL_ETH_SRC_CHECK_MC_LB;
693 qpc->pri_path.vlan_control |=
694 MLX4_VLAN_CTRL_ETH_SRC_CHECK_IF_COUNTER;
697 if (MLX4_VGT != vp_oper->state.default_vlan) {
698 /* the reserved QPs (special, proxy, tunnel)
699 * do not operate over vlans
701 if (mlx4_is_qp_reserved(dev, qpn))
704 /* force strip vlan by clear vsd */
705 qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
706 /* preserve IF_COUNTER flag */
707 qpc->pri_path.vlan_control &=
708 MLX4_VLAN_CTRL_ETH_SRC_CHECK_IF_COUNTER;
709 if (MLX4_QP_ST_RC != qp_type) {
710 if (0 != vp_oper->state.default_vlan) {
711 qpc->pri_path.vlan_control |=
712 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
713 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
714 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
715 } else { /* priority tagged */
716 qpc->pri_path.vlan_control |=
717 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
718 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
721 qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
722 qpc->pri_path.vlan_index = vp_oper->vlan_idx;
723 qpc->pri_path.fl |= MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
724 qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
725 qpc->pri_path.sched_queue &= 0xC7;
726 qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
728 if (vp_oper->state.spoofchk) {
729 qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
730 qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
735 static int mpt_mask(struct mlx4_dev *dev)
737 return dev->caps.num_mpts - 1;
740 static void *find_res(struct mlx4_dev *dev, u64 res_id,
741 enum mlx4_resource type)
743 struct mlx4_priv *priv = mlx4_priv(dev);
745 return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
749 static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
750 enum mlx4_resource type,
753 struct res_common *r;
756 spin_lock_irq(mlx4_tlock(dev));
757 r = find_res(dev, res_id, type);
763 if (r->state == RES_ANY_BUSY) {
768 if (r->owner != slave) {
773 r->from_state = r->state;
774 r->state = RES_ANY_BUSY;
777 *((struct res_common **)res) = r;
780 spin_unlock_irq(mlx4_tlock(dev));
784 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
785 enum mlx4_resource type,
786 u64 res_id, int *slave)
789 struct res_common *r;
795 spin_lock(mlx4_tlock(dev));
797 r = find_res(dev, id, type);
802 spin_unlock(mlx4_tlock(dev));
807 static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
808 enum mlx4_resource type)
810 struct res_common *r;
812 spin_lock_irq(mlx4_tlock(dev));
813 r = find_res(dev, res_id, type);
815 r->state = r->from_state;
816 spin_unlock_irq(mlx4_tlock(dev));
819 static struct res_common *alloc_qp_tr(int id)
823 ret = kzalloc(sizeof *ret, GFP_KERNEL);
827 ret->com.res_id = id;
828 ret->com.state = RES_QP_RESERVED;
830 INIT_LIST_HEAD(&ret->mcg_list);
831 spin_lock_init(&ret->mcg_spl);
832 atomic_set(&ret->ref_count, 0);
837 static struct res_common *alloc_mtt_tr(int id, int order)
841 ret = kzalloc(sizeof *ret, GFP_KERNEL);
845 ret->com.res_id = id;
847 ret->com.state = RES_MTT_ALLOCATED;
848 atomic_set(&ret->ref_count, 0);
853 static struct res_common *alloc_mpt_tr(int id, int key)
857 ret = kzalloc(sizeof *ret, GFP_KERNEL);
861 ret->com.res_id = id;
862 ret->com.state = RES_MPT_RESERVED;
868 static struct res_common *alloc_eq_tr(int id)
872 ret = kzalloc(sizeof *ret, GFP_KERNEL);
876 ret->com.res_id = id;
877 ret->com.state = RES_EQ_RESERVED;
882 static struct res_common *alloc_cq_tr(int id)
886 ret = kzalloc(sizeof *ret, GFP_KERNEL);
890 ret->com.res_id = id;
891 ret->com.state = RES_CQ_ALLOCATED;
892 atomic_set(&ret->ref_count, 0);
897 static struct res_common *alloc_srq_tr(int id)
901 ret = kzalloc(sizeof *ret, GFP_KERNEL);
905 ret->com.res_id = id;
906 ret->com.state = RES_SRQ_ALLOCATED;
907 atomic_set(&ret->ref_count, 0);
912 static struct res_common *alloc_counter_tr(int id)
914 struct res_counter *ret;
916 ret = kzalloc(sizeof *ret, GFP_KERNEL);
920 ret->com.res_id = id;
921 ret->com.state = RES_COUNTER_ALLOCATED;
926 static struct res_common *alloc_xrcdn_tr(int id)
928 struct res_xrcdn *ret;
930 ret = kzalloc(sizeof *ret, GFP_KERNEL);
934 ret->com.res_id = id;
935 ret->com.state = RES_XRCD_ALLOCATED;
940 static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
942 struct res_fs_rule *ret;
944 ret = kzalloc(sizeof *ret, GFP_KERNEL);
948 ret->com.res_id = id;
949 ret->com.state = RES_FS_RULE_ALLOCATED;
954 static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
957 struct res_common *ret;
961 ret = alloc_qp_tr(id);
964 ret = alloc_mpt_tr(id, extra);
967 ret = alloc_mtt_tr(id, extra);
970 ret = alloc_eq_tr(id);
973 ret = alloc_cq_tr(id);
976 ret = alloc_srq_tr(id);
979 printk(KERN_ERR "implementation missing\n");
982 ret = alloc_counter_tr(id);
985 ret = alloc_xrcdn_tr(id);
988 ret = alloc_fs_rule_tr(id, extra);
999 static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
1000 enum mlx4_resource type, int extra)
1004 struct mlx4_priv *priv = mlx4_priv(dev);
1005 struct res_common **res_arr;
1006 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1007 struct rb_root *root = &tracker->res_tree[type];
1009 res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
1013 for (i = 0; i < count; ++i) {
1014 res_arr[i] = alloc_tr(base + i, type, slave, extra);
1016 for (--i; i >= 0; --i)
1024 spin_lock_irq(mlx4_tlock(dev));
1025 for (i = 0; i < count; ++i) {
1026 if (find_res(dev, base + i, type)) {
1030 err = res_tracker_insert(root, res_arr[i]);
1033 list_add_tail(&res_arr[i]->list,
1034 &tracker->slave_list[slave].res_list[type]);
1036 spin_unlock_irq(mlx4_tlock(dev));
1042 for (--i; i >= 0; --i) {
1043 rb_erase(&res_arr[i]->node, root);
1044 list_del_init(&res_arr[i]->list);
1047 spin_unlock_irq(mlx4_tlock(dev));
1049 for (i = 0; i < count; ++i)
1057 static int remove_qp_ok(struct res_qp *res)
1059 if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
1060 !list_empty(&res->mcg_list)) {
1061 pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
1062 res->com.state, atomic_read(&res->ref_count));
1064 } else if (res->com.state != RES_QP_RESERVED) {
1071 static int remove_mtt_ok(struct res_mtt *res, int order)
1073 if (res->com.state == RES_MTT_BUSY ||
1074 atomic_read(&res->ref_count)) {
1075 printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
1077 mtt_states_str(res->com.state),
1078 atomic_read(&res->ref_count));
1080 } else if (res->com.state != RES_MTT_ALLOCATED)
1082 else if (res->order != order)
1088 static int remove_mpt_ok(struct res_mpt *res)
1090 if (res->com.state == RES_MPT_BUSY)
1092 else if (res->com.state != RES_MPT_RESERVED)
1098 static int remove_eq_ok(struct res_eq *res)
1100 if (res->com.state == RES_MPT_BUSY)
1102 else if (res->com.state != RES_MPT_RESERVED)
1108 static int remove_counter_ok(struct res_counter *res)
1110 if (res->com.state == RES_COUNTER_BUSY)
1112 else if (res->com.state != RES_COUNTER_ALLOCATED)
1118 static int remove_xrcdn_ok(struct res_xrcdn *res)
1120 if (res->com.state == RES_XRCD_BUSY)
1122 else if (res->com.state != RES_XRCD_ALLOCATED)
1128 static int remove_fs_rule_ok(struct res_fs_rule *res)
1130 if (res->com.state == RES_FS_RULE_BUSY)
1132 else if (res->com.state != RES_FS_RULE_ALLOCATED)
1138 static int remove_cq_ok(struct res_cq *res)
1140 if (res->com.state == RES_CQ_BUSY)
1142 else if (res->com.state != RES_CQ_ALLOCATED)
1148 static int remove_srq_ok(struct res_srq *res)
1150 if (res->com.state == RES_SRQ_BUSY)
1152 else if (res->com.state != RES_SRQ_ALLOCATED)
1158 static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
1162 return remove_qp_ok((struct res_qp *)res);
1164 return remove_cq_ok((struct res_cq *)res);
1166 return remove_srq_ok((struct res_srq *)res);
1168 return remove_mpt_ok((struct res_mpt *)res);
1170 return remove_mtt_ok((struct res_mtt *)res, extra);
1174 return remove_eq_ok((struct res_eq *)res);
1176 return remove_counter_ok((struct res_counter *)res);
1178 return remove_xrcdn_ok((struct res_xrcdn *)res);
1180 return remove_fs_rule_ok((struct res_fs_rule *)res);
1186 static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
1187 enum mlx4_resource type, int extra)
1191 struct mlx4_priv *priv = mlx4_priv(dev);
1192 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1193 struct res_common *r;
1195 spin_lock_irq(mlx4_tlock(dev));
1196 for (i = base; i < base + count; ++i) {
1197 r = res_tracker_lookup(&tracker->res_tree[type], i);
1202 if (r->owner != slave) {
1206 err = remove_ok(r, type, extra);
1211 for (i = base; i < base + count; ++i) {
1212 r = res_tracker_lookup(&tracker->res_tree[type], i);
1213 rb_erase(&r->node, &tracker->res_tree[type]);
1220 spin_unlock_irq(mlx4_tlock(dev));
1225 static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
1226 enum res_qp_states state, struct res_qp **qp,
1229 struct mlx4_priv *priv = mlx4_priv(dev);
1230 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1234 spin_lock_irq(mlx4_tlock(dev));
1235 r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
1238 else if (r->com.owner != slave)
1243 mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
1244 __func__, (unsigned long long)r->com.res_id);
1248 case RES_QP_RESERVED:
1249 if (r->com.state == RES_QP_MAPPED && !alloc)
1252 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", (unsigned long long)r->com.res_id);
1257 if ((r->com.state == RES_QP_RESERVED && alloc) ||
1258 r->com.state == RES_QP_HW)
1261 mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
1262 (unsigned long long)r->com.res_id);
1269 if (r->com.state != RES_QP_MAPPED)
1277 r->com.from_state = r->com.state;
1278 r->com.to_state = state;
1279 r->com.state = RES_QP_BUSY;
1285 spin_unlock_irq(mlx4_tlock(dev));
1290 static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1291 enum res_mpt_states state, struct res_mpt **mpt)
1293 struct mlx4_priv *priv = mlx4_priv(dev);
1294 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1298 spin_lock_irq(mlx4_tlock(dev));
1299 r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
1302 else if (r->com.owner != slave)
1310 case RES_MPT_RESERVED:
1311 if (r->com.state != RES_MPT_MAPPED)
1315 case RES_MPT_MAPPED:
1316 if (r->com.state != RES_MPT_RESERVED &&
1317 r->com.state != RES_MPT_HW)
1322 if (r->com.state != RES_MPT_MAPPED)
1330 r->com.from_state = r->com.state;
1331 r->com.to_state = state;
1332 r->com.state = RES_MPT_BUSY;
1338 spin_unlock_irq(mlx4_tlock(dev));
1343 static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1344 enum res_eq_states state, struct res_eq **eq)
1346 struct mlx4_priv *priv = mlx4_priv(dev);
1347 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1351 spin_lock_irq(mlx4_tlock(dev));
1352 r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
1355 else if (r->com.owner != slave)
1363 case RES_EQ_RESERVED:
1364 if (r->com.state != RES_EQ_HW)
1369 if (r->com.state != RES_EQ_RESERVED)
1378 r->com.from_state = r->com.state;
1379 r->com.to_state = state;
1380 r->com.state = RES_EQ_BUSY;
1386 spin_unlock_irq(mlx4_tlock(dev));
1391 static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
1392 enum res_cq_states state, struct res_cq **cq)
1394 struct mlx4_priv *priv = mlx4_priv(dev);
1395 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1399 spin_lock_irq(mlx4_tlock(dev));
1400 r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
1403 else if (r->com.owner != slave)
1411 case RES_CQ_ALLOCATED:
1412 if (r->com.state != RES_CQ_HW)
1414 else if (atomic_read(&r->ref_count))
1421 if (r->com.state != RES_CQ_ALLOCATED)
1432 r->com.from_state = r->com.state;
1433 r->com.to_state = state;
1434 r->com.state = RES_CQ_BUSY;
1440 spin_unlock_irq(mlx4_tlock(dev));
1445 static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
1446 enum res_srq_states state, struct res_srq **srq)
1448 struct mlx4_priv *priv = mlx4_priv(dev);
1449 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1453 spin_lock_irq(mlx4_tlock(dev));
1454 r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
1457 else if (r->com.owner != slave)
1465 case RES_SRQ_ALLOCATED:
1466 if (r->com.state != RES_SRQ_HW)
1468 else if (atomic_read(&r->ref_count))
1473 if (r->com.state != RES_SRQ_ALLOCATED)
1482 r->com.from_state = r->com.state;
1483 r->com.to_state = state;
1484 r->com.state = RES_SRQ_BUSY;
1490 spin_unlock_irq(mlx4_tlock(dev));
1495 static void res_abort_move(struct mlx4_dev *dev, int slave,
1496 enum mlx4_resource type, int id)
1498 struct mlx4_priv *priv = mlx4_priv(dev);
1499 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1500 struct res_common *r;
1502 spin_lock_irq(mlx4_tlock(dev));
1503 r = res_tracker_lookup(&tracker->res_tree[type], id);
1504 if (r && (r->owner == slave))
1505 r->state = r->from_state;
1506 spin_unlock_irq(mlx4_tlock(dev));
1509 static void res_end_move(struct mlx4_dev *dev, int slave,
1510 enum mlx4_resource type, int id)
1512 struct mlx4_priv *priv = mlx4_priv(dev);
1513 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1514 struct res_common *r;
1516 spin_lock_irq(mlx4_tlock(dev));
1517 r = res_tracker_lookup(&tracker->res_tree[type], id);
1518 if (r && (r->owner == slave))
1519 r->state = r->to_state;
1520 spin_unlock_irq(mlx4_tlock(dev));
1523 static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
1525 return mlx4_is_qp_reserved(dev, qpn) &&
1526 (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
1529 static int fw_reserved(struct mlx4_dev *dev, int qpn)
1531 return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
1534 static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1535 u64 in_param, u64 *out_param)
1545 case RES_OP_RESERVE:
1546 count = get_param_l(&in_param) & 0xffffff;
1547 /* Turn off all unsupported QP allocation flags that the
1548 * slave tries to set.
1550 flags = (get_param_l(&in_param) >> 24) & dev->caps.alloc_res_qp_mask;
1551 align = get_param_h(&in_param);
1552 err = mlx4_grant_resource(dev, slave, RES_QP, count, 0);
1556 err = __mlx4_qp_reserve_range(dev, count, align, &base, flags);
1558 mlx4_release_resource(dev, slave, RES_QP, count, 0);
1562 err = add_res_range(dev, slave, base, count, RES_QP, 0);
1564 mlx4_release_resource(dev, slave, RES_QP, count, 0);
1565 __mlx4_qp_release_range(dev, base, count);
1568 set_param_l(out_param, base);
1570 case RES_OP_MAP_ICM:
1571 qpn = get_param_l(&in_param) & 0x7fffff;
1572 if (valid_reserved(dev, slave, qpn)) {
1573 err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
1578 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
1583 if (!fw_reserved(dev, qpn)) {
1584 err = __mlx4_qp_alloc_icm(dev, qpn);
1586 res_abort_move(dev, slave, RES_QP, qpn);
1591 res_end_move(dev, slave, RES_QP, qpn);
1601 static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1602 u64 in_param, u64 *out_param)
1608 if (op != RES_OP_RESERVE_AND_MAP)
1611 order = get_param_l(&in_param);
1613 err = mlx4_grant_resource(dev, slave, RES_MTT, 1 << order, 0);
1617 base = __mlx4_alloc_mtt_range(dev, order);
1619 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
1623 err = add_res_range(dev, slave, base, 1, RES_MTT, order);
1625 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
1626 __mlx4_free_mtt_range(dev, base, order);
1628 set_param_l(out_param, base);
1633 static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1634 u64 in_param, u64 *out_param)
1639 struct res_mpt *mpt;
1642 case RES_OP_RESERVE:
1643 err = mlx4_grant_resource(dev, slave, RES_MPT, 1, 0);
1647 index = __mlx4_mpt_reserve(dev);
1649 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
1652 id = index & mpt_mask(dev);
1654 err = add_res_range(dev, slave, id, 1, RES_MPT, index);
1656 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
1657 __mlx4_mpt_release(dev, index);
1660 set_param_l(out_param, index);
1662 case RES_OP_MAP_ICM:
1663 index = get_param_l(&in_param);
1664 id = index & mpt_mask(dev);
1665 err = mr_res_start_move_to(dev, slave, id,
1666 RES_MPT_MAPPED, &mpt);
1670 err = __mlx4_mpt_alloc_icm(dev, mpt->key);
1672 res_abort_move(dev, slave, RES_MPT, id);
1676 res_end_move(dev, slave, RES_MPT, id);
1682 static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1683 u64 in_param, u64 *out_param)
1689 case RES_OP_RESERVE_AND_MAP:
1690 err = mlx4_grant_resource(dev, slave, RES_CQ, 1, 0);
1694 err = __mlx4_cq_alloc_icm(dev, &cqn);
1696 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
1700 err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
1702 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
1703 __mlx4_cq_free_icm(dev, cqn);
1707 set_param_l(out_param, cqn);
1717 static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1718 u64 in_param, u64 *out_param)
1724 case RES_OP_RESERVE_AND_MAP:
1725 err = mlx4_grant_resource(dev, slave, RES_SRQ, 1, 0);
1729 err = __mlx4_srq_alloc_icm(dev, &srqn);
1731 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
1735 err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
1737 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
1738 __mlx4_srq_free_icm(dev, srqn);
1742 set_param_l(out_param, srqn);
1752 static int mac_find_smac_ix_in_slave(struct mlx4_dev *dev, int slave, int port,
1753 u8 smac_index, u64 *mac)
1755 struct mlx4_priv *priv = mlx4_priv(dev);
1756 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1757 struct list_head *mac_list =
1758 &tracker->slave_list[slave].res_list[RES_MAC];
1759 struct mac_res *res, *tmp;
1761 list_for_each_entry_safe(res, tmp, mac_list, list) {
1762 if (res->smac_index == smac_index && res->port == (u8) port) {
1770 static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port, u8 smac_index)
1772 struct mlx4_priv *priv = mlx4_priv(dev);
1773 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1774 struct list_head *mac_list =
1775 &tracker->slave_list[slave].res_list[RES_MAC];
1776 struct mac_res *res, *tmp;
1778 list_for_each_entry_safe(res, tmp, mac_list, list) {
1779 if (res->mac == mac && res->port == (u8) port) {
1780 /* mac found. update ref count */
1786 if (mlx4_grant_resource(dev, slave, RES_MAC, 1, port))
1788 res = kzalloc(sizeof *res, GFP_KERNEL);
1790 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
1794 res->port = (u8) port;
1795 res->smac_index = smac_index;
1797 list_add_tail(&res->list,
1798 &tracker->slave_list[slave].res_list[RES_MAC]);
1803 static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
1806 struct mlx4_priv *priv = mlx4_priv(dev);
1807 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1808 struct list_head *mac_list =
1809 &tracker->slave_list[slave].res_list[RES_MAC];
1810 struct mac_res *res, *tmp;
1812 list_for_each_entry_safe(res, tmp, mac_list, list) {
1813 if (res->mac == mac && res->port == (u8) port) {
1814 if (!--res->ref_count) {
1815 list_del(&res->list);
1816 mlx4_release_resource(dev, slave, RES_MAC, 1, port);
1824 static void rem_slave_macs(struct mlx4_dev *dev, int slave)
1826 struct mlx4_priv *priv = mlx4_priv(dev);
1827 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1828 struct list_head *mac_list =
1829 &tracker->slave_list[slave].res_list[RES_MAC];
1830 struct mac_res *res, *tmp;
1833 list_for_each_entry_safe(res, tmp, mac_list, list) {
1834 list_del(&res->list);
1835 /* dereference the mac the num times the slave referenced it */
1836 for (i = 0; i < res->ref_count; i++)
1837 __mlx4_unregister_mac(dev, res->port, res->mac);
1838 mlx4_release_resource(dev, slave, RES_MAC, 1, res->port);
1843 static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1844 u64 in_param, u64 *out_param, int in_port)
1851 if (op != RES_OP_RESERVE_AND_MAP)
1854 port = !in_port ? get_param_l(out_param) : in_port;
1857 err = __mlx4_register_mac(dev, port, mac);
1860 set_param_l(out_param, err);
1865 err = mac_add_to_slave(dev, slave, mac, port, smac_index);
1867 __mlx4_unregister_mac(dev, port, mac);
1872 static int vlan_add_to_slave(struct mlx4_dev *dev, int slave, u16 vlan,
1873 int port, int vlan_index)
1875 struct mlx4_priv *priv = mlx4_priv(dev);
1876 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1877 struct list_head *vlan_list =
1878 &tracker->slave_list[slave].res_list[RES_VLAN];
1879 struct vlan_res *res, *tmp;
1881 list_for_each_entry_safe(res, tmp, vlan_list, list) {
1882 if (res->vlan == vlan && res->port == (u8) port) {
1883 /* vlan found. update ref count */
1889 if (mlx4_grant_resource(dev, slave, RES_VLAN, 1, port))
1891 res = kzalloc(sizeof(*res), GFP_KERNEL);
1893 mlx4_release_resource(dev, slave, RES_VLAN, 1, port);
1897 res->port = (u8) port;
1898 res->vlan_index = vlan_index;
1900 list_add_tail(&res->list,
1901 &tracker->slave_list[slave].res_list[RES_VLAN]);
1906 static void vlan_del_from_slave(struct mlx4_dev *dev, int slave, u16 vlan,
1909 struct mlx4_priv *priv = mlx4_priv(dev);
1910 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1911 struct list_head *vlan_list =
1912 &tracker->slave_list[slave].res_list[RES_VLAN];
1913 struct vlan_res *res, *tmp;
1915 list_for_each_entry_safe(res, tmp, vlan_list, list) {
1916 if (res->vlan == vlan && res->port == (u8) port) {
1917 if (!--res->ref_count) {
1918 list_del(&res->list);
1919 mlx4_release_resource(dev, slave, RES_VLAN,
1928 static void rem_slave_vlans(struct mlx4_dev *dev, int slave)
1930 struct mlx4_priv *priv = mlx4_priv(dev);
1931 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
1932 struct list_head *vlan_list =
1933 &tracker->slave_list[slave].res_list[RES_VLAN];
1934 struct vlan_res *res, *tmp;
1937 list_for_each_entry_safe(res, tmp, vlan_list, list) {
1938 list_del(&res->list);
1939 /* dereference the vlan the num times the slave referenced it */
1940 for (i = 0; i < res->ref_count; i++)
1941 __mlx4_unregister_vlan(dev, res->port, res->vlan);
1942 mlx4_release_resource(dev, slave, RES_VLAN, 1, res->port);
1947 static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1948 u64 in_param, u64 *out_param, int in_port)
1950 struct mlx4_priv *priv = mlx4_priv(dev);
1951 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1957 port = !in_port ? get_param_l(out_param) : in_port;
1962 if (op != RES_OP_RESERVE_AND_MAP)
1965 /* upstream kernels had NOP for reg/unreg vlan. Continue this. */
1966 if (!in_port && port > 0 && port <= dev->caps.num_ports) {
1967 slave_state[slave].old_vlan_api = true;
1971 vlan = (u16) in_param;
1973 err = __mlx4_register_vlan(dev, port, vlan, &vlan_index);
1975 set_param_l(out_param, (u32) vlan_index);
1976 err = vlan_add_to_slave(dev, slave, vlan, port, vlan_index);
1978 __mlx4_unregister_vlan(dev, port, vlan);
1983 static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
1984 u64 in_param, u64 *out_param, int port)
1989 if (op != RES_OP_RESERVE)
1992 err = __mlx4_counter_alloc(dev, slave, port, &index);
1994 set_param_l(out_param, index);
1999 static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2000 u64 in_param, u64 *out_param)
2005 if (op != RES_OP_RESERVE)
2008 err = __mlx4_xrcd_alloc(dev, &xrcdn);
2012 err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2014 __mlx4_xrcd_free(dev, xrcdn);
2016 set_param_l(out_param, xrcdn);
2021 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
2022 struct mlx4_vhcr *vhcr,
2023 struct mlx4_cmd_mailbox *inbox,
2024 struct mlx4_cmd_mailbox *outbox,
2025 struct mlx4_cmd_info *cmd)
2028 int alop = vhcr->op_modifier;
2030 switch (vhcr->in_modifier & 0xFF) {
2032 err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
2033 vhcr->in_param, &vhcr->out_param);
2037 err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2038 vhcr->in_param, &vhcr->out_param);
2042 err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
2043 vhcr->in_param, &vhcr->out_param);
2047 err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2048 vhcr->in_param, &vhcr->out_param);
2052 err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
2053 vhcr->in_param, &vhcr->out_param);
2057 err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
2058 vhcr->in_param, &vhcr->out_param,
2059 (vhcr->in_modifier >> 8) & 0xFF);
2063 err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
2064 vhcr->in_param, &vhcr->out_param,
2065 (vhcr->in_modifier >> 8) & 0xFF);
2069 err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
2070 vhcr->in_param, &vhcr->out_param,
2071 (vhcr->in_modifier >> 8) & 0xFF);
2075 err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
2076 vhcr->in_param, &vhcr->out_param);
2087 static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2096 case RES_OP_RESERVE:
2097 base = get_param_l(&in_param) & 0x7fffff;
2098 count = get_param_h(&in_param);
2099 err = rem_res_range(dev, slave, base, count, RES_QP, 0);
2102 mlx4_release_resource(dev, slave, RES_QP, count, 0);
2103 __mlx4_qp_release_range(dev, base, count);
2105 case RES_OP_MAP_ICM:
2106 qpn = get_param_l(&in_param) & 0x7fffff;
2107 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
2112 if (!fw_reserved(dev, qpn))
2113 __mlx4_qp_free_icm(dev, qpn);
2115 res_end_move(dev, slave, RES_QP, qpn);
2117 if (valid_reserved(dev, slave, qpn))
2118 err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
2127 static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2128 u64 in_param, u64 *out_param)
2134 if (op != RES_OP_RESERVE_AND_MAP)
2137 base = get_param_l(&in_param);
2138 order = get_param_h(&in_param);
2139 err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
2141 mlx4_release_resource(dev, slave, RES_MTT, 1 << order, 0);
2142 __mlx4_free_mtt_range(dev, base, order);
2147 static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2153 struct res_mpt *mpt;
2156 case RES_OP_RESERVE:
2157 index = get_param_l(&in_param);
2158 id = index & mpt_mask(dev);
2159 err = get_res(dev, slave, id, RES_MPT, &mpt);
2163 put_res(dev, slave, id, RES_MPT);
2165 err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
2168 mlx4_release_resource(dev, slave, RES_MPT, 1, 0);
2169 __mlx4_mpt_release(dev, index);
2171 case RES_OP_MAP_ICM:
2172 index = get_param_l(&in_param);
2173 id = index & mpt_mask(dev);
2174 err = mr_res_start_move_to(dev, slave, id,
2175 RES_MPT_RESERVED, &mpt);
2179 __mlx4_mpt_free_icm(dev, mpt->key);
2180 res_end_move(dev, slave, RES_MPT, id);
2190 static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2191 u64 in_param, u64 *out_param)
2197 case RES_OP_RESERVE_AND_MAP:
2198 cqn = get_param_l(&in_param);
2199 err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
2203 mlx4_release_resource(dev, slave, RES_CQ, 1, 0);
2204 __mlx4_cq_free_icm(dev, cqn);
2215 static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2216 u64 in_param, u64 *out_param)
2222 case RES_OP_RESERVE_AND_MAP:
2223 srqn = get_param_l(&in_param);
2224 err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
2228 mlx4_release_resource(dev, slave, RES_SRQ, 1, 0);
2229 __mlx4_srq_free_icm(dev, srqn);
2240 static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2241 u64 in_param, u64 *out_param, int in_port)
2247 case RES_OP_RESERVE_AND_MAP:
2248 port = !in_port ? get_param_l(out_param) : in_port;
2249 mac_del_from_slave(dev, slave, in_param, port);
2250 __mlx4_unregister_mac(dev, port, in_param);
2261 static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2262 u64 in_param, u64 *out_param, int port)
2264 struct mlx4_priv *priv = mlx4_priv(dev);
2265 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2269 case RES_OP_RESERVE_AND_MAP:
2270 if (slave_state[slave].old_vlan_api == true)
2274 vlan_del_from_slave(dev, slave, in_param, port);
2275 __mlx4_unregister_vlan(dev, port, in_param);
2285 static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2286 u64 in_param, u64 *out_param, int port)
2290 if (op != RES_OP_RESERVE)
2293 index = get_param_l(&in_param);
2295 __mlx4_counter_free(dev, slave, port, index);
2300 static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
2301 u64 in_param, u64 *out_param)
2306 if (op != RES_OP_RESERVE)
2309 xrcdn = get_param_l(&in_param);
2310 err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
2314 __mlx4_xrcd_free(dev, xrcdn);
2319 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
2320 struct mlx4_vhcr *vhcr,
2321 struct mlx4_cmd_mailbox *inbox,
2322 struct mlx4_cmd_mailbox *outbox,
2323 struct mlx4_cmd_info *cmd)
2326 int alop = vhcr->op_modifier;
2328 switch (vhcr->in_modifier & 0xFF) {
2330 err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
2335 err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
2336 vhcr->in_param, &vhcr->out_param);
2340 err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
2345 err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
2346 vhcr->in_param, &vhcr->out_param);
2350 err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
2351 vhcr->in_param, &vhcr->out_param);
2355 err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
2356 vhcr->in_param, &vhcr->out_param,
2357 (vhcr->in_modifier >> 8) & 0xFF);
2361 err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
2362 vhcr->in_param, &vhcr->out_param,
2363 (vhcr->in_modifier >> 8) & 0xFF);
2367 err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
2368 vhcr->in_param, &vhcr->out_param,
2369 (vhcr->in_modifier >> 8) & 0xFF);
2373 err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
2374 vhcr->in_param, &vhcr->out_param);
2382 /* ugly but other choices are uglier */
2383 static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
2385 return (be32_to_cpu(mpt->flags) >> 9) & 1;
2388 static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
2390 return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
2393 static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
2395 return be32_to_cpu(mpt->mtt_sz);
2398 static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
2400 return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
2403 static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
2405 return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
2408 static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
2410 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
2413 static int mr_is_region(struct mlx4_mpt_entry *mpt)
2415 return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
2418 static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
2420 return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
2423 static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
2425 return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
2428 static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
2430 int page_shift = (qpc->log_page_size & 0x3f) + 12;
2431 int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
2432 int log_sq_sride = qpc->sq_size_stride & 7;
2433 int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
2434 int log_rq_stride = qpc->rq_size_stride & 7;
2435 int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
2436 int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
2437 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
2438 int xrc = (ts == MLX4_QP_ST_XRC) ? 1 : 0;
2443 int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
2445 sq_size = 1 << (log_sq_size + log_sq_sride + 4);
2446 rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
2447 total_mem = sq_size + rq_size;
2449 roundup_pow_of_two((total_mem + (page_offset << 6)) >>
2455 static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
2456 int size, struct res_mtt *mtt)
2458 int res_start = mtt->com.res_id;
2459 int res_size = (1 << mtt->order);
2461 if (start < res_start || start + size > res_start + res_size)
2466 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2467 struct mlx4_vhcr *vhcr,
2468 struct mlx4_cmd_mailbox *inbox,
2469 struct mlx4_cmd_mailbox *outbox,
2470 struct mlx4_cmd_info *cmd)
2473 int index = vhcr->in_modifier;
2474 struct res_mtt *mtt;
2475 struct res_mpt *mpt;
2476 int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
2482 id = index & mpt_mask(dev);
2483 err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
2487 /* Currently disable memory windows since this feature isn't tested yet
2488 * under virtualization.
2490 if (!mr_is_region(inbox->buf)) {
2495 /* Make sure that the PD bits related to the slave id are zeros. */
2496 pd = mr_get_pd(inbox->buf);
2497 pd_slave = (pd >> 17) & 0x7f;
2498 if (pd_slave != 0 && pd_slave != slave) {
2503 if (mr_is_fmr(inbox->buf)) {
2504 /* FMR and Bind Enable are forbidden in slave devices. */
2505 if (mr_is_bind_enabled(inbox->buf)) {
2509 /* FMR and Memory Windows are also forbidden. */
2510 if (!mr_is_region(inbox->buf)) {
2516 phys = mr_phys_mpt(inbox->buf);
2518 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2522 err = check_mtt_range(dev, slave, mtt_base,
2523 mr_get_mtt_size(inbox->buf), mtt);
2530 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2535 atomic_inc(&mtt->ref_count);
2536 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2539 res_end_move(dev, slave, RES_MPT, id);
2544 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2546 res_abort_move(dev, slave, RES_MPT, id);
2551 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
2552 struct mlx4_vhcr *vhcr,
2553 struct mlx4_cmd_mailbox *inbox,
2554 struct mlx4_cmd_mailbox *outbox,
2555 struct mlx4_cmd_info *cmd)
2558 int index = vhcr->in_modifier;
2559 struct res_mpt *mpt;
2562 id = index & mpt_mask(dev);
2563 err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
2567 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2572 atomic_dec(&mpt->mtt->ref_count);
2574 res_end_move(dev, slave, RES_MPT, id);
2578 res_abort_move(dev, slave, RES_MPT, id);
2583 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
2584 struct mlx4_vhcr *vhcr,
2585 struct mlx4_cmd_mailbox *inbox,
2586 struct mlx4_cmd_mailbox *outbox,
2587 struct mlx4_cmd_info *cmd)
2590 int index = vhcr->in_modifier;
2591 struct res_mpt *mpt;
2594 id = index & mpt_mask(dev);
2595 err = get_res(dev, slave, id, RES_MPT, &mpt);
2599 if (mpt->com.from_state != RES_MPT_HW) {
2604 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2607 put_res(dev, slave, id, RES_MPT);
2611 static int qp_get_rcqn(struct mlx4_qp_context *qpc)
2613 return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
2616 static int qp_get_scqn(struct mlx4_qp_context *qpc)
2618 return be32_to_cpu(qpc->cqn_send) & 0xffffff;
2621 static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
2623 return be32_to_cpu(qpc->srqn) & 0x1ffffff;
2626 static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
2627 struct mlx4_qp_context *context)
2629 u32 qpn = vhcr->in_modifier & 0xffffff;
2632 if (mlx4_get_parav_qkey(dev, qpn, &qkey))
2635 /* adjust qkey in qp context */
2636 context->qkey = cpu_to_be32(qkey);
2639 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
2640 struct mlx4_vhcr *vhcr,
2641 struct mlx4_cmd_mailbox *inbox,
2642 struct mlx4_cmd_mailbox *outbox,
2643 struct mlx4_cmd_info *cmd)
2646 int qpn = vhcr->in_modifier & 0x7fffff;
2647 struct res_mtt *mtt;
2649 struct mlx4_qp_context *qpc = inbox->buf + 8;
2650 int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
2651 int mtt_size = qp_get_mtt_size(qpc);
2654 int rcqn = qp_get_rcqn(qpc);
2655 int scqn = qp_get_scqn(qpc);
2656 u32 srqn = qp_get_srqn(qpc) & 0xffffff;
2657 int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
2658 struct res_srq *srq;
2659 int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
2661 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
2664 qp->local_qpn = local_qpn;
2665 qp->sched_queue = 0;
2667 qp->vlan_control = 0;
2669 qp->pri_path_fl = 0;
2672 qp->qpc_flags = be32_to_cpu(qpc->flags);
2674 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2678 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2682 err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
2687 err = get_res(dev, slave, scqn, RES_CQ, &scq);
2694 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
2699 adjust_proxy_tun_qkey(dev, vhcr, qpc);
2700 update_pkey_index(dev, slave, inbox);
2701 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2704 atomic_inc(&mtt->ref_count);
2706 atomic_inc(&rcq->ref_count);
2708 atomic_inc(&scq->ref_count);
2712 put_res(dev, slave, scqn, RES_CQ);
2715 atomic_inc(&srq->ref_count);
2716 put_res(dev, slave, srqn, RES_SRQ);
2719 put_res(dev, slave, rcqn, RES_CQ);
2720 put_res(dev, slave, mtt_base, RES_MTT);
2721 res_end_move(dev, slave, RES_QP, qpn);
2727 put_res(dev, slave, srqn, RES_SRQ);
2730 put_res(dev, slave, scqn, RES_CQ);
2732 put_res(dev, slave, rcqn, RES_CQ);
2734 put_res(dev, slave, mtt_base, RES_MTT);
2736 res_abort_move(dev, slave, RES_QP, qpn);
2741 static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
2743 return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
2746 static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
2748 int log_eq_size = eqc->log_eq_size & 0x1f;
2749 int page_shift = (eqc->log_page_size & 0x3f) + 12;
2751 if (log_eq_size + 5 < page_shift)
2754 return 1 << (log_eq_size + 5 - page_shift);
2757 static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
2759 return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
2762 static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
2764 int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
2765 int page_shift = (cqc->log_page_size & 0x3f) + 12;
2767 if (log_cq_size + 5 < page_shift)
2770 return 1 << (log_cq_size + 5 - page_shift);
2773 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
2774 struct mlx4_vhcr *vhcr,
2775 struct mlx4_cmd_mailbox *inbox,
2776 struct mlx4_cmd_mailbox *outbox,
2777 struct mlx4_cmd_info *cmd)
2780 int eqn = vhcr->in_modifier;
2781 int res_id = (slave << 8) | eqn;
2782 struct mlx4_eq_context *eqc = inbox->buf;
2783 int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
2784 int mtt_size = eq_get_mtt_size(eqc);
2786 struct res_mtt *mtt;
2788 err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
2791 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
2795 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
2799 err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
2803 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2807 atomic_inc(&mtt->ref_count);
2809 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2810 res_end_move(dev, slave, RES_EQ, res_id);
2814 put_res(dev, slave, mtt->com.res_id, RES_MTT);
2816 res_abort_move(dev, slave, RES_EQ, res_id);
2818 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
2822 static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
2823 int len, struct res_mtt **res)
2825 struct mlx4_priv *priv = mlx4_priv(dev);
2826 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
2827 struct res_mtt *mtt;
2830 spin_lock_irq(mlx4_tlock(dev));
2831 list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
2833 if (!check_mtt_range(dev, slave, start, len, mtt)) {
2835 mtt->com.from_state = mtt->com.state;
2836 mtt->com.state = RES_MTT_BUSY;
2841 spin_unlock_irq(mlx4_tlock(dev));
2846 static int verify_qp_parameters(struct mlx4_dev *dev,
2847 struct mlx4_cmd_mailbox *inbox,
2848 enum qp_transition transition, u8 slave)
2851 struct mlx4_qp_context *qp_ctx;
2852 enum mlx4_qp_optpar optpar;
2856 qp_ctx = inbox->buf + 8;
2857 qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
2858 optpar = be32_to_cpu(*(__be32 *) inbox->buf);
2863 switch (transition) {
2864 case QP_TRANS_INIT2RTR:
2865 case QP_TRANS_RTR2RTS:
2866 case QP_TRANS_RTS2RTS:
2867 case QP_TRANS_SQD2SQD:
2868 case QP_TRANS_SQD2RTS:
2869 if (slave != mlx4_master_func_num(dev))
2870 if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH) {
2871 port = (qp_ctx->pri_path.sched_queue >> 6 & 1) + 1;
2872 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
2873 num_gids = mlx4_get_slave_num_gids(dev, slave);
2876 if (qp_ctx->pri_path.mgid_index >= num_gids)
2879 if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH) {
2880 port = (qp_ctx->alt_path.sched_queue >> 6 & 1) + 1;
2881 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB)
2882 num_gids = mlx4_get_slave_num_gids(dev, slave);
2885 if (qp_ctx->alt_path.mgid_index >= num_gids)
2901 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
2902 struct mlx4_vhcr *vhcr,
2903 struct mlx4_cmd_mailbox *inbox,
2904 struct mlx4_cmd_mailbox *outbox,
2905 struct mlx4_cmd_info *cmd)
2907 struct mlx4_mtt mtt;
2908 __be64 *page_list = inbox->buf;
2909 u64 *pg_list = (u64 *)page_list;
2911 struct res_mtt *rmtt = NULL;
2912 int start = be64_to_cpu(page_list[0]);
2913 int npages = vhcr->in_modifier;
2916 err = get_containing_mtt(dev, slave, start, npages, &rmtt);
2920 /* Call the SW implementation of write_mtt:
2921 * - Prepare a dummy mtt struct
2922 * - Translate inbox contents to simple addresses in host endianness */
2923 mtt.offset = 0; /* TBD this is broken but I don't handle it since
2924 we don't really use it */
2927 for (i = 0; i < npages; ++i)
2928 pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
2930 err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
2931 ((u64 *)page_list + 2));
2934 put_res(dev, slave, rmtt->com.res_id, RES_MTT);
2939 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
2940 struct mlx4_vhcr *vhcr,
2941 struct mlx4_cmd_mailbox *inbox,
2942 struct mlx4_cmd_mailbox *outbox,
2943 struct mlx4_cmd_info *cmd)
2945 int eqn = vhcr->in_modifier;
2946 int res_id = eqn | (slave << 8);
2950 err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
2954 err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
2958 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
2962 atomic_dec(&eq->mtt->ref_count);
2963 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
2964 res_end_move(dev, slave, RES_EQ, res_id);
2965 rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
2970 put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
2972 res_abort_move(dev, slave, RES_EQ, res_id);
2977 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
2979 struct mlx4_priv *priv = mlx4_priv(dev);
2980 struct mlx4_slave_event_eq_info *event_eq;
2981 struct mlx4_cmd_mailbox *mailbox;
2982 u32 in_modifier = 0;
2987 if (!priv->mfunc.master.slave_state)
2990 /* check for slave valid, slave not PF, and slave active */
2991 if (slave < 0 || slave >= dev->num_slaves ||
2992 slave == dev->caps.function ||
2993 !priv->mfunc.master.slave_state[slave].active)
2996 event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
2998 /* Create the event only if the slave is registered */
2999 if (event_eq->eqn < 0)
3002 mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3003 res_id = (slave << 8) | event_eq->eqn;
3004 err = get_res(dev, slave, res_id, RES_EQ, &req);
3008 if (req->com.from_state != RES_EQ_HW) {
3013 mailbox = mlx4_alloc_cmd_mailbox(dev);
3014 if (IS_ERR(mailbox)) {
3015 err = PTR_ERR(mailbox);
3019 if (eqe->type == MLX4_EVENT_TYPE_CMD) {
3021 eqe->event.cmd.token = cpu_to_be16(event_eq->token);
3024 memcpy(mailbox->buf, (u8 *) eqe, 28);
3026 in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
3028 err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
3029 MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
3032 put_res(dev, slave, res_id, RES_EQ);
3033 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3034 mlx4_free_cmd_mailbox(dev, mailbox);
3038 put_res(dev, slave, res_id, RES_EQ);
3041 mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
3045 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
3046 struct mlx4_vhcr *vhcr,
3047 struct mlx4_cmd_mailbox *inbox,
3048 struct mlx4_cmd_mailbox *outbox,
3049 struct mlx4_cmd_info *cmd)
3051 int eqn = vhcr->in_modifier;
3052 int res_id = eqn | (slave << 8);
3056 err = get_res(dev, slave, res_id, RES_EQ, &eq);
3060 if (eq->com.from_state != RES_EQ_HW) {
3065 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3068 put_res(dev, slave, res_id, RES_EQ);
3072 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3073 struct mlx4_vhcr *vhcr,
3074 struct mlx4_cmd_mailbox *inbox,
3075 struct mlx4_cmd_mailbox *outbox,
3076 struct mlx4_cmd_info *cmd)
3079 int cqn = vhcr->in_modifier;
3080 struct mlx4_cq_context *cqc = inbox->buf;
3081 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
3083 struct res_mtt *mtt;
3085 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
3088 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3091 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3094 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3097 atomic_inc(&mtt->ref_count);
3099 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3100 res_end_move(dev, slave, RES_CQ, cqn);
3104 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3106 res_abort_move(dev, slave, RES_CQ, cqn);
3110 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
3111 struct mlx4_vhcr *vhcr,
3112 struct mlx4_cmd_mailbox *inbox,
3113 struct mlx4_cmd_mailbox *outbox,
3114 struct mlx4_cmd_info *cmd)
3117 int cqn = vhcr->in_modifier;
3120 err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
3123 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3126 atomic_dec(&cq->mtt->ref_count);
3127 res_end_move(dev, slave, RES_CQ, cqn);
3131 res_abort_move(dev, slave, RES_CQ, cqn);
3135 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3136 struct mlx4_vhcr *vhcr,
3137 struct mlx4_cmd_mailbox *inbox,
3138 struct mlx4_cmd_mailbox *outbox,
3139 struct mlx4_cmd_info *cmd)
3141 int cqn = vhcr->in_modifier;
3145 err = get_res(dev, slave, cqn, RES_CQ, &cq);
3149 if (cq->com.from_state != RES_CQ_HW)
3152 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3154 put_res(dev, slave, cqn, RES_CQ);
3159 static int handle_resize(struct mlx4_dev *dev, int slave,
3160 struct mlx4_vhcr *vhcr,
3161 struct mlx4_cmd_mailbox *inbox,
3162 struct mlx4_cmd_mailbox *outbox,
3163 struct mlx4_cmd_info *cmd,
3167 struct res_mtt *orig_mtt;
3168 struct res_mtt *mtt;
3169 struct mlx4_cq_context *cqc = inbox->buf;
3170 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
3172 err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
3176 if (orig_mtt != cq->mtt) {
3181 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3185 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
3188 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3191 atomic_dec(&orig_mtt->ref_count);
3192 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3193 atomic_inc(&mtt->ref_count);
3195 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3199 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3201 put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
3207 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
3208 struct mlx4_vhcr *vhcr,
3209 struct mlx4_cmd_mailbox *inbox,
3210 struct mlx4_cmd_mailbox *outbox,
3211 struct mlx4_cmd_info *cmd)
3213 int cqn = vhcr->in_modifier;
3217 err = get_res(dev, slave, cqn, RES_CQ, &cq);
3221 if (cq->com.from_state != RES_CQ_HW)
3224 if (vhcr->op_modifier == 0) {
3225 err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
3229 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3231 put_res(dev, slave, cqn, RES_CQ);
3236 static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
3238 int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
3239 int log_rq_stride = srqc->logstride & 7;
3240 int page_shift = (srqc->log_page_size & 0x3f) + 12;
3242 if (log_srq_size + log_rq_stride + 4 < page_shift)
3245 return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
3248 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3249 struct mlx4_vhcr *vhcr,
3250 struct mlx4_cmd_mailbox *inbox,
3251 struct mlx4_cmd_mailbox *outbox,
3252 struct mlx4_cmd_info *cmd)
3255 int srqn = vhcr->in_modifier;
3256 struct res_mtt *mtt;
3257 struct res_srq *srq;
3258 struct mlx4_srq_context *srqc = inbox->buf;
3259 int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
3261 if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
3264 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
3267 err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
3270 err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
3275 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3279 atomic_inc(&mtt->ref_count);
3281 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3282 res_end_move(dev, slave, RES_SRQ, srqn);
3286 put_res(dev, slave, mtt->com.res_id, RES_MTT);
3288 res_abort_move(dev, slave, RES_SRQ, srqn);
3293 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3294 struct mlx4_vhcr *vhcr,
3295 struct mlx4_cmd_mailbox *inbox,
3296 struct mlx4_cmd_mailbox *outbox,
3297 struct mlx4_cmd_info *cmd)
3300 int srqn = vhcr->in_modifier;
3301 struct res_srq *srq;
3303 err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
3306 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3309 atomic_dec(&srq->mtt->ref_count);
3311 atomic_dec(&srq->cq->ref_count);
3312 res_end_move(dev, slave, RES_SRQ, srqn);
3317 res_abort_move(dev, slave, RES_SRQ, srqn);
3322 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3323 struct mlx4_vhcr *vhcr,
3324 struct mlx4_cmd_mailbox *inbox,
3325 struct mlx4_cmd_mailbox *outbox,
3326 struct mlx4_cmd_info *cmd)
3329 int srqn = vhcr->in_modifier;
3330 struct res_srq *srq;
3332 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3335 if (srq->com.from_state != RES_SRQ_HW) {
3339 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3341 put_res(dev, slave, srqn, RES_SRQ);
3345 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
3346 struct mlx4_vhcr *vhcr,
3347 struct mlx4_cmd_mailbox *inbox,
3348 struct mlx4_cmd_mailbox *outbox,
3349 struct mlx4_cmd_info *cmd)
3352 int srqn = vhcr->in_modifier;
3353 struct res_srq *srq;
3355 err = get_res(dev, slave, srqn, RES_SRQ, &srq);
3359 if (srq->com.from_state != RES_SRQ_HW) {
3364 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3366 put_res(dev, slave, srqn, RES_SRQ);
3370 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
3371 struct mlx4_vhcr *vhcr,
3372 struct mlx4_cmd_mailbox *inbox,
3373 struct mlx4_cmd_mailbox *outbox,
3374 struct mlx4_cmd_info *cmd)
3377 int qpn = vhcr->in_modifier & 0x7fffff;
3380 err = get_res(dev, slave, qpn, RES_QP, &qp);
3383 if (qp->com.from_state != RES_QP_HW) {
3388 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3390 put_res(dev, slave, qpn, RES_QP);
3394 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
3395 struct mlx4_vhcr *vhcr,
3396 struct mlx4_cmd_mailbox *inbox,
3397 struct mlx4_cmd_mailbox *outbox,
3398 struct mlx4_cmd_info *cmd)
3400 struct mlx4_qp_context *context = inbox->buf + 8;
3401 adjust_proxy_tun_qkey(dev, vhcr, context);
3402 update_pkey_index(dev, slave, inbox);
3403 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3406 static int roce_verify_mac(struct mlx4_dev *dev, int slave,
3407 struct mlx4_qp_context *qpc,
3408 struct mlx4_cmd_mailbox *inbox)
3412 u32 ts = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
3413 u8 sched = *(u8 *)(inbox->buf + 64);
3416 port = (sched >> 6 & 1) + 1;
3417 if (mlx4_is_eth(dev, port) && (ts != MLX4_QP_ST_MLX)) {
3418 smac_ix = qpc->pri_path.grh_mylmc & 0x7f;
3419 if (mac_find_smac_ix_in_slave(dev, slave, port, smac_ix, &mac))
3425 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
3426 struct mlx4_vhcr *vhcr,
3427 struct mlx4_cmd_mailbox *inbox,
3428 struct mlx4_cmd_mailbox *outbox,
3429 struct mlx4_cmd_info *cmd)
3432 struct mlx4_qp_context *qpc = inbox->buf + 8;
3433 int qpn = vhcr->in_modifier & 0x7fffff;
3435 u8 orig_sched_queue;
3436 __be32 orig_param3 = qpc->param3;
3437 u8 orig_vlan_control = qpc->pri_path.vlan_control;
3438 u8 orig_fvl_rx = qpc->pri_path.fvl_rx;
3439 u8 orig_pri_path_fl = qpc->pri_path.fl;
3440 u8 orig_vlan_index = qpc->pri_path.vlan_index;
3441 u8 orig_feup = qpc->pri_path.feup;
3443 err = verify_qp_parameters(dev, inbox, QP_TRANS_INIT2RTR, slave);
3447 if (roce_verify_mac(dev, slave, qpc, inbox))
3450 update_pkey_index(dev, slave, inbox);
3451 update_gid(dev, inbox, (u8)slave);
3452 adjust_proxy_tun_qkey(dev, vhcr, qpc);
3453 orig_sched_queue = qpc->pri_path.sched_queue;
3455 err = get_res(dev, slave, qpn, RES_QP, &qp);
3458 if (qp->com.from_state != RES_QP_HW) {
3463 /* do not modify vport QP params for RSS QPs */
3464 if (!(qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET))) {
3465 err = update_vport_qp_param(dev, inbox, slave, qpn);
3470 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3472 /* if no error, save sched queue value passed in by VF. This is
3473 * essentially the QOS value provided by the VF. This will be useful
3474 * if we allow dynamic changes from VST back to VGT
3477 qp->sched_queue = orig_sched_queue;
3478 qp->param3 = orig_param3;
3479 qp->vlan_control = orig_vlan_control;
3480 qp->fvl_rx = orig_fvl_rx;
3481 qp->pri_path_fl = orig_pri_path_fl;
3482 qp->vlan_index = orig_vlan_index;
3483 qp->feup = orig_feup;
3485 put_res(dev, slave, qpn, RES_QP);
3489 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3490 struct mlx4_vhcr *vhcr,
3491 struct mlx4_cmd_mailbox *inbox,
3492 struct mlx4_cmd_mailbox *outbox,
3493 struct mlx4_cmd_info *cmd)
3496 struct mlx4_qp_context *context = inbox->buf + 8;
3498 err = verify_qp_parameters(dev, inbox, QP_TRANS_RTR2RTS, slave);
3502 update_pkey_index(dev, slave, inbox);
3503 update_gid(dev, inbox, (u8)slave);
3504 adjust_proxy_tun_qkey(dev, vhcr, context);
3505 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3508 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3509 struct mlx4_vhcr *vhcr,
3510 struct mlx4_cmd_mailbox *inbox,
3511 struct mlx4_cmd_mailbox *outbox,
3512 struct mlx4_cmd_info *cmd)
3515 struct mlx4_qp_context *context = inbox->buf + 8;
3517 err = verify_qp_parameters(dev, inbox, QP_TRANS_RTS2RTS, slave);
3521 update_pkey_index(dev, slave, inbox);
3522 update_gid(dev, inbox, (u8)slave);
3523 adjust_proxy_tun_qkey(dev, vhcr, context);
3524 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3528 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3529 struct mlx4_vhcr *vhcr,
3530 struct mlx4_cmd_mailbox *inbox,
3531 struct mlx4_cmd_mailbox *outbox,
3532 struct mlx4_cmd_info *cmd)
3534 struct mlx4_qp_context *context = inbox->buf + 8;
3535 adjust_proxy_tun_qkey(dev, vhcr, context);
3536 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3539 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
3540 struct mlx4_vhcr *vhcr,
3541 struct mlx4_cmd_mailbox *inbox,
3542 struct mlx4_cmd_mailbox *outbox,
3543 struct mlx4_cmd_info *cmd)
3546 struct mlx4_qp_context *context = inbox->buf + 8;
3548 err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2SQD, slave);
3552 adjust_proxy_tun_qkey(dev, vhcr, context);
3553 update_gid(dev, inbox, (u8)slave);
3554 update_pkey_index(dev, slave, inbox);
3555 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3558 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
3559 struct mlx4_vhcr *vhcr,
3560 struct mlx4_cmd_mailbox *inbox,
3561 struct mlx4_cmd_mailbox *outbox,
3562 struct mlx4_cmd_info *cmd)
3565 struct mlx4_qp_context *context = inbox->buf + 8;
3567 err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2RTS, slave);
3571 adjust_proxy_tun_qkey(dev, vhcr, context);
3572 update_gid(dev, inbox, (u8)slave);
3573 update_pkey_index(dev, slave, inbox);
3574 return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3577 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
3578 struct mlx4_vhcr *vhcr,
3579 struct mlx4_cmd_mailbox *inbox,
3580 struct mlx4_cmd_mailbox *outbox,
3581 struct mlx4_cmd_info *cmd)
3584 int qpn = vhcr->in_modifier & 0x7fffff;
3587 err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
3590 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3594 atomic_dec(&qp->mtt->ref_count);
3595 atomic_dec(&qp->rcq->ref_count);
3596 atomic_dec(&qp->scq->ref_count);
3598 atomic_dec(&qp->srq->ref_count);
3599 res_end_move(dev, slave, RES_QP, qpn);
3603 res_abort_move(dev, slave, RES_QP, qpn);
3608 static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
3609 struct res_qp *rqp, u8 *gid)
3611 struct res_gid *res;
3613 list_for_each_entry(res, &rqp->mcg_list, list) {
3614 if (!memcmp(res->gid, gid, 16))
3620 static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
3621 u8 *gid, enum mlx4_protocol prot,
3622 enum mlx4_steer_type steer, u64 reg_id)
3624 struct res_gid *res;
3627 res = kzalloc(sizeof *res, GFP_KERNEL);
3631 spin_lock_irq(&rqp->mcg_spl);
3632 if (find_gid(dev, slave, rqp, gid)) {
3636 memcpy(res->gid, gid, 16);
3639 res->reg_id = reg_id;
3640 list_add_tail(&res->list, &rqp->mcg_list);
3643 spin_unlock_irq(&rqp->mcg_spl);
3648 static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
3649 u8 *gid, enum mlx4_protocol prot,
3650 enum mlx4_steer_type steer, u64 *reg_id)
3652 struct res_gid *res;
3655 spin_lock_irq(&rqp->mcg_spl);
3656 res = find_gid(dev, slave, rqp, gid);
3657 if (!res || res->prot != prot || res->steer != steer)
3660 *reg_id = res->reg_id;
3661 list_del(&res->list);
3665 spin_unlock_irq(&rqp->mcg_spl);
3670 static int qp_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
3671 int block_loopback, enum mlx4_protocol prot,
3672 enum mlx4_steer_type type, u64 *reg_id)
3674 switch (dev->caps.steering_mode) {
3675 case MLX4_STEERING_MODE_DEVICE_MANAGED:
3676 return mlx4_trans_to_dmfs_attach(dev, qp, gid, gid[5],
3677 block_loopback, prot,
3679 case MLX4_STEERING_MODE_B0:
3680 return mlx4_qp_attach_common(dev, qp, gid,
3681 block_loopback, prot, type);
3687 static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
3688 enum mlx4_protocol prot, enum mlx4_steer_type type,
3691 switch (dev->caps.steering_mode) {
3692 case MLX4_STEERING_MODE_DEVICE_MANAGED:
3693 return mlx4_flow_detach(dev, reg_id);
3694 case MLX4_STEERING_MODE_B0:
3695 return mlx4_qp_detach_common(dev, qp, gid, prot, type);
3701 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
3702 struct mlx4_vhcr *vhcr,
3703 struct mlx4_cmd_mailbox *inbox,
3704 struct mlx4_cmd_mailbox *outbox,
3705 struct mlx4_cmd_info *cmd)
3707 struct mlx4_qp qp; /* dummy for calling attach/detach */
3708 u8 *gid = inbox->buf;
3709 enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
3714 int attach = vhcr->op_modifier;
3715 int block_loopback = vhcr->in_modifier >> 31;
3716 u8 steer_type_mask = 2;
3717 enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
3719 qpn = vhcr->in_modifier & 0xffffff;
3720 err = get_res(dev, slave, qpn, RES_QP, &rqp);
3726 err = qp_attach(dev, &qp, gid, block_loopback, prot,
3729 pr_err("Fail to attach rule to qp 0x%x\n", qpn);
3732 err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
3736 err = rem_mcg_res(dev, slave, rqp, gid, prot, type, ®_id);
3740 err = qp_detach(dev, &qp, gid, prot, type, reg_id);
3742 pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
3743 qpn, (unsigned long long)reg_id);
3745 put_res(dev, slave, qpn, RES_QP);
3749 qp_detach(dev, &qp, gid, prot, type, reg_id);
3751 put_res(dev, slave, qpn, RES_QP);
3756 * MAC validation for Flow Steering rules.
3757 * VF can attach rules only with a mac address which is assigned to it.
3759 static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
3760 struct list_head *rlist)
3762 struct mac_res *res, *tmp;
3765 /* make sure it isn't multicast or broadcast mac*/
3766 if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
3767 !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
3768 list_for_each_entry_safe(res, tmp, rlist, list) {
3769 be_mac = cpu_to_be64(res->mac << 16);
3770 if (!memcmp(&be_mac, eth_header->eth.dst_mac, ETH_ALEN))
3773 pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
3774 eth_header->eth.dst_mac, slave);
3781 * In case of missing eth header, append eth header with a MAC address
3782 * assigned to the VF.
3784 static int add_eth_header(struct mlx4_dev *dev, int slave,
3785 struct mlx4_cmd_mailbox *inbox,
3786 struct list_head *rlist, int header_id)
3788 struct mac_res *res, *tmp;
3790 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
3791 struct mlx4_net_trans_rule_hw_eth *eth_header;
3792 struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
3793 struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
3795 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
3797 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
3799 eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
3801 /* Clear a space in the inbox for eth header */
3802 switch (header_id) {
3803 case MLX4_NET_TRANS_RULE_ID_IPV4:
3805 (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
3806 memmove(ip_header, eth_header,
3807 sizeof(*ip_header) + sizeof(*l4_header));
3809 case MLX4_NET_TRANS_RULE_ID_TCP:
3810 case MLX4_NET_TRANS_RULE_ID_UDP:
3811 l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
3813 memmove(l4_header, eth_header, sizeof(*l4_header));
3818 list_for_each_entry_safe(res, tmp, rlist, list) {
3819 if (port == res->port) {
3820 be_mac = cpu_to_be64(res->mac << 16);
3825 pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d .\n",
3830 memset(eth_header, 0, sizeof(*eth_header));
3831 eth_header->size = sizeof(*eth_header) >> 2;
3832 eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
3833 memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
3834 memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
3840 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
3841 struct mlx4_vhcr *vhcr,
3842 struct mlx4_cmd_mailbox *inbox,
3843 struct mlx4_cmd_mailbox *outbox,
3844 struct mlx4_cmd_info *cmd)
3847 struct mlx4_priv *priv = mlx4_priv(dev);
3848 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
3849 struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
3853 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
3854 struct _rule_hw *rule_header;
3857 if (dev->caps.steering_mode !=
3858 MLX4_STEERING_MODE_DEVICE_MANAGED)
3861 ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
3862 qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
3863 err = get_res(dev, slave, qpn, RES_QP, &rqp);
3865 pr_err("Steering rule with qpn 0x%x rejected.\n", qpn);
3868 rule_header = (struct _rule_hw *)(ctrl + 1);
3869 header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
3871 switch (header_id) {
3872 case MLX4_NET_TRANS_RULE_ID_ETH:
3873 if (validate_eth_header_mac(slave, rule_header, rlist)) {
3878 case MLX4_NET_TRANS_RULE_ID_IB:
3880 case MLX4_NET_TRANS_RULE_ID_IPV4:
3881 case MLX4_NET_TRANS_RULE_ID_TCP:
3882 case MLX4_NET_TRANS_RULE_ID_UDP:
3883 pr_warn("Can't attach FS rule without L2 headers, adding L2 header.\n");
3884 if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
3888 vhcr->in_modifier +=
3889 sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
3892 pr_err("Corrupted mailbox.\n");
3897 err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
3898 vhcr->in_modifier, 0,
3899 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
3904 err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
3906 mlx4_err(dev, "Fail to add flow steering resources.\n ");
3908 mlx4_cmd(dev, vhcr->out_param, 0, 0,
3909 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
3913 atomic_inc(&rqp->ref_count);
3915 put_res(dev, slave, qpn, RES_QP);
3919 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
3920 struct mlx4_vhcr *vhcr,
3921 struct mlx4_cmd_mailbox *inbox,
3922 struct mlx4_cmd_mailbox *outbox,
3923 struct mlx4_cmd_info *cmd)
3927 struct res_fs_rule *rrule;
3929 if (dev->caps.steering_mode !=
3930 MLX4_STEERING_MODE_DEVICE_MANAGED)
3933 err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
3936 /* Release the rule form busy state before removal */
3937 put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
3938 err = get_res(dev, slave, rrule->qpn, RES_QP, &rqp);
3942 err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
3943 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
3946 err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE,
3948 atomic_dec(&rqp->ref_count);
3951 mlx4_err(dev, "Fail to remove flow steering resources.\n ");
3957 put_res(dev, slave, rrule->qpn, RES_QP);
3962 BUSY_MAX_RETRIES = 10
3965 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
3966 struct mlx4_vhcr *vhcr,
3967 struct mlx4_cmd_mailbox *inbox,
3968 struct mlx4_cmd_mailbox *outbox,
3969 struct mlx4_cmd_info *cmd)
3973 err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
3978 static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
3980 struct res_gid *rgid;
3981 struct res_gid *tmp;
3982 struct mlx4_qp qp; /* dummy for calling attach/detach */
3984 list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
3985 switch (dev->caps.steering_mode) {
3986 case MLX4_STEERING_MODE_DEVICE_MANAGED:
3987 mlx4_flow_detach(dev, rgid->reg_id);
3989 case MLX4_STEERING_MODE_B0:
3990 qp.qpn = rqp->local_qpn;
3991 (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
3992 rgid->prot, rgid->steer);
3995 list_del(&rgid->list);
4000 static int _move_all_busy(struct mlx4_dev *dev, int slave,
4001 enum mlx4_resource type, int print)
4003 struct mlx4_priv *priv = mlx4_priv(dev);
4004 struct mlx4_resource_tracker *tracker =
4005 &priv->mfunc.master.res_tracker;
4006 struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
4007 struct res_common *r;
4008 struct res_common *tmp;
4012 spin_lock_irq(mlx4_tlock(dev));
4013 list_for_each_entry_safe(r, tmp, rlist, list) {
4014 if (r->owner == slave) {
4016 if (r->state == RES_ANY_BUSY) {
4019 "%s id 0x%llx is busy\n",
4021 (unsigned long long)r->res_id);
4024 r->from_state = r->state;
4025 r->state = RES_ANY_BUSY;
4031 spin_unlock_irq(mlx4_tlock(dev));
4036 static int move_all_busy(struct mlx4_dev *dev, int slave,
4037 enum mlx4_resource type)
4039 unsigned long begin;
4044 busy = _move_all_busy(dev, slave, type, 0);
4045 if (time_after(jiffies, begin + 5 * HZ))
4052 busy = _move_all_busy(dev, slave, type, 1);
4056 static void rem_slave_qps(struct mlx4_dev *dev, int slave)
4058 struct mlx4_priv *priv = mlx4_priv(dev);
4059 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4060 struct list_head *qp_list =
4061 &tracker->slave_list[slave].res_list[RES_QP];
4069 err = move_all_busy(dev, slave, RES_QP);
4071 mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
4072 "for slave %d\n", slave);
4074 spin_lock_irq(mlx4_tlock(dev));
4075 list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
4076 spin_unlock_irq(mlx4_tlock(dev));
4077 if (qp->com.owner == slave) {
4078 qpn = qp->com.res_id;
4079 detach_qp(dev, slave, qp);
4080 state = qp->com.from_state;
4081 while (state != 0) {
4083 case RES_QP_RESERVED:
4084 spin_lock_irq(mlx4_tlock(dev));
4085 rb_erase(&qp->com.node,
4086 &tracker->res_tree[RES_QP]);
4087 list_del(&qp->com.list);
4088 spin_unlock_irq(mlx4_tlock(dev));
4089 if (!valid_reserved(dev, slave, qpn)) {
4090 __mlx4_qp_release_range(dev, qpn, 1);
4091 mlx4_release_resource(dev, slave,
4098 if (!valid_reserved(dev, slave, qpn))
4099 __mlx4_qp_free_icm(dev, qpn);
4100 state = RES_QP_RESERVED;
4104 err = mlx4_cmd(dev, in_param,
4107 MLX4_CMD_TIME_CLASS_A,
4110 mlx4_dbg(dev, "rem_slave_qps: failed"
4111 " to move slave %d qpn %d to"
4114 atomic_dec(&qp->rcq->ref_count);
4115 atomic_dec(&qp->scq->ref_count);
4116 atomic_dec(&qp->mtt->ref_count);
4118 atomic_dec(&qp->srq->ref_count);
4119 state = RES_QP_MAPPED;
4126 spin_lock_irq(mlx4_tlock(dev));
4128 spin_unlock_irq(mlx4_tlock(dev));
4131 static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
4133 struct mlx4_priv *priv = mlx4_priv(dev);
4134 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4135 struct list_head *srq_list =
4136 &tracker->slave_list[slave].res_list[RES_SRQ];
4137 struct res_srq *srq;
4138 struct res_srq *tmp;
4145 err = move_all_busy(dev, slave, RES_SRQ);
4147 mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
4148 "busy for slave %d\n", slave);
4150 spin_lock_irq(mlx4_tlock(dev));
4151 list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
4152 spin_unlock_irq(mlx4_tlock(dev));
4153 if (srq->com.owner == slave) {
4154 srqn = srq->com.res_id;
4155 state = srq->com.from_state;
4156 while (state != 0) {
4158 case RES_SRQ_ALLOCATED:
4159 __mlx4_srq_free_icm(dev, srqn);
4160 spin_lock_irq(mlx4_tlock(dev));
4161 rb_erase(&srq->com.node,
4162 &tracker->res_tree[RES_SRQ]);
4163 list_del(&srq->com.list);
4164 spin_unlock_irq(mlx4_tlock(dev));
4165 mlx4_release_resource(dev, slave,
4173 err = mlx4_cmd(dev, in_param, srqn, 1,
4175 MLX4_CMD_TIME_CLASS_A,
4178 mlx4_dbg(dev, "rem_slave_srqs: failed"
4179 " to move slave %d srq %d to"
4183 atomic_dec(&srq->mtt->ref_count);
4185 atomic_dec(&srq->cq->ref_count);
4186 state = RES_SRQ_ALLOCATED;
4194 spin_lock_irq(mlx4_tlock(dev));
4196 spin_unlock_irq(mlx4_tlock(dev));
4199 static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
4201 struct mlx4_priv *priv = mlx4_priv(dev);
4202 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4203 struct list_head *cq_list =
4204 &tracker->slave_list[slave].res_list[RES_CQ];
4213 err = move_all_busy(dev, slave, RES_CQ);
4215 mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
4216 "busy for slave %d\n", slave);
4218 spin_lock_irq(mlx4_tlock(dev));
4219 list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
4220 spin_unlock_irq(mlx4_tlock(dev));
4221 if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
4222 cqn = cq->com.res_id;
4223 state = cq->com.from_state;
4224 while (state != 0) {
4226 case RES_CQ_ALLOCATED:
4227 __mlx4_cq_free_icm(dev, cqn);
4228 spin_lock_irq(mlx4_tlock(dev));
4229 rb_erase(&cq->com.node,
4230 &tracker->res_tree[RES_CQ]);
4231 list_del(&cq->com.list);
4232 spin_unlock_irq(mlx4_tlock(dev));
4233 mlx4_release_resource(dev, slave,
4241 err = mlx4_cmd(dev, in_param, cqn, 1,
4243 MLX4_CMD_TIME_CLASS_A,
4246 mlx4_dbg(dev, "rem_slave_cqs: failed"
4247 " to move slave %d cq %d to"
4250 atomic_dec(&cq->mtt->ref_count);
4251 state = RES_CQ_ALLOCATED;
4259 spin_lock_irq(mlx4_tlock(dev));
4261 spin_unlock_irq(mlx4_tlock(dev));
4264 static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
4266 struct mlx4_priv *priv = mlx4_priv(dev);
4267 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4268 struct list_head *mpt_list =
4269 &tracker->slave_list[slave].res_list[RES_MPT];
4270 struct res_mpt *mpt;
4271 struct res_mpt *tmp;
4278 err = move_all_busy(dev, slave, RES_MPT);
4280 mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
4281 "busy for slave %d\n", slave);
4283 spin_lock_irq(mlx4_tlock(dev));
4284 list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
4285 spin_unlock_irq(mlx4_tlock(dev));
4286 if (mpt->com.owner == slave) {
4287 mptn = mpt->com.res_id;
4288 state = mpt->com.from_state;
4289 while (state != 0) {
4291 case RES_MPT_RESERVED:
4292 __mlx4_mpt_release(dev, mpt->key);
4293 spin_lock_irq(mlx4_tlock(dev));
4294 rb_erase(&mpt->com.node,
4295 &tracker->res_tree[RES_MPT]);
4296 list_del(&mpt->com.list);
4297 spin_unlock_irq(mlx4_tlock(dev));
4298 mlx4_release_resource(dev, slave,
4304 case RES_MPT_MAPPED:
4305 __mlx4_mpt_free_icm(dev, mpt->key);
4306 state = RES_MPT_RESERVED;
4311 err = mlx4_cmd(dev, in_param, mptn, 0,
4313 MLX4_CMD_TIME_CLASS_A,
4316 mlx4_dbg(dev, "rem_slave_mrs: failed"
4317 " to move slave %d mpt %d to"
4321 atomic_dec(&mpt->mtt->ref_count);
4322 state = RES_MPT_MAPPED;
4329 spin_lock_irq(mlx4_tlock(dev));
4331 spin_unlock_irq(mlx4_tlock(dev));
4334 static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
4336 struct mlx4_priv *priv = mlx4_priv(dev);
4337 struct mlx4_resource_tracker *tracker =
4338 &priv->mfunc.master.res_tracker;
4339 struct list_head *mtt_list =
4340 &tracker->slave_list[slave].res_list[RES_MTT];
4341 struct res_mtt *mtt;
4342 struct res_mtt *tmp;
4348 err = move_all_busy(dev, slave, RES_MTT);
4350 mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
4351 "busy for slave %d\n", slave);
4353 spin_lock_irq(mlx4_tlock(dev));
4354 list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
4355 spin_unlock_irq(mlx4_tlock(dev));
4356 if (mtt->com.owner == slave) {
4357 base = mtt->com.res_id;
4358 state = mtt->com.from_state;
4359 while (state != 0) {
4361 case RES_MTT_ALLOCATED:
4362 __mlx4_free_mtt_range(dev, base,
4364 spin_lock_irq(mlx4_tlock(dev));
4365 rb_erase(&mtt->com.node,
4366 &tracker->res_tree[RES_MTT]);
4367 list_del(&mtt->com.list);
4368 spin_unlock_irq(mlx4_tlock(dev));
4369 mlx4_release_resource(dev, slave, RES_MTT,
4370 1 << mtt->order, 0);
4380 spin_lock_irq(mlx4_tlock(dev));
4382 spin_unlock_irq(mlx4_tlock(dev));
4385 static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
4387 struct mlx4_priv *priv = mlx4_priv(dev);
4388 struct mlx4_resource_tracker *tracker =
4389 &priv->mfunc.master.res_tracker;
4390 struct list_head *fs_rule_list =
4391 &tracker->slave_list[slave].res_list[RES_FS_RULE];
4392 struct res_fs_rule *fs_rule;
4393 struct res_fs_rule *tmp;
4398 err = move_all_busy(dev, slave, RES_FS_RULE);
4400 mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
4403 spin_lock_irq(mlx4_tlock(dev));
4404 list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
4405 spin_unlock_irq(mlx4_tlock(dev));
4406 if (fs_rule->com.owner == slave) {
4407 base = fs_rule->com.res_id;
4408 state = fs_rule->com.from_state;
4409 while (state != 0) {
4411 case RES_FS_RULE_ALLOCATED:
4413 err = mlx4_cmd(dev, base, 0, 0,
4414 MLX4_QP_FLOW_STEERING_DETACH,
4415 MLX4_CMD_TIME_CLASS_A,
4418 spin_lock_irq(mlx4_tlock(dev));
4419 rb_erase(&fs_rule->com.node,
4420 &tracker->res_tree[RES_FS_RULE]);
4421 list_del(&fs_rule->com.list);
4422 spin_unlock_irq(mlx4_tlock(dev));
4432 spin_lock_irq(mlx4_tlock(dev));
4434 spin_unlock_irq(mlx4_tlock(dev));
4437 static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
4439 struct mlx4_priv *priv = mlx4_priv(dev);
4440 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4441 struct list_head *eq_list =
4442 &tracker->slave_list[slave].res_list[RES_EQ];
4449 struct mlx4_cmd_mailbox *mailbox;
4451 err = move_all_busy(dev, slave, RES_EQ);
4453 mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
4454 "busy for slave %d\n", slave);
4456 spin_lock_irq(mlx4_tlock(dev));
4457 list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
4458 spin_unlock_irq(mlx4_tlock(dev));
4459 if (eq->com.owner == slave) {
4460 eqn = eq->com.res_id;
4461 state = eq->com.from_state;
4462 while (state != 0) {
4464 case RES_EQ_RESERVED:
4465 spin_lock_irq(mlx4_tlock(dev));
4466 rb_erase(&eq->com.node,
4467 &tracker->res_tree[RES_EQ]);
4468 list_del(&eq->com.list);
4469 spin_unlock_irq(mlx4_tlock(dev));
4475 mailbox = mlx4_alloc_cmd_mailbox(dev);
4476 if (IS_ERR(mailbox)) {
4480 err = mlx4_cmd_box(dev, slave, 0,
4483 MLX4_CMD_TIME_CLASS_A,
4486 mlx4_dbg(dev, "rem_slave_eqs: failed"
4487 " to move slave %d eqs %d to"
4488 " SW ownership\n", slave, eqn);
4489 mlx4_free_cmd_mailbox(dev, mailbox);
4490 atomic_dec(&eq->mtt->ref_count);
4491 state = RES_EQ_RESERVED;
4499 spin_lock_irq(mlx4_tlock(dev));
4501 spin_unlock_irq(mlx4_tlock(dev));
4504 static void rem_slave_counters(struct mlx4_dev *dev, int slave)
4506 __mlx4_slave_counters_free(dev, slave);
4509 static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
4511 struct mlx4_priv *priv = mlx4_priv(dev);
4512 struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
4513 struct list_head *xrcdn_list =
4514 &tracker->slave_list[slave].res_list[RES_XRCD];
4515 struct res_xrcdn *xrcd;
4516 struct res_xrcdn *tmp;
4520 err = move_all_busy(dev, slave, RES_XRCD);
4522 mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns to "
4523 "busy for slave %d\n", slave);
4525 spin_lock_irq(mlx4_tlock(dev));
4526 list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
4527 if (xrcd->com.owner == slave) {
4528 xrcdn = xrcd->com.res_id;
4529 rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
4530 list_del(&xrcd->com.list);
4532 __mlx4_xrcd_free(dev, xrcdn);
4535 spin_unlock_irq(mlx4_tlock(dev));
4538 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
4540 struct mlx4_priv *priv = mlx4_priv(dev);
4542 mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
4543 rem_slave_macs(dev, slave);
4544 rem_slave_vlans(dev, slave);
4545 rem_slave_fs_rule(dev, slave);
4546 rem_slave_qps(dev, slave);
4547 rem_slave_srqs(dev, slave);
4548 rem_slave_cqs(dev, slave);
4549 rem_slave_mrs(dev, slave);
4550 rem_slave_eqs(dev, slave);
4551 rem_slave_mtts(dev, slave);
4552 rem_slave_counters(dev, slave);
4553 rem_slave_xrcdns(dev, slave);
4554 mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
4557 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work)
4559 struct mlx4_vf_immed_vlan_work *work =
4560 container_of(_work, struct mlx4_vf_immed_vlan_work, work);
4561 struct mlx4_cmd_mailbox *mailbox;
4562 struct mlx4_update_qp_context *upd_context;
4563 struct mlx4_dev *dev = &work->priv->dev;
4564 struct mlx4_resource_tracker *tracker =
4565 &work->priv->mfunc.master.res_tracker;
4566 struct list_head *qp_list =
4567 &tracker->slave_list[work->slave].res_list[RES_QP];
4570 u64 qp_path_mask_vlan_ctrl =
4571 ((1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED) |
4572 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P) |
4573 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED) |
4574 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED) |
4575 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P) |
4576 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED));
4578 u64 qp_path_mask = ((1ULL << MLX4_UPD_QP_PATH_MASK_VLAN_INDEX) |
4579 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL) |
4580 (1ULL << MLX4_UPD_QP_PATH_MASK_CV) |
4581 (1ULL << MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN) |
4582 (1ULL << MLX4_UPD_QP_PATH_MASK_FEUP) |
4583 (1ULL << MLX4_UPD_QP_PATH_MASK_FVL_RX) |
4584 (1ULL << MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE));
4587 int port, errors = 0;
4590 if (mlx4_is_slave(dev)) {
4591 mlx4_warn(dev, "Trying to update-qp in slave %d\n",
4596 mailbox = mlx4_alloc_cmd_mailbox(dev);
4597 if (IS_ERR(mailbox))
4601 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
4602 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
4604 vlan_control = MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
4605 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
4606 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
4608 upd_context = mailbox->buf;
4609 upd_context->qp_mask = cpu_to_be64(MLX4_UPD_QP_MASK_VSD);
4611 spin_lock_irq(mlx4_tlock(dev));
4612 list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
4613 spin_unlock_irq(mlx4_tlock(dev));
4614 if (qp->com.owner == work->slave) {
4615 if (qp->com.from_state != RES_QP_HW ||
4616 !qp->sched_queue || /* no INIT2RTR trans yet */
4617 mlx4_is_qp_reserved(dev, qp->local_qpn) ||
4618 qp->qpc_flags & (1 << MLX4_RSS_QPC_FLAG_OFFSET)) {
4619 spin_lock_irq(mlx4_tlock(dev));
4622 port = (qp->sched_queue >> 6 & 1) + 1;
4623 if (port != work->port) {
4624 spin_lock_irq(mlx4_tlock(dev));
4627 if (MLX4_QP_ST_RC == ((qp->qpc_flags >> 16) & 0xff))
4628 upd_context->primary_addr_path_mask = cpu_to_be64(qp_path_mask);
4630 upd_context->primary_addr_path_mask =
4631 cpu_to_be64(qp_path_mask | qp_path_mask_vlan_ctrl);
4632 if (work->vlan_id == MLX4_VGT) {
4633 upd_context->qp_context.param3 = qp->param3;
4634 upd_context->qp_context.pri_path.vlan_control = qp->vlan_control;
4635 upd_context->qp_context.pri_path.fvl_rx = qp->fvl_rx;
4636 upd_context->qp_context.pri_path.vlan_index = qp->vlan_index;
4637 upd_context->qp_context.pri_path.fl = qp->pri_path_fl;
4638 upd_context->qp_context.pri_path.feup = qp->feup;
4639 upd_context->qp_context.pri_path.sched_queue =
4642 upd_context->qp_context.param3 = qp->param3 & ~cpu_to_be32(MLX4_STRIP_VLAN);
4643 upd_context->qp_context.pri_path.vlan_control = vlan_control;
4644 upd_context->qp_context.pri_path.vlan_index = work->vlan_ix;
4645 upd_context->qp_context.pri_path.fvl_rx =
4646 qp->fvl_rx | MLX4_FVL_RX_FORCE_ETH_VLAN;
4647 upd_context->qp_context.pri_path.fl =
4648 qp->pri_path_fl | MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
4649 upd_context->qp_context.pri_path.feup =
4650 qp->feup | MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
4651 upd_context->qp_context.pri_path.sched_queue =
4652 qp->sched_queue & 0xC7;
4653 upd_context->qp_context.pri_path.sched_queue |=
4654 ((work->qos & 0x7) << 3);
4657 err = mlx4_cmd(dev, mailbox->dma,
4658 qp->local_qpn & 0xffffff,
4659 0, MLX4_CMD_UPDATE_QP,
4660 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
4662 mlx4_info(dev, "UPDATE_QP failed for slave %d, "
4663 "port %d, qpn %d (%d)\n",
4664 work->slave, port, qp->local_qpn,
4669 spin_lock_irq(mlx4_tlock(dev));
4671 spin_unlock_irq(mlx4_tlock(dev));
4672 mlx4_free_cmd_mailbox(dev, mailbox);
4675 mlx4_err(dev, "%d UPDATE_QP failures for slave %d, port %d\n",
4676 errors, work->slave, work->port);
4678 /* unregister previous vlan_id if needed and we had no errors
4679 * while updating the QPs
4681 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN && !errors &&
4682 NO_INDX != work->orig_vlan_ix)
4683 __mlx4_unregister_vlan(&work->priv->dev, work->port,
4684 work->orig_vlan_id);