2 * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/kobject.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_vlan.h>
44 #include <linux/if_ether.h>
45 #ifdef CONFIG_MLX4_EN_DCB
46 #include <linux/dcbnl.h>
49 #include <dev/mlx4/device.h>
50 #include <dev/mlx4/qp.h>
51 #include <dev/mlx4/cq.h>
52 #include <dev/mlx4/srq.h>
53 #include <dev/mlx4/doorbell.h>
54 #include <dev/mlx4/cmd.h>
56 #include <net/debugnet.h>
57 #include <netinet/tcp_lro.h>
60 #include <dev/mlx4/stats.h>
62 #define DRV_NAME "mlx4_en"
64 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
71 #define MLX4_EN_PAGE_SHIFT 12
72 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
73 #define MLX4_NET_IP_ALIGN 2 /* bytes */
74 #define DEF_RX_RINGS 16
75 #define MAX_RX_RINGS 128
76 #define MIN_RX_RINGS 4
79 #ifndef MLX4_EN_MAX_RX_SEGS
80 #define MLX4_EN_MAX_RX_SEGS 1 /* or 8 */
83 #ifndef MLX4_EN_MAX_RX_BYTES
84 #define MLX4_EN_MAX_RX_BYTES MCLBYTES
87 #define HEADROOM (2048 / TXBB_SIZE + 1)
88 #define INIT_OWNER_BIT 0xffffffff
89 #define STAMP_STRIDE 64
90 #define STAMP_DWORDS (STAMP_STRIDE / 4)
91 #define STAMP_SHIFT 31
92 #define STAMP_VAL 0x7fffffff
93 #define STATS_DELAY (HZ / 4)
94 #define SERVICE_TASK_DELAY (HZ / 4)
95 #define MAX_NUM_OF_FS_RULES 256
97 #define MLX4_EN_FILTER_HASH_SHIFT 4
98 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
100 #ifdef CONFIG_NET_RX_BUSY_POLL
101 #define LL_EXTENDED_STATS
104 /* vlan valid range */
105 #define VLAN_MIN_VALUE 1
106 #define VLAN_MAX_VALUE 4094
109 * OS related constants and tunables
112 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
114 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(PAGE_SIZE)
115 #define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE)
117 enum mlx4_en_alloc_type {
118 MLX4_EN_ALLOC_NEW = 0,
119 MLX4_EN_ALLOC_REPLACEMENT = 1,
122 /* Maximum ring sizes */
123 #define MLX4_EN_DEF_TX_QUEUE_SIZE 4096
125 /* Minimum packet number till arming the CQ */
126 #define MLX4_EN_MIN_RX_ARM 2048
127 #define MLX4_EN_MIN_TX_ARM 2048
129 /* Maximum ring sizes */
130 #define MLX4_EN_MAX_TX_SIZE 8192
131 #define MLX4_EN_MAX_RX_SIZE 8192
133 /* Minimum ring sizes */
134 #define MLX4_EN_MIN_RX_SIZE (4096 / TXBB_SIZE)
135 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
137 #define MLX4_EN_SMALL_PKT_SIZE 64
139 #define MLX4_EN_MAX_TX_RING_P_UP 32
140 #define MLX4_EN_NUM_UP 1
142 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
145 #define MLX4_EN_NO_VLAN 0xffff
147 #define MLX4_EN_DEF_TX_RING_SIZE 1024
148 #define MLX4_EN_DEF_RX_RING_SIZE 1024
150 /* Target number of bytes to coalesce with interrupt moderation */
151 #define MLX4_EN_RX_COAL_TARGET 44
152 #define MLX4_EN_RX_COAL_TIME 0x10
154 #define MLX4_EN_TX_COAL_PKTS 64
155 #define MLX4_EN_TX_COAL_TIME 64
157 #define MLX4_EN_RX_RATE_LOW 400000
158 #define MLX4_EN_RX_COAL_TIME_LOW 0
159 #define MLX4_EN_RX_RATE_HIGH 450000
160 #define MLX4_EN_RX_COAL_TIME_HIGH 128
161 #define MLX4_EN_RX_SIZE_THRESH 1024
162 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
163 #define MLX4_EN_SAMPLE_INTERVAL 0
164 #define MLX4_EN_AVG_PKT_SMALL 256
166 #define MLX4_EN_AUTO_CONF 0xffff
168 #define MLX4_EN_DEF_RX_PAUSE 1
169 #define MLX4_EN_DEF_TX_PAUSE 1
171 /* Interval between successive polls in the Tx routine when polling is used
172 instead of interrupts (in per-core Tx rings) - should be power of 2 */
173 #define MLX4_EN_TX_POLL_MODER 16
174 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
176 #define MLX4_EN_64_ALIGN (64 - NET_SKB_PAD)
177 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
178 #define HEADER_COPY_SIZE (128)
179 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETHER_HDR_LEN)
181 #define MLX4_EN_MIN_MTU 46
182 #define ETH_BCAST 0xffffffffffffULL
184 #define MLX4_EN_LOOPBACK_RETRIES 5
185 #define MLX4_EN_LOOPBACK_TIMEOUT 100
187 #ifdef MLX4_EN_PERF_STAT
188 /* Number of samples to 'average' */
190 #define AVG_FACTOR 1024
192 #define INC_PERF_COUNTER(cnt) (++(cnt))
193 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
194 #define AVG_PERF_COUNTER(cnt, sample) \
195 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
196 #define GET_PERF_COUNTER(cnt) (cnt)
197 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
201 #define INC_PERF_COUNTER(cnt) do {} while (0)
202 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
203 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
204 #define GET_PERF_COUNTER(cnt) (0)
205 #define GET_AVG_PERF_COUNTER(cnt) (0)
206 #endif /* MLX4_EN_PERF_STAT */
208 /* Constants for TX flow */
210 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
228 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
229 #define XNOR(x, y) (!(x) == !(y))
230 #define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
232 struct mlx4_en_tx_info {
233 bus_dmamap_t dma_map;
240 #define MLX4_EN_BIT_DESC_OWN 0x80000000
241 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
242 #define MLX4_EN_MEMTYPE_PAD 0x100
243 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
246 struct mlx4_en_tx_desc {
247 struct mlx4_wqe_ctrl_seg ctrl;
249 struct mlx4_wqe_data_seg data; /* at least one data segment */
250 struct mlx4_wqe_lso_seg lso;
251 struct mlx4_wqe_inline_seg inl;
255 #define MLX4_EN_USE_SRQ 0x01000000
257 #define MLX4_EN_RX_BUDGET 64
259 #define MLX4_EN_TX_MAX_DESC_SIZE 512 /* bytes */
260 #define MLX4_EN_TX_MAX_MBUF_SIZE 65536 /* bytes */
261 #define MLX4_EN_TX_MAX_PAYLOAD_SIZE 65536 /* bytes */
262 #define MLX4_EN_TX_MAX_MBUF_FRAGS \
263 ((MLX4_EN_TX_MAX_DESC_SIZE - 128) / DS_SIZE_ALIGNMENT) /* units */
264 #define MLX4_EN_TX_WQE_MAX_WQEBBS \
265 (MLX4_EN_TX_MAX_DESC_SIZE / TXBB_SIZE) /* units */
267 #define MLX4_EN_CX3_LOW_ID 0x1000
268 #define MLX4_EN_CX3_HIGH_ID 0x1005
270 struct mlx4_en_tx_ring {
272 bus_dma_tag_t dma_tag;
273 struct mlx4_hwq_resources wqres;
274 u32 size ; /* number of TXBBs */
277 u16 cqn; /* index of port CQ associated with this ring */
284 struct mlx4_en_tx_info *tx_info;
288 struct mlx4_qp_context context;
290 enum mlx4_qp_state qp_state;
291 struct mlx4_srq dummy;
296 u64 oversized_packets;
302 int hwtstamp_tx_type;
303 spinlock_t comp_lock;
308 struct mlx4_en_rx_desc {
309 struct mlx4_wqe_data_seg data[MLX4_EN_MAX_RX_SEGS];
312 /* the size of the structure above must be power of two */
313 CTASSERT(powerof2(sizeof(struct mlx4_en_rx_desc)));
315 struct mlx4_en_rx_mbuf {
316 bus_dmamap_t dma_map;
320 struct mlx4_en_rx_spare {
321 bus_dmamap_t dma_map;
323 bus_dma_segment_t segs[MLX4_EN_MAX_RX_SEGS];
326 struct mlx4_en_rx_ring {
327 struct mlx4_hwq_resources wqres;
328 bus_dma_tag_t dma_tag;
329 struct mlx4_en_rx_spare spare;
330 u32 size ; /* number of Rx descs*/
334 u16 cqn; /* index of port CQ associated with this ring */
343 struct mlx4_en_rx_mbuf *mbuf;
347 #ifdef LL_EXTENDED_STATS
354 int hwtstamp_rx_filter;
359 static inline int mlx4_en_can_lro(__be16 status)
361 const __be16 status_all = cpu_to_be16(
362 MLX4_CQE_STATUS_IPV4 |
363 MLX4_CQE_STATUS_IPV4F |
364 MLX4_CQE_STATUS_IPV6 |
365 MLX4_CQE_STATUS_IPV4OPT |
366 MLX4_CQE_STATUS_TCP |
367 MLX4_CQE_STATUS_UDP |
368 MLX4_CQE_STATUS_IPOK);
369 const __be16 status_ipv4_ipok_tcp = cpu_to_be16(
370 MLX4_CQE_STATUS_IPV4 |
371 MLX4_CQE_STATUS_IPOK |
372 MLX4_CQE_STATUS_TCP);
373 const __be16 status_ipv6_ipok_tcp = cpu_to_be16(
374 MLX4_CQE_STATUS_IPV6 |
375 MLX4_CQE_STATUS_IPOK |
376 MLX4_CQE_STATUS_TCP);
378 status &= status_all;
379 return (status == status_ipv4_ipok_tcp ||
380 status == status_ipv6_ipok_tcp);
385 struct mlx4_hwq_resources wqres;
388 struct net_device *dev;
389 /* Per-core Tx cq processing support */
390 struct timer_list timer;
397 struct mlx4_cqe *buf;
399 struct taskqueue *tq;
400 #define MLX4_EN_OPCODE_ERROR 0x1e
403 u32 curr_poll_rx_cpu_id;
405 #ifdef CONFIG_NET_RX_BUSY_POLL
407 #define MLX4_EN_CQ_STATE_IDLE 0
408 #define MLX4_EN_CQ_STATE_NAPI 1 /* NAPI owns this CQ */
409 #define MLX4_EN_CQ_STATE_POLL 2 /* poll owns this CQ */
410 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL)
411 #define MLX4_EN_CQ_STATE_NAPI_YIELD 4 /* NAPI yielded this CQ */
412 #define MLX4_EN_CQ_STATE_POLL_YIELD 8 /* poll yielded this CQ */
413 #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD)
414 #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD)
415 spinlock_t poll_lock; /* protects from LLS/napi conflicts */
416 #endif /* CONFIG_NET_RX_BUSY_POLL */
419 struct mlx4_en_port_profile {
433 struct mlx4_en_profile {
440 u8 num_tx_rings_p_up;
441 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
445 struct mlx4_dev *dev;
446 struct pci_dev *pdev;
447 struct mutex state_lock;
448 struct net_device *pndev[MLX4_MAX_PORTS + 1];
451 struct mlx4_en_profile profile;
453 struct workqueue_struct *workqueue;
454 struct device *dma_device;
455 void __iomem *uar_map;
456 struct mlx4_uar priv_uar;
460 u8 mac_removed[MLX4_MAX_PORTS + 1];
461 unsigned long last_overflow_check;
462 unsigned long overflow_period;
466 struct mlx4_en_rss_map {
468 struct mlx4_qp qps[MAX_RX_RINGS];
469 enum mlx4_qp_state state[MAX_RX_RINGS];
470 struct mlx4_qp indir_qp;
471 enum mlx4_qp_state indir_state;
474 enum mlx4_en_port_flag {
475 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
476 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
479 struct mlx4_en_port_state {
486 enum mlx4_en_addr_list_act {
492 struct mlx4_en_addr_list {
493 struct list_head list;
494 enum mlx4_en_addr_list_act action;
500 #ifdef CONFIG_MLX4_EN_DCB
501 /* Minimal TC BW - setting to 0 will block traffic */
502 #define MLX4_EN_BW_MIN 1
503 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
505 #define MLX4_EN_TC_VENDOR 0
506 #define MLX4_EN_TC_ETS 7
512 MLX4_EN_FLAG_PROMISC = (1 << 0),
513 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
514 /* whether we need to enable hardware loopback by putting dmac
517 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
518 /* whether we need to drop packets that hardware loopback-ed */
519 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
520 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4),
521 #ifdef CONFIG_MLX4_EN_DCB
522 MLX4_EN_FLAG_DCB_ENABLED = (1 << 5)
526 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
527 #define MLX4_EN_MAC_HASH_IDX 5
531 struct mlx4_dev *dev;
536 struct mlx4_en_priv {
537 struct mlx4_en_dev *mdev;
538 struct mlx4_en_port_profile *prof;
539 struct net_device *dev;
540 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
541 struct mlx4_en_port_state port_state;
542 spinlock_t stats_lock;
543 /* To allow rules removal while port is going down */
544 struct list_head ethtool_list;
546 unsigned long last_moder_packets[MAX_RX_RINGS];
547 unsigned long last_moder_tx_packets;
548 unsigned long last_moder_bytes[MAX_RX_RINGS];
549 unsigned long last_moder_jiffies;
550 int last_moder_time[MAX_RX_RINGS];
560 u32 adaptive_rx_coal;
563 u32 validate_loopback;
565 struct mlx4_hwq_resources res;
573 unsigned char current_mac[ETH_ALEN + 2];
580 struct mlx4_en_rss_map rss_map;
582 u8 num_tx_rings_p_up;
587 struct mlx4_en_tx_ring **tx_ring;
588 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
589 struct mlx4_en_cq **tx_cq;
590 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
591 struct mlx4_qp drop_qp;
592 struct work_struct rx_mode_task;
593 struct work_struct watchdog_task;
594 struct work_struct linkstate_task;
595 struct delayed_work stats_task;
596 struct delayed_work service_task;
597 struct mlx4_en_perf_stats pstats;
598 struct mlx4_en_pkt_stats pkstats;
599 struct mlx4_en_pkt_stats pkstats_last;
600 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
601 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
602 struct mlx4_en_flow_stats_rx rx_flowstats;
603 struct mlx4_en_flow_stats_tx tx_flowstats;
604 struct mlx4_en_port_stats port_stats;
605 struct mlx4_en_vport_stats vport_stats;
606 struct mlx4_en_vf_stats vf_stats;
607 struct list_head mc_list;
608 struct list_head uc_list;
609 struct list_head curr_mc_list;
610 struct list_head curr_uc_list;
612 struct mlx4_en_stat_out_mbox hw_stats;
616 struct dentry *dev_root;
618 eventhandler_tag vlan_attach;
619 eventhandler_tag vlan_detach;
620 struct callout watchdog_timer;
621 struct ifmedia media;
622 volatile int blocked;
623 struct sysctl_oid *conf_sysctl;
624 struct sysctl_oid *stat_sysctl;
625 struct sysctl_ctx_list conf_ctx;
626 struct sysctl_ctx_list stat_ctx;
628 #ifdef CONFIG_MLX4_EN_DCB
630 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
633 #ifdef CONFIG_RFS_ACCEL
634 spinlock_t filters_lock;
636 struct list_head filters;
637 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
640 struct en_port *vf_ports[MLX4_MAX_NUM_VF];
641 unsigned long last_ifq_jiffies;
642 u64 if_counters_rx_errors;
643 u64 if_counters_rx_no_buffer;
647 MLX4_EN_WOL_MAGIC = (1ULL << 61),
648 MLX4_EN_WOL_ENABLED = (1ULL << 62),
651 struct mlx4_mac_entry {
652 struct hlist_node hlist;
653 unsigned char mac[ETH_ALEN + 2];
657 static inline struct mlx4_cqe *mlx4_en_get_cqe(u8 *buf, int idx, int cqe_sz)
659 return (struct mlx4_cqe *)(buf + idx * cqe_sz);
662 #ifdef CONFIG_NET_RX_BUSY_POLL
663 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
665 spin_lock_init(&cq->poll_lock);
666 cq->state = MLX4_EN_CQ_STATE_IDLE;
669 /* called from the device poll rutine to get ownership of a cq */
670 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
673 spin_lock(&cq->poll_lock);
674 if (cq->state & MLX4_CQ_LOCKED) {
675 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI);
676 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD;
679 /* we don't care if someone yielded */
680 cq->state = MLX4_EN_CQ_STATE_NAPI;
681 spin_unlock(&cq->poll_lock);
685 /* returns true is someone tried to get the cq while napi had it */
686 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
689 spin_lock(&cq->poll_lock);
690 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL |
691 MLX4_EN_CQ_STATE_NAPI_YIELD));
693 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
695 cq->state = MLX4_EN_CQ_STATE_IDLE;
696 spin_unlock(&cq->poll_lock);
700 /* called from mlx4_en_low_latency_poll() */
701 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
704 spin_lock_bh(&cq->poll_lock);
705 if ((cq->state & MLX4_CQ_LOCKED)) {
706 struct net_device *dev = cq->dev;
707 struct mlx4_en_priv *priv = netdev_priv(dev);
708 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
710 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD;
712 #ifdef LL_EXTENDED_STATS
716 /* preserve yield marks */
717 cq->state |= MLX4_EN_CQ_STATE_POLL;
718 spin_unlock_bh(&cq->poll_lock);
722 /* returns true if someone tried to get the cq while it was locked */
723 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
726 spin_lock_bh(&cq->poll_lock);
727 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI));
729 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
731 cq->state = MLX4_EN_CQ_STATE_IDLE;
732 spin_unlock_bh(&cq->poll_lock);
736 /* true if a socket is polling, even if it did not get the lock */
737 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
739 WARN_ON(!(cq->state & MLX4_CQ_LOCKED));
740 return cq->state & CQ_USER_PEND;
743 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
747 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
752 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
757 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
762 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
767 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
771 #endif /* CONFIG_NET_RX_BUSY_POLL */
773 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
775 void mlx4_en_destroy_netdev(struct net_device *dev);
776 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
777 struct mlx4_en_port_profile *prof);
779 int mlx4_en_start_port(struct net_device *dev);
780 void mlx4_en_stop_port(struct net_device *dev);
782 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
783 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
785 int mlx4_en_pre_config(struct mlx4_en_priv *priv);
786 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
787 int entries, int ring, enum cq_type mode, int node);
788 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
789 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
791 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
792 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
793 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
795 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
796 u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb);
798 int mlx4_en_xmit(struct mlx4_en_priv *priv, int tx_ind, struct mbuf **mbp);
799 int mlx4_en_transmit(struct ifnet *dev, struct mbuf *m);
800 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
801 struct mlx4_en_tx_ring **pring,
802 u32 size, u16 stride, int node, int queue_idx);
803 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
804 struct mlx4_en_tx_ring **pring);
805 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
806 struct mlx4_en_tx_ring *ring,
807 int cq, int user_prio);
808 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
809 struct mlx4_en_tx_ring *ring);
810 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
811 void mlx4_en_qflush(struct ifnet *dev);
813 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
814 struct mlx4_en_rx_ring **pring,
816 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
817 struct mlx4_en_rx_ring **pring,
819 void mlx4_en_rx_que(void *context, int pending);
820 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
821 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
822 struct mlx4_en_rx_ring *ring);
823 int mlx4_en_process_rx_cq(struct net_device *dev,
824 struct mlx4_en_cq *cq,
826 void mlx4_en_poll_tx_cq(unsigned long data);
827 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
828 int is_tx, int rss, int qpn, int cqn, int user_prio,
829 struct mlx4_qp_context *context);
830 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
831 int mlx4_en_map_buffer(struct mlx4_buf *buf);
832 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
833 void mlx4_en_calc_rx_buf(struct net_device *dev);
835 const u32 *mlx4_en_get_rss_key(struct mlx4_en_priv *priv, u16 *keylen);
836 u8 mlx4_en_get_rss_mask(struct mlx4_en_priv *priv);
837 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
838 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
839 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
840 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
841 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
842 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
844 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
846 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
847 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
848 int mlx4_en_get_vport_stats(struct mlx4_en_dev *mdev, u8 port);
849 void mlx4_en_create_debug_files(struct mlx4_en_priv *priv);
850 void mlx4_en_delete_debug_files(struct mlx4_en_priv *priv);
851 int mlx4_en_register_debugfs(void);
852 void mlx4_en_unregister_debugfs(void);
854 #ifdef CONFIG_MLX4_EN_DCB
855 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
856 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
859 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
861 #ifdef CONFIG_RFS_ACCEL
862 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv,
863 struct mlx4_en_rx_ring *rx_ring);
866 #define MLX4_EN_NUM_SELF_TEST 5
867 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
868 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
871 * Functions for time stamping
873 #define SKBTX_HW_TSTAMP (1 << 0)
874 #define SKBTX_IN_PROGRESS (1 << 2)
876 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
878 /* Functions for caching and restoring statistics */
879 int mlx4_en_get_sset_count(struct net_device *dev, int sset);
880 void mlx4_en_restore_ethtool_stats(struct mlx4_en_priv *priv,
886 extern const struct ethtool_ops mlx4_en_ethtool_ops;
889 * Defines for link speed - needed by selftest
891 #define MLX4_EN_LINK_SPEED_1G 1000
892 #define MLX4_EN_LINK_SPEED_10G 10000
893 #define MLX4_EN_LINK_SPEED_40G 40000
896 NETIF_MSG_DRV = 0x0001,
897 NETIF_MSG_PROBE = 0x0002,
898 NETIF_MSG_LINK = 0x0004,
899 NETIF_MSG_TIMER = 0x0008,
900 NETIF_MSG_IFDOWN = 0x0010,
901 NETIF_MSG_IFUP = 0x0020,
902 NETIF_MSG_RX_ERR = 0x0040,
903 NETIF_MSG_TX_ERR = 0x0080,
904 NETIF_MSG_TX_QUEUED = 0x0100,
905 NETIF_MSG_INTR = 0x0200,
906 NETIF_MSG_TX_DONE = 0x0400,
907 NETIF_MSG_RX_STATUS = 0x0800,
908 NETIF_MSG_PKTDATA = 0x1000,
909 NETIF_MSG_HW = 0x2000,
910 NETIF_MSG_WOL = 0x4000,
915 * printk / logging functions
918 #define en_print(level, priv, format, arg...) \
920 if ((priv)->registered) \
921 printk(level "%s: %s: " format, DRV_NAME, \
922 (priv)->dev->if_xname, ## arg); \
924 printk(level "%s: %s: Port %d: " format, \
925 DRV_NAME, dev_name(&(priv)->mdev->pdev->dev), \
926 (priv)->port, ## arg); \
930 #define en_dbg(mlevel, priv, format, arg...) \
932 if (NETIF_MSG_##mlevel & priv->msg_enable) \
933 en_print(KERN_DEBUG, priv, format, ##arg); \
935 #define en_warn(priv, format, arg...) \
936 en_print(KERN_WARNING, priv, format, ##arg)
937 #define en_err(priv, format, arg...) \
938 en_print(KERN_ERR, priv, format, ##arg)
939 #define en_info(priv, format, arg...) \
940 en_print(KERN_INFO, priv, format, ## arg)
942 #define mlx4_err(mdev, format, arg...) \
943 pr_err("%s %s: " format, DRV_NAME, \
944 dev_name(&(mdev)->pdev->dev), ##arg)
945 #define mlx4_info(mdev, format, arg...) \
946 pr_info("%s %s: " format, DRV_NAME, \
947 dev_name(&(mdev)->pdev->dev), ##arg)
948 #define mlx4_warn(mdev, format, arg...) \
949 pr_warning("%s %s: " format, DRV_NAME, \
950 dev_name(&(mdev)->pdev->dev), ##arg)