sys/dev/mlx4/mlx4_en/mlx4_en_rx.c

   1 /*
   2  * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33 #include "opt_inet.h"
  34 #include <dev/mlx4/cq.h>
  35 #include <linux/slab.h>
  36 #include <dev/mlx4/qp.h>
  37 #include <linux/if_ether.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/vmalloc.h>
  40 #include <dev/mlx4/driver.h>
  41 #ifdef CONFIG_NET_RX_BUSY_POLL
  42 #include <net/busy_poll.h>
  43 #endif
  44
  45 #include "en.h"
  46
  47
  48 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
  49                                  struct mlx4_en_rx_ring *ring,
  50                                  int index)
  51 {
  52         struct mlx4_en_rx_desc *rx_desc = (struct mlx4_en_rx_desc *)
  53             (ring->buf + (ring->stride * index));
  54         int possible_frags;
  55         int i;
  56
  57         /* Set size and memtype fields */
  58         rx_desc->data[0].byte_count = cpu_to_be32(priv->rx_mb_size - MLX4_NET_IP_ALIGN);
  59         rx_desc->data[0].lkey = cpu_to_be32(priv->mdev->mr.key);
  60
  61         /*
  62          * If the number of used fragments does not fill up the ring
  63          * stride, remaining (unused) fragments must be padded with
  64          * null address/size and a special memory key:
  65          */
  66         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
  67         for (i = 1; i < possible_frags; i++) {
  68                 rx_desc->data[i].byte_count = 0;
  69                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
  70                 rx_desc->data[i].addr = 0;
  71         }
  72 }
  73
  74 static int
  75 mlx4_en_alloc_buf(struct mlx4_en_rx_ring *ring,
  76      __be64 *pdma, struct mlx4_en_rx_mbuf *mb_list)
  77 {
  78         bus_dma_segment_t segs[1];
  79         bus_dmamap_t map;
  80         struct mbuf *mb;
  81         int nsegs;
  82         int err;
  83
  84         /* try to allocate a new spare mbuf */
  85         if (unlikely(ring->spare.mbuf == NULL)) {
  86                 mb = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, ring->rx_mb_size);
  87                 if (unlikely(mb == NULL))
  88                         return (-ENOMEM);
  89                 /* setup correct length */
  90                 mb->m_pkthdr.len = mb->m_len = ring->rx_mb_size;
  91
  92                 /* make sure IP header gets aligned */
  93                 m_adj(mb, MLX4_NET_IP_ALIGN);
  94
  95                 /* load spare mbuf into BUSDMA */
  96                 err = -bus_dmamap_load_mbuf_sg(ring->dma_tag, ring->spare.dma_map,
  97                     mb, segs, &nsegs, BUS_DMA_NOWAIT);
  98                 if (unlikely(err != 0)) {
  99                         m_freem(mb);
 100                         return (err);
 101                 }
 102
 103                 /* store spare info */
 104                 ring->spare.mbuf = mb;
 105                 ring->spare.paddr_be = cpu_to_be64(segs[0].ds_addr);
 106
 107                 bus_dmamap_sync(ring->dma_tag, ring->spare.dma_map,
 108                     BUS_DMASYNC_PREREAD);
 109         }
 110
 111         /* synchronize and unload the current mbuf, if any */
 112         if (likely(mb_list->mbuf != NULL)) {
 113                 bus_dmamap_sync(ring->dma_tag, mb_list->dma_map,
 114                     BUS_DMASYNC_POSTREAD);
 115                 bus_dmamap_unload(ring->dma_tag, mb_list->dma_map);
 116         }
 117
 118         mb = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, ring->rx_mb_size);
 119         if (unlikely(mb == NULL))
 120                 goto use_spare;
 121
 122         /* setup correct length */
 123         mb->m_pkthdr.len = mb->m_len = ring->rx_mb_size;
 124
 125         /* make sure IP header gets aligned */
 126         m_adj(mb, MLX4_NET_IP_ALIGN);
 127
 128         err = -bus_dmamap_load_mbuf_sg(ring->dma_tag, mb_list->dma_map,
 129             mb, segs, &nsegs, BUS_DMA_NOWAIT);
 130         if (unlikely(err != 0)) {
 131                 m_freem(mb);
 132                 goto use_spare;
 133         }
 134
 135         *pdma = cpu_to_be64(segs[0].ds_addr);
 136         mb_list->mbuf = mb;
 137
 138         bus_dmamap_sync(ring->dma_tag, mb_list->dma_map, BUS_DMASYNC_PREREAD);
 139         return (0);
 140
 141 use_spare:
 142         /* swap DMA maps */
 143         map = mb_list->dma_map;
 144         mb_list->dma_map = ring->spare.dma_map;
 145         ring->spare.dma_map = map;
 146
 147         /* swap MBUFs */
 148         mb_list->mbuf = ring->spare.mbuf;
 149         ring->spare.mbuf = NULL;
 150
 151         /* store physical address */
 152         *pdma = ring->spare.paddr_be;
 153         return (0);
 154 }
 155
 156 static void
 157 mlx4_en_free_buf(struct mlx4_en_rx_ring *ring, struct mlx4_en_rx_mbuf *mb_list)
 158 {
 159         bus_dmamap_t map = mb_list->dma_map;
 160         bus_dmamap_sync(ring->dma_tag, map, BUS_DMASYNC_POSTREAD);
 161         bus_dmamap_unload(ring->dma_tag, map);
 162         m_freem(mb_list->mbuf);
 163         mb_list->mbuf = NULL;   /* safety clearing */
 164 }
 165
 166 static int
 167 mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
 168     struct mlx4_en_rx_ring *ring, int index)
 169 {
 170         struct mlx4_en_rx_desc *rx_desc = (struct mlx4_en_rx_desc *)
 171             (ring->buf + (index * ring->stride));
 172         struct mlx4_en_rx_mbuf *mb_list = ring->mbuf + index;
 173
 174         mb_list->mbuf = NULL;
 175
 176         if (mlx4_en_alloc_buf(ring, &rx_desc->data[0].addr, mb_list)) {
 177                 priv->port_stats.rx_alloc_failed++;
 178                 return (-ENOMEM);
 179         }
 180         return (0);
 181 }
 182
 183 static inline void
 184 mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
 185 {
 186         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
 187 }
 188
 189 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
 190 {
 191         struct mlx4_en_rx_ring *ring;
 192         int ring_ind;
 193         int buf_ind;
 194         int new_size;
 195         int err;
 196
 197         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
 198                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 199                         ring = priv->rx_ring[ring_ind];
 200
 201                         err = mlx4_en_prepare_rx_desc(priv, ring,
 202                                                       ring->actual_size);
 203                         if (err) {
 204                                 if (ring->actual_size == 0) {
 205                                         en_err(priv, "Failed to allocate "
 206                                                      "enough rx buffers\n");
 207                                         return -ENOMEM;
 208                                 } else {
 209                                         new_size =
 210                                                 rounddown_pow_of_two(ring->actual_size);
 211                                         en_warn(priv, "Only %d buffers allocated "
 212                                                       "reducing ring size to %d\n",
 213                                                 ring->actual_size, new_size);
 214                                         goto reduce_rings;
 215                                 }
 216                         }
 217                         ring->actual_size++;
 218                         ring->prod++;
 219                 }
 220         }
 221         return 0;
 222
 223 reduce_rings:
 224         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 225                 ring = priv->rx_ring[ring_ind];
 226                 while (ring->actual_size > new_size) {
 227                         ring->actual_size--;
 228                         ring->prod--;
 229                         mlx4_en_free_buf(ring,
 230                             ring->mbuf + ring->actual_size);
 231                 }
 232         }
 233
 234         return 0;
 235 }
 236
 237 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
 238                                 struct mlx4_en_rx_ring *ring)
 239 {
 240         int index;
 241
 242         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
 243                ring->cons, ring->prod);
 244
 245         /* Unmap and free Rx buffers */
 246         BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
 247         while (ring->cons != ring->prod) {
 248                 index = ring->cons & ring->size_mask;
 249                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
 250                 mlx4_en_free_buf(ring, ring->mbuf + index);
 251                 ++ring->cons;
 252         }
 253 }
 254
 255 void mlx4_en_calc_rx_buf(struct net_device *dev)
 256 {
 257         struct mlx4_en_priv *priv = netdev_priv(dev);
 258         int eff_mtu = dev->if_mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN +
 259             MLX4_NET_IP_ALIGN;
 260
 261         if (eff_mtu > MJUM16BYTES) {
 262                 en_err(priv, "MTU(%d) is too big\n", dev->if_mtu);
 263                 eff_mtu = MJUM16BYTES;
 264         } else if (eff_mtu > MJUM9BYTES) {
 265                 eff_mtu = MJUM16BYTES;
 266         } else if (eff_mtu > MJUMPAGESIZE) {
 267                 eff_mtu = MJUM9BYTES;
 268         } else if (eff_mtu > MCLBYTES) {
 269                 eff_mtu = MJUMPAGESIZE;
 270         } else {
 271                 eff_mtu = MCLBYTES;
 272         }
 273
 274         priv->rx_mb_size = eff_mtu;
 275
 276         en_dbg(DRV, priv, "Effective RX MTU: %d bytes\n", eff_mtu);
 277 }
 278
 279 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 280                            struct mlx4_en_rx_ring **pring,
 281                            u32 size, int node)
 282 {
 283         struct mlx4_en_dev *mdev = priv->mdev;
 284         struct mlx4_en_rx_ring *ring;
 285         int err;
 286         int tmp;
 287         uint32_t x;
 288
 289         ring = kzalloc(sizeof(struct mlx4_en_rx_ring), GFP_KERNEL);
 290         if (!ring) {
 291                 en_err(priv, "Failed to allocate RX ring structure\n");
 292                 return -ENOMEM;
 293         }
 294
 295         /* Create DMA descriptor TAG */
 296         if ((err = -bus_dma_tag_create(
 297             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 298             1,                          /* any alignment */
 299             0,                          /* no boundary */
 300             BUS_SPACE_MAXADDR,          /* lowaddr */
 301             BUS_SPACE_MAXADDR,          /* highaddr */
 302             NULL, NULL,                 /* filter, filterarg */
 303             MJUM16BYTES,                /* maxsize */
 304             1,                          /* nsegments */
 305             MJUM16BYTES,                /* maxsegsize */
 306             0,                          /* flags */
 307             NULL, NULL,                 /* lockfunc, lockfuncarg */
 308             &ring->dma_tag))) {
 309                 en_err(priv, "Failed to create DMA tag\n");
 310                 goto err_ring;
 311         }
 312
 313         ring->prod = 0;
 314         ring->cons = 0;
 315         ring->size = size;
 316         ring->size_mask = size - 1;
 317         ring->stride = roundup_pow_of_two(
 318             sizeof(struct mlx4_en_rx_desc) + DS_SIZE);
 319         ring->log_stride = ffs(ring->stride) - 1;
 320         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
 321
 322         tmp = size * sizeof(struct mlx4_en_rx_mbuf);
 323
 324         ring->mbuf = kzalloc(tmp, GFP_KERNEL);
 325         if (ring->mbuf == NULL) {
 326                 err = -ENOMEM;
 327                 goto err_dma_tag;
 328         }
 329
 330         err = -bus_dmamap_create(ring->dma_tag, 0, &ring->spare.dma_map);
 331         if (err != 0)
 332                 goto err_info;
 333
 334         for (x = 0; x != size; x++) {
 335                 err = -bus_dmamap_create(ring->dma_tag, 0,
 336                     &ring->mbuf[x].dma_map);
 337                 if (err != 0) {
 338                         while (x--)
 339                                 bus_dmamap_destroy(ring->dma_tag,
 340                                     ring->mbuf[x].dma_map);
 341                         goto err_info;
 342                 }
 343         }
 344         en_dbg(DRV, priv, "Allocated MBUF ring at addr:%p size:%d\n",
 345                  ring->mbuf, tmp);
 346
 347         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
 348                                  ring->buf_size, 2 * PAGE_SIZE);
 349         if (err)
 350                 goto err_dma_map;
 351
 352         err = mlx4_en_map_buffer(&ring->wqres.buf);
 353         if (err) {
 354                 en_err(priv, "Failed to map RX buffer\n");
 355                 goto err_hwq;
 356         }
 357         ring->buf = ring->wqres.buf.direct.buf;
 358         *pring = ring;
 359         return 0;
 360
 361 err_hwq:
 362         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 363 err_dma_map:
 364         for (x = 0; x != size; x++) {
 365                 bus_dmamap_destroy(ring->dma_tag,
 366                     ring->mbuf[x].dma_map);
 367         }
 368         bus_dmamap_destroy(ring->dma_tag, ring->spare.dma_map);
 369 err_info:
 370         vfree(ring->mbuf);
 371 err_dma_tag:
 372         bus_dma_tag_destroy(ring->dma_tag);
 373 err_ring:
 374         kfree(ring);
 375         return (err);
 376 }
 377
 378 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
 379 {
 380         struct mlx4_en_rx_ring *ring;
 381         int i;
 382         int ring_ind;
 383         int err;
 384         int stride = roundup_pow_of_two(
 385             sizeof(struct mlx4_en_rx_desc) + DS_SIZE);
 386
 387         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 388                 ring = priv->rx_ring[ring_ind];
 389
 390                 ring->prod = 0;
 391                 ring->cons = 0;
 392                 ring->actual_size = 0;
 393                 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
 394                 ring->rx_mb_size = priv->rx_mb_size;
 395
 396                 ring->stride = stride;
 397                 if (ring->stride <= TXBB_SIZE) {
 398                         /* Stamp first unused send wqe */
 399                         __be32 *ptr = (__be32 *)ring->buf;
 400                         __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT);
 401                         *ptr = stamp;
 402                         /* Move pointer to start of rx section */
 403                         ring->buf += TXBB_SIZE;
 404                 }
 405
 406                 ring->log_stride = ffs(ring->stride) - 1;
 407                 ring->buf_size = ring->size * ring->stride;
 408
 409                 memset(ring->buf, 0, ring->buf_size);
 410                 mlx4_en_update_rx_prod_db(ring);
 411
 412                 /* Initialize all descriptors */
 413                 for (i = 0; i < ring->size; i++)
 414                         mlx4_en_init_rx_desc(priv, ring, i);
 415
 416 #ifdef INET
 417                 /* Configure lro mngr */
 418                 if (priv->dev->if_capenable & IFCAP_LRO) {
 419                         if (tcp_lro_init(&ring->lro))
 420                                 priv->dev->if_capenable &= ~IFCAP_LRO;
 421                         else
 422                                 ring->lro.ifp = priv->dev;
 423                 }
 424 #endif
 425         }
 426
 427
 428         err = mlx4_en_fill_rx_buffers(priv);
 429         if (err)
 430                 goto err_buffers;
 431
 432         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 433                 ring = priv->rx_ring[ring_ind];
 434
 435                 ring->size_mask = ring->actual_size - 1;
 436                 mlx4_en_update_rx_prod_db(ring);
 437         }
 438
 439         return 0;
 440
 441 err_buffers:
 442         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
 443                 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
 444
 445         ring_ind = priv->rx_ring_num - 1;
 446
 447         while (ring_ind >= 0) {
 448                 ring = priv->rx_ring[ring_ind];
 449                 if (ring->stride <= TXBB_SIZE)
 450                         ring->buf -= TXBB_SIZE;
 451                 ring_ind--;
 452         }
 453
 454         return err;
 455 }
 456
 457
 458 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 459                              struct mlx4_en_rx_ring **pring,
 460                              u32 size, u16 stride)
 461 {
 462         struct mlx4_en_dev *mdev = priv->mdev;
 463         struct mlx4_en_rx_ring *ring = *pring;
 464         uint32_t x;
 465
 466         mlx4_en_unmap_buffer(&ring->wqres.buf);
 467         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
 468         for (x = 0; x != size; x++)
 469                 bus_dmamap_destroy(ring->dma_tag, ring->mbuf[x].dma_map);
 470         /* free spare mbuf, if any */
 471         if (ring->spare.mbuf != NULL) {
 472                 bus_dmamap_sync(ring->dma_tag, ring->spare.dma_map,
 473                     BUS_DMASYNC_POSTREAD);
 474                 bus_dmamap_unload(ring->dma_tag, ring->spare.dma_map);
 475                 m_freem(ring->spare.mbuf);
 476         }
 477         bus_dmamap_destroy(ring->dma_tag, ring->spare.dma_map);
 478         vfree(ring->mbuf);
 479         bus_dma_tag_destroy(ring->dma_tag);
 480         kfree(ring);
 481         *pring = NULL;
 482 #ifdef CONFIG_RFS_ACCEL
 483         mlx4_en_cleanup_filters(priv, ring);
 484 #endif
 485 }
 486
 487 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 488                                 struct mlx4_en_rx_ring *ring)
 489 {
 490 #ifdef INET
 491         tcp_lro_free(&ring->lro);
 492 #endif
 493         mlx4_en_free_rx_buf(priv, ring);
 494         if (ring->stride <= TXBB_SIZE)
 495                 ring->buf -= TXBB_SIZE;
 496 }
 497
 498
 499 static void validate_loopback(struct mlx4_en_priv *priv, struct mbuf *mb)
 500 {
 501         int i;
 502         int offset = ETHER_HDR_LEN;
 503
 504         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
 505                 if (*(mb->m_data + offset) != (unsigned char) (i & 0xff))
 506                         goto out_loopback;
 507         }
 508         /* Loopback found */
 509         priv->loopback_ok = 1;
 510
 511 out_loopback:
 512         m_freem(mb);
 513 }
 514
 515
 516 static inline int invalid_cqe(struct mlx4_en_priv *priv,
 517                               struct mlx4_cqe *cqe)
 518 {
 519         /* Drop packet on bad receive or bad checksum */
 520         if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 521                      MLX4_CQE_OPCODE_ERROR)) {
 522                 en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
 523                        ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
 524                        ((struct mlx4_err_cqe *)cqe)->syndrome);
 525                 return 1;
 526         }
 527         if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
 528                 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
 529                 return 1;
 530         }
 531
 532         return 0;
 533 }
 534
 535 static struct mbuf *
 536 mlx4_en_rx_mb(struct mlx4_en_priv *priv, struct mlx4_en_rx_ring *ring,
 537     struct mlx4_en_rx_desc *rx_desc, struct mlx4_en_rx_mbuf *mb_list,
 538     int length)
 539 {
 540         struct mbuf *mb;
 541
 542         /* get mbuf */
 543         mb = mb_list->mbuf;
 544
 545         /* collect used fragment while atomically replacing it */
 546         if (mlx4_en_alloc_buf(ring, &rx_desc->data[0].addr, mb_list))
 547                 return (NULL);
 548
 549         /* range check hardware computed value */
 550         if (unlikely(length > mb->m_len))
 551                 length = mb->m_len;
 552
 553         /* update total packet length in packet header */
 554         mb->m_len = mb->m_pkthdr.len = length;
 555         return (mb);
 556 }
 557
 558 /* For cpu arch with cache line of 64B the performance is better when cqe size==64B
 559  * To enlarge cqe size from 32B to 64B --> 32B of garbage (i.e. 0xccccccc)
 560  * was added in the beginning of each cqe (the real data is in the corresponding 32B).
 561  * The following calc ensures that when factor==1, it means we are aligned to 64B
 562  * and we get the real cqe data*/
 563 #define CQE_FACTOR_INDEX(index, factor) ((index << factor) + factor)
 564 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
 565 {
 566         struct mlx4_en_priv *priv = netdev_priv(dev);
 567         struct mlx4_cqe *cqe;
 568         struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
 569         struct mlx4_en_rx_mbuf *mb_list;
 570         struct mlx4_en_rx_desc *rx_desc;
 571         struct mbuf *mb;
 572         struct mlx4_cq *mcq = &cq->mcq;
 573         struct mlx4_cqe *buf = cq->buf;
 574         int index;
 575         unsigned int length;
 576         int polled = 0;
 577         u32 cons_index = mcq->cons_index;
 578         u32 size_mask = ring->size_mask;
 579         int size = cq->size;
 580         int factor = priv->cqe_factor;
 581
 582         if (!priv->port_up)
 583                 return 0;
 584
 585         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
 586          * descriptor offset can be deducted from the CQE index instead of
 587          * reading 'cqe->index' */
 588         index = cons_index & size_mask;
 589         cqe = &buf[CQE_FACTOR_INDEX(index, factor)];
 590
 591         /* Process all completed CQEs */
 592         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 593                     cons_index & size)) {
 594                 mb_list = ring->mbuf + index;
 595                 rx_desc = (struct mlx4_en_rx_desc *)
 596                     (ring->buf + (index << ring->log_stride));
 597
 598                 /*
 599                  * make sure we read the CQE after we read the ownership bit
 600                  */
 601                 rmb();
 602
 603                 if (invalid_cqe(priv, cqe)) {
 604                         goto next;
 605                 }
 606                 /*
 607                  * Packet is OK - process it.
 608                  */
 609                 length = be32_to_cpu(cqe->byte_cnt);
 610                 length -= ring->fcs_del;
 611
 612                 mb = mlx4_en_rx_mb(priv, ring, rx_desc, mb_list, length);
 613                 if (unlikely(!mb)) {
 614                         ring->errors++;
 615                         goto next;
 616                 }
 617
 618                 ring->bytes += length;
 619                 ring->packets++;
 620
 621                 if (unlikely(priv->validate_loopback)) {
 622                         validate_loopback(priv, mb);
 623                         goto next;
 624                 }
 625
 626                 /* forward Toeplitz compatible hash value */
 627                 mb->m_pkthdr.flowid = be32_to_cpu(cqe->immed_rss_invalid);
 628                 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE_HASH);
 629                 mb->m_pkthdr.rcvif = dev;
 630                 if (be32_to_cpu(cqe->vlan_my_qpn) &
 631                     MLX4_CQE_VLAN_PRESENT_MASK) {
 632                         mb->m_pkthdr.ether_vtag = be16_to_cpu(cqe->sl_vid);
 633                         mb->m_flags |= M_VLANTAG;
 634                 }
 635                 if (likely(dev->if_capenable &
 636                     (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) &&
 637                     (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
 638                     (cqe->checksum == cpu_to_be16(0xffff))) {
 639                         priv->port_stats.rx_chksum_good++;
 640                         mb->m_pkthdr.csum_flags =
 641                             CSUM_IP_CHECKED | CSUM_IP_VALID |
 642                             CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
 643                         mb->m_pkthdr.csum_data = htons(0xffff);
 644                         /* This packet is eligible for LRO if it is:
 645                          * - DIX Ethernet (type interpretation)
 646                          * - TCP/IP (v4)
 647                          * - without IP options
 648                          * - not an IP fragment
 649                          */
 650 #ifdef INET
 651                         if (mlx4_en_can_lro(cqe->status) &&
 652                                         (dev->if_capenable & IFCAP_LRO)) {
 653                                 if (ring->lro.lro_cnt != 0 &&
 654                                                 tcp_lro_rx(&ring->lro, mb, 0) == 0)
 655                                         goto next;
 656                         }
 657
 658 #endif
 659                         /* LRO not possible, complete processing here */
 660                         INC_PERF_COUNTER(priv->pstats.lro_misses);
 661                 } else {
 662                         mb->m_pkthdr.csum_flags = 0;
 663                         priv->port_stats.rx_chksum_none++;
 664                 }
 665
 666                 /* Push it up the stack */
 667                 dev->if_input(dev, mb);
 668
 669 next:
 670                 ++cons_index;
 671                 index = cons_index & size_mask;
 672                 cqe = &buf[CQE_FACTOR_INDEX(index, factor)];
 673                 if (++polled == budget)
 674                         goto out;
 675         }
 676         /* Flush all pending IP reassembly sessions */
 677 out:
 678 #ifdef INET
 679         tcp_lro_flush_all(&ring->lro);
 680 #endif
 681         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
 682         mcq->cons_index = cons_index;
 683         mlx4_cq_set_ci(mcq);
 684         wmb(); /* ensure HW sees CQ consumer before we post new buffers */
 685         ring->cons = mcq->cons_index;
 686         ring->prod += polled; /* Polled descriptors were realocated in place */
 687         mlx4_en_update_rx_prod_db(ring);
 688         return polled;
 689
 690 }
 691
 692 /* Rx CQ polling - called by NAPI */
 693 static int mlx4_en_poll_rx_cq(struct mlx4_en_cq *cq, int budget)
 694 {
 695         struct net_device *dev = cq->dev;
 696         int done;
 697
 698         done = mlx4_en_process_rx_cq(dev, cq, budget);
 699         cq->tot_rx += done;
 700
 701         return done;
 702
 703 }
 704 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
 705 {
 706         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
 707         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
 708         int done;
 709
 710         // Shoot one within the irq context
 711         // Because there is no NAPI in freeBSD
 712         done = mlx4_en_poll_rx_cq(cq, MLX4_EN_RX_BUDGET);
 713         if (priv->port_up  && (done == MLX4_EN_RX_BUDGET) ) {
 714                 cq->curr_poll_rx_cpu_id = curcpu;
 715                 taskqueue_enqueue(cq->tq, &cq->cq_task);
 716         }
 717         else {
 718                 mlx4_en_arm_cq(priv, cq);
 719         }
 720 }
 721
 722 void mlx4_en_rx_que(void *context, int pending)
 723 {
 724         struct mlx4_en_cq *cq;
 725         struct thread *td;
 726
 727         cq = context;
 728         td = curthread;
 729
 730         thread_lock(td);
 731         sched_bind(td, cq->curr_poll_rx_cpu_id);
 732         thread_unlock(td);
 733
 734         while (mlx4_en_poll_rx_cq(cq, MLX4_EN_RX_BUDGET)
 735                         == MLX4_EN_RX_BUDGET);
 736         mlx4_en_arm_cq(cq->dev->if_softc, cq);
 737 }
 738
 739
 740 /* RSS related functions */
 741
 742 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
 743                                  struct mlx4_en_rx_ring *ring,
 744                                  enum mlx4_qp_state *state,
 745                                  struct mlx4_qp *qp)
 746 {
 747         struct mlx4_en_dev *mdev = priv->mdev;
 748         struct mlx4_qp_context *context;
 749         int err = 0;
 750
 751         context = kmalloc(sizeof *context , GFP_KERNEL);
 752         if (!context) {
 753                 en_err(priv, "Failed to allocate qp context\n");
 754                 return -ENOMEM;
 755         }
 756
 757         err = mlx4_qp_alloc(mdev->dev, qpn, qp);
 758         if (err) {
 759                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
 760                 goto out;
 761         }
 762         qp->event = mlx4_en_sqp_event;
 763
 764         memset(context, 0, sizeof *context);
 765         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
 766                                 qpn, ring->cqn, -1, context);
 767         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
 768
 769         /* Cancel FCS removal if FW allows */
 770         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
 771                 context->param3 |= cpu_to_be32(1 << 29);
 772                 ring->fcs_del = ETH_FCS_LEN;
 773         } else
 774                 ring->fcs_del = 0;
 775
 776         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
 777         if (err) {
 778                 mlx4_qp_remove(mdev->dev, qp);
 779                 mlx4_qp_free(mdev->dev, qp);
 780         }
 781         mlx4_en_update_rx_prod_db(ring);
 782 out:
 783         kfree(context);
 784         return err;
 785 }
 786
 787 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
 788 {
 789         int err;
 790         u32 qpn;
 791
 792         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn, 0);
 793         if (err) {
 794                 en_err(priv, "Failed reserving drop qpn\n");
 795                 return err;
 796         }
 797         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp);
 798         if (err) {
 799                 en_err(priv, "Failed allocating drop qp\n");
 800                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
 801                 return err;
 802         }
 803
 804         return 0;
 805 }
 806
 807 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
 808 {
 809         u32 qpn;
 810
 811         qpn = priv->drop_qp.qpn;
 812         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
 813         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
 814         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
 815 }
 816
 817 /* Allocate rx qp's and configure them according to rss map */
 818 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
 819 {
 820         struct mlx4_en_dev *mdev = priv->mdev;
 821         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
 822         struct mlx4_qp_context context;
 823         struct mlx4_rss_context *rss_context;
 824         int rss_rings;
 825         void *ptr;
 826         u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
 827                         MLX4_RSS_TCP_IPV6);
 828         int i;
 829         int err = 0;
 830         int good_qps = 0;
 831         static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC,
 832                                 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD,
 833                                 0x593D56D9, 0xF3253C06, 0x2ADC1FFC};
 834
 835         en_dbg(DRV, priv, "Configuring rss steering\n");
 836         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
 837                                     priv->rx_ring_num,
 838                                     &rss_map->base_qpn, 0);
 839         if (err) {
 840                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
 841                 return err;
 842         }
 843
 844         for (i = 0; i < priv->rx_ring_num; i++) {
 845                 priv->rx_ring[i]->qpn = rss_map->base_qpn + i;
 846                 err = mlx4_en_config_rss_qp(priv, priv->rx_ring[i]->qpn,
 847                                             priv->rx_ring[i],
 848                                             &rss_map->state[i],
 849                                             &rss_map->qps[i]);
 850                 if (err)
 851                         goto rss_err;
 852
 853                 ++good_qps;
 854         }
 855
 856         /* Configure RSS indirection qp */
 857         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
 858         if (err) {
 859                 en_err(priv, "Failed to allocate RSS indirection QP\n");
 860                 goto rss_err;
 861         }
 862         rss_map->indir_qp.event = mlx4_en_sqp_event;
 863         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
 864                                 priv->rx_ring[0]->cqn, -1, &context);
 865
 866         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
 867                 rss_rings = priv->rx_ring_num;
 868         else
 869                 rss_rings = priv->prof->rss_rings;
 870
 871         ptr = ((u8 *)&context) + offsetof(struct mlx4_qp_context, pri_path) +
 872             MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
 873         rss_context = ptr;
 874         rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
 875                                             (rss_map->base_qpn));
 876         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
 877         if (priv->mdev->profile.udp_rss) {
 878                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
 879                 rss_context->base_qpn_udp = rss_context->default_qpn;
 880         }
 881         rss_context->flags = rss_mask;
 882         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
 883         for (i = 0; i < 10; i++)
 884                 rss_context->rss_key[i] = cpu_to_be32(rsskey[i]);
 885
 886         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
 887                                &rss_map->indir_qp, &rss_map->indir_state);
 888         if (err)
 889                 goto indir_err;
 890
 891         return 0;
 892
 893 indir_err:
 894         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
 895                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
 896         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
 897         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
 898 rss_err:
 899         for (i = 0; i < good_qps; i++) {
 900                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
 901                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
 902                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
 903                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
 904         }
 905         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
 906         return err;
 907 }
 908
 909 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
 910 {
 911         struct mlx4_en_dev *mdev = priv->mdev;
 912         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
 913         int i;
 914
 915         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
 916                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
 917         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
 918         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
 919
 920         for (i = 0; i < priv->rx_ring_num; i++) {
 921                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
 922                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
 923                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
 924                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
 925         }
 926         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
 927 }
 928