2 * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #define LINUXKPI_PARAM_PREFIX mlx4_
36 #include <linux/page.h>
37 #include <dev/mlx4/cq.h>
38 #include <linux/slab.h>
39 #include <dev/mlx4/qp.h>
40 #include <linux/if_vlan.h>
41 #include <linux/vmalloc.h>
42 #include <linux/moduleparam.h>
44 #include <netinet/in_systm.h>
45 #include <netinet/in.h>
46 #include <netinet/if_ether.h>
47 #include <netinet/ip.h>
48 #include <netinet/ip6.h>
49 #include <netinet/tcp.h>
50 #include <netinet/tcp_lro.h>
51 #include <netinet/udp.h>
55 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
56 struct mlx4_en_tx_ring **pring, u32 size,
57 u16 stride, int node, int queue_idx)
59 struct mlx4_en_dev *mdev = priv->mdev;
60 struct mlx4_en_tx_ring *ring;
65 ring = kzalloc_node(sizeof(struct mlx4_en_tx_ring), GFP_KERNEL, node);
67 ring = kzalloc(sizeof(struct mlx4_en_tx_ring), GFP_KERNEL);
69 en_err(priv, "Failed allocating TX ring\n");
74 /* Create DMA descriptor TAG */
75 if ((err = -bus_dma_tag_create(
76 bus_get_dma_tag(mdev->pdev->dev.bsddev),
77 1, /* any alignment */
79 BUS_SPACE_MAXADDR, /* lowaddr */
80 BUS_SPACE_MAXADDR, /* highaddr */
81 NULL, NULL, /* filter, filterarg */
82 MLX4_EN_TX_MAX_PAYLOAD_SIZE, /* maxsize */
83 MLX4_EN_TX_MAX_MBUF_FRAGS, /* nsegments */
84 MLX4_EN_TX_MAX_MBUF_SIZE, /* maxsegsize */
86 NULL, NULL, /* lockfunc, lockfuncarg */
91 ring->size_mask = size - 1;
92 ring->stride = stride;
93 ring->inline_thold = MAX(MIN_PKT_LEN, MIN(priv->prof->inline_thold, MAX_INLINE));
94 mtx_init(&ring->tx_lock.m, "mlx4 tx", NULL, MTX_DEF);
95 mtx_init(&ring->comp_lock.m, "mlx4 comp", NULL, MTX_DEF);
97 /* Allocate the buf ring */
98 ring->br = buf_ring_alloc(MLX4_EN_DEF_TX_QUEUE_SIZE, M_DEVBUF,
99 M_WAITOK, &ring->tx_lock.m);
100 if (ring->br == NULL) {
101 en_err(priv, "Failed allocating tx_info ring\n");
103 goto err_free_dma_tag;
106 tmp = size * sizeof(struct mlx4_en_tx_info);
107 ring->tx_info = kzalloc_node(tmp, GFP_KERNEL, node);
108 if (!ring->tx_info) {
109 ring->tx_info = kzalloc(tmp, GFP_KERNEL);
110 if (!ring->tx_info) {
116 /* Create DMA descriptor MAPs */
117 for (x = 0; x != size; x++) {
118 err = -bus_dmamap_create(ring->dma_tag, 0,
119 &ring->tx_info[x].dma_map);
122 bus_dmamap_destroy(ring->dma_tag,
123 ring->tx_info[x].dma_map);
129 en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
132 ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
134 /* Allocate HW buffers on provided NUMA node */
135 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
138 en_err(priv, "Failed allocating hwq resources\n");
142 err = mlx4_en_map_buffer(&ring->wqres.buf);
144 en_err(priv, "Failed to map TX buffer\n");
148 ring->buf = ring->wqres.buf.direct.buf;
150 en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d "
151 "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size,
152 ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map);
154 err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn,
155 MLX4_RESERVE_ETH_BF_QP);
157 en_err(priv, "failed reserving qp for TX ring\n");
161 err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL);
163 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
166 ring->qp.event = mlx4_en_sqp_event;
168 err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
170 en_dbg(DRV, priv, "working without blueflame (%d)", err);
171 ring->bf.uar = &mdev->priv_uar;
172 ring->bf.uar->map = mdev->uar_map;
173 ring->bf_enabled = false;
175 ring->bf_enabled = true;
176 ring->queue_index = queue_idx;
182 mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
184 mlx4_en_unmap_buffer(&ring->wqres.buf);
186 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
188 for (x = 0; x != size; x++)
189 bus_dmamap_destroy(ring->dma_tag, ring->tx_info[x].dma_map);
191 vfree(ring->tx_info);
193 buf_ring_free(ring->br, M_DEVBUF);
195 bus_dma_tag_destroy(ring->dma_tag);
201 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
202 struct mlx4_en_tx_ring **pring)
204 struct mlx4_en_dev *mdev = priv->mdev;
205 struct mlx4_en_tx_ring *ring = *pring;
207 en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
209 buf_ring_free(ring->br, M_DEVBUF);
210 if (ring->bf_enabled)
211 mlx4_bf_free(mdev->dev, &ring->bf);
212 mlx4_qp_remove(mdev->dev, &ring->qp);
213 mlx4_qp_free(mdev->dev, &ring->qp);
214 mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1);
215 mlx4_en_unmap_buffer(&ring->wqres.buf);
216 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
217 for (x = 0; x != ring->size; x++)
218 bus_dmamap_destroy(ring->dma_tag, ring->tx_info[x].dma_map);
219 vfree(ring->tx_info);
220 mtx_destroy(&ring->tx_lock.m);
221 mtx_destroy(&ring->comp_lock.m);
222 bus_dma_tag_destroy(ring->dma_tag);
227 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
228 struct mlx4_en_tx_ring *ring,
229 int cq, int user_prio)
231 struct mlx4_en_dev *mdev = priv->mdev;
236 ring->cons = 0xffffffff;
237 ring->last_nr_txbb = 1;
240 memset(ring->buf, 0, ring->buf_size);
242 ring->qp_state = MLX4_QP_STATE_RST;
243 ring->doorbell_qpn = ring->qp.qpn << 8;
245 mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
246 ring->cqn, user_prio, &ring->context);
247 if (ring->bf_enabled)
248 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
250 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
251 &ring->qp, &ring->qp_state);
255 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
256 struct mlx4_en_tx_ring *ring)
258 struct mlx4_en_dev *mdev = priv->mdev;
260 mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
261 MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
264 static volatile struct mlx4_wqe_data_seg *
265 mlx4_en_store_inline_lso_data(volatile struct mlx4_wqe_data_seg *dseg,
266 struct mbuf *mb, int len, __be32 owner_bit)
268 uint8_t *inl = __DEVOLATILE(uint8_t *, dseg);
270 /* copy data into place */
271 m_copydata(mb, 0, len, inl + 4);
272 dseg += DIV_ROUND_UP(4 + len, DS_SIZE_ALIGNMENT);
277 mlx4_en_store_inline_lso_header(volatile struct mlx4_wqe_data_seg *dseg,
278 int len, __be32 owner_bit)
283 mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
284 struct mlx4_en_tx_ring *ring, u32 index, u8 owner)
286 struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
287 struct mlx4_en_tx_desc *tx_desc = (struct mlx4_en_tx_desc *)
288 (ring->buf + (index * TXBB_SIZE));
289 volatile __be32 *ptr = (__be32 *)tx_desc;
290 const __be32 stamp = cpu_to_be32(STAMP_VAL |
291 ((u32)owner << STAMP_SHIFT));
294 /* Stamp the freed descriptor */
295 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
302 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
303 struct mlx4_en_tx_ring *ring, u32 index)
305 struct mlx4_en_tx_info *tx_info;
308 tx_info = &ring->tx_info[index];
314 bus_dmamap_sync(ring->dma_tag, tx_info->dma_map,
315 BUS_DMASYNC_POSTWRITE);
316 bus_dmamap_unload(ring->dma_tag, tx_info->dma_map);
320 return (tx_info->nr_txbb);
323 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
325 struct mlx4_en_priv *priv = netdev_priv(dev);
328 /* Skip last polled descriptor */
329 ring->cons += ring->last_nr_txbb;
330 en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
331 ring->cons, ring->prod);
333 if ((u32) (ring->prod - ring->cons) > ring->size) {
334 en_warn(priv, "Tx consumer passed producer!\n");
338 while (ring->cons != ring->prod) {
339 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
340 ring->cons & ring->size_mask);
341 ring->cons += ring->last_nr_txbb;
346 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
352 mlx4_en_tx_ring_is_full(struct mlx4_en_tx_ring *ring)
355 wqs = ring->size - (ring->prod - ring->cons);
356 return (wqs < (HEADROOM + (2 * MLX4_EN_TX_WQE_MAX_WQEBBS)));
359 static int mlx4_en_process_tx_cq(struct net_device *dev,
360 struct mlx4_en_cq *cq)
362 struct mlx4_en_priv *priv = netdev_priv(dev);
363 struct mlx4_cq *mcq = &cq->mcq;
364 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
365 struct mlx4_cqe *cqe;
367 u16 new_index, ring_index, stamp_index;
368 u32 txbbs_skipped = 0;
370 u32 cons_index = mcq->cons_index;
372 u32 size_mask = ring->size_mask;
373 struct mlx4_cqe *buf = cq->buf;
374 int factor = priv->cqe_factor;
379 index = cons_index & size_mask;
380 cqe = &buf[(index << factor) + factor];
381 ring_index = ring->cons & size_mask;
382 stamp_index = ring_index;
384 /* Process all completed CQEs */
385 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
386 cons_index & size)) {
388 * make sure we read the CQE after we read the
393 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
394 MLX4_CQE_OPCODE_ERROR)) {
395 en_err(priv, "CQE completed in error - vendor syndrom: 0x%x syndrom: 0x%x\n",
396 ((struct mlx4_err_cqe *)cqe)->
398 ((struct mlx4_err_cqe *)cqe)->syndrome);
401 /* Skip over last polled CQE */
402 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
405 txbbs_skipped += ring->last_nr_txbb;
406 ring_index = (ring_index + ring->last_nr_txbb) & size_mask;
407 /* free next descriptor */
408 ring->last_nr_txbb = mlx4_en_free_tx_desc(
409 priv, ring, ring_index);
410 mlx4_en_stamp_wqe(priv, ring, stamp_index,
411 !!((ring->cons + txbbs_stamp) &
413 stamp_index = ring_index;
414 txbbs_stamp = txbbs_skipped;
415 } while (ring_index != new_index);
418 index = cons_index & size_mask;
419 cqe = &buf[(index << factor) + factor];
424 * To prevent CQ overflow we first update CQ consumer and only then
427 mcq->cons_index = cons_index;
430 ring->cons += txbbs_skipped;
432 /* Wakeup Tx queue if it was stopped and ring is not full */
433 if (unlikely(ring->blocked) && !mlx4_en_tx_ring_is_full(ring)) {
435 if (atomic_fetchadd_int(&priv->blocked, -1) == 1)
436 atomic_clear_int(&dev->if_drv_flags ,IFF_DRV_OACTIVE);
437 priv->port_stats.wake_queue++;
443 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
445 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
446 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
447 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
449 if (priv->port_up == 0 || !spin_trylock(&ring->comp_lock))
451 mlx4_en_process_tx_cq(cq->dev, cq);
452 mod_timer(&cq->timer, jiffies + 1);
453 spin_unlock(&ring->comp_lock);
456 void mlx4_en_poll_tx_cq(unsigned long data)
458 struct mlx4_en_cq *cq = (struct mlx4_en_cq *) data;
459 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
460 struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
463 INC_PERF_COUNTER(priv->pstats.tx_poll);
465 if (priv->port_up == 0)
467 if (!spin_trylock(&ring->comp_lock)) {
468 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
471 mlx4_en_process_tx_cq(cq->dev, cq);
472 inflight = (u32) (ring->prod - ring->cons - ring->last_nr_txbb);
474 /* If there are still packets in flight and the timer has not already
475 * been scheduled by the Tx routine then schedule it here to guarantee
476 * completion processing of these packets */
477 if (inflight && priv->port_up)
478 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
480 spin_unlock(&ring->comp_lock);
483 static inline void mlx4_en_xmit_poll(struct mlx4_en_priv *priv, int tx_ind)
485 struct mlx4_en_cq *cq = priv->tx_cq[tx_ind];
486 struct mlx4_en_tx_ring *ring = priv->tx_ring[tx_ind];
488 if (priv->port_up == 0)
491 /* If we don't have a pending timer, set one up to catch our recent
492 post in case the interface becomes idle */
493 if (!timer_pending(&cq->timer))
494 mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
496 /* Poll the CQ every mlx4_en_TX_MODER_POLL packets */
497 if ((++ring->poll_cnt & (MLX4_EN_TX_POLL_MODER - 1)) == 0)
498 if (spin_trylock(&ring->comp_lock)) {
499 mlx4_en_process_tx_cq(priv->dev, cq);
500 spin_unlock(&ring->comp_lock);
505 mlx4_en_get_inline_hdr_size(struct mlx4_en_tx_ring *ring, struct mbuf *mb)
509 /* only copy from first fragment, if possible */
510 retval = MIN(ring->inline_thold, mb->m_len);
512 /* check for too little data */
513 if (unlikely(retval < MIN_PKT_LEN))
514 retval = MIN(ring->inline_thold, mb->m_pkthdr.len);
519 mlx4_en_get_header_size(struct mbuf *mb)
521 struct ether_vlan_header *eh;
524 int ip_hlen, tcp_hlen;
529 eh = mtod(mb, struct ether_vlan_header *);
530 if (mb->m_len < ETHER_HDR_LEN)
532 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
533 eth_type = ntohs(eh->evl_proto);
534 eth_hdr_len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
536 eth_type = ntohs(eh->evl_encap_proto);
537 eth_hdr_len = ETHER_HDR_LEN;
539 if (mb->m_len < eth_hdr_len)
543 ip = (struct ip *)(mb->m_data + eth_hdr_len);
544 if (mb->m_len < eth_hdr_len + sizeof(*ip))
546 if (ip->ip_p != IPPROTO_TCP)
548 ip_hlen = ip->ip_hl << 2;
549 eth_hdr_len += ip_hlen;
552 ip6 = (struct ip6_hdr *)(mb->m_data + eth_hdr_len);
553 if (mb->m_len < eth_hdr_len + sizeof(*ip6))
555 if (ip6->ip6_nxt != IPPROTO_TCP)
557 eth_hdr_len += sizeof(*ip6);
562 if (mb->m_len < eth_hdr_len + sizeof(*th))
564 th = (struct tcphdr *)(mb->m_data + eth_hdr_len);
565 tcp_hlen = th->th_off << 2;
566 eth_hdr_len += tcp_hlen;
567 if (mb->m_len < eth_hdr_len)
569 return (eth_hdr_len);
572 static volatile struct mlx4_wqe_data_seg *
573 mlx4_en_store_inline_data(volatile struct mlx4_wqe_data_seg *dseg,
574 struct mbuf *mb, int len, __be32 owner_bit)
576 uint8_t *inl = __DEVOLATILE(uint8_t *, dseg);
577 const int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - 4;
579 if (unlikely(len < MIN_PKT_LEN)) {
580 m_copydata(mb, 0, len, inl + 4);
581 memset(inl + 4 + len, 0, MIN_PKT_LEN - len);
582 dseg += DIV_ROUND_UP(4 + MIN_PKT_LEN, DS_SIZE_ALIGNMENT);
583 } else if (len <= spc) {
584 m_copydata(mb, 0, len, inl + 4);
585 dseg += DIV_ROUND_UP(4 + len, DS_SIZE_ALIGNMENT);
587 m_copydata(mb, 0, spc, inl + 4);
588 m_copydata(mb, spc, len - spc, inl + 8 + spc);
589 dseg += DIV_ROUND_UP(8 + len, DS_SIZE_ALIGNMENT);
595 mlx4_en_store_inline_header(volatile struct mlx4_wqe_data_seg *dseg,
596 int len, __be32 owner_bit)
598 uint8_t *inl = __DEVOLATILE(uint8_t *, dseg);
599 const int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - 4;
601 if (unlikely(len < MIN_PKT_LEN)) {
602 *(volatile uint32_t *)inl =
603 SET_BYTE_COUNT((1U << 31) | MIN_PKT_LEN);
604 } else if (len <= spc) {
605 *(volatile uint32_t *)inl =
606 SET_BYTE_COUNT((1U << 31) | len);
608 *(volatile uint32_t *)(inl + 4 + spc) =
609 SET_BYTE_COUNT((1U << 31) | (len - spc));
611 *(volatile uint32_t *)inl =
612 SET_BYTE_COUNT((1U << 31) | spc);
616 static uint32_t hashrandom;
617 static void hashrandom_init(void *arg)
620 * It is assumed that the random subsystem has been
621 * initialized when this function is called:
623 hashrandom = m_ether_tcpip_hash_init();
625 SYSINIT(hashrandom_init, SI_SUB_RANDOM, SI_ORDER_ANY, &hashrandom_init, NULL);
627 u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb)
629 struct mlx4_en_priv *priv = netdev_priv(dev);
630 u32 rings_p_up = priv->num_tx_rings_p_up;
634 #if (MLX4_EN_NUM_UP > 1)
635 /* Obtain VLAN information if present */
636 if (mb->m_flags & M_VLANTAG) {
637 u32 vlan_tag = mb->m_pkthdr.ether_vtag;
638 up = (vlan_tag >> 13) % MLX4_EN_NUM_UP;
641 queue_index = m_ether_tcpip_hash(MBUF_HASHFLAG_L3 | MBUF_HASHFLAG_L4, mb, hashrandom);
643 return ((queue_index % rings_p_up) + (up * rings_p_up));
646 static void mlx4_bf_copy(void __iomem *dst, volatile unsigned long *src, unsigned bytecnt)
648 __iowrite64_copy(dst, __DEVOLATILE(void *, src), bytecnt / 8);
651 static int mlx4_en_xmit(struct mlx4_en_priv *priv, int tx_ind, struct mbuf **mbp)
654 DS_FACT = TXBB_SIZE / DS_SIZE_ALIGNMENT,
655 CTRL_FLAGS = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
656 MLX4_WQE_CTRL_SOLICITED),
658 bus_dma_segment_t segs[MLX4_EN_TX_MAX_MBUF_FRAGS];
659 volatile struct mlx4_wqe_data_seg *dseg;
660 volatile struct mlx4_wqe_data_seg *dseg_inline;
661 volatile struct mlx4_en_tx_desc *tx_desc;
662 struct mlx4_en_tx_ring *ring = priv->tx_ring[tx_ind];
663 struct ifnet *ifp = priv->dev;
664 struct mlx4_en_tx_info *tx_info;
665 struct mbuf *mb = *mbp;
678 if (unlikely(!priv->port_up)) {
683 /* check if TX ring is full */
684 if (unlikely(mlx4_en_tx_ring_is_full(ring))) {
685 /* every full native Tx ring stops queue */
686 if (ring->blocked == 0)
687 atomic_add_int(&priv->blocked, 1);
688 /* Set HW-queue-is-full flag */
689 atomic_set_int(&ifp->if_drv_flags, IFF_DRV_OACTIVE);
690 priv->port_stats.queue_stopped++;
692 ring->queue_stopped++;
694 /* Use interrupts to find out when queue opened */
695 mlx4_en_arm_cq(priv, priv->tx_cq[tx_ind]);
699 /* sanity check we are not wrapping around */
700 KASSERT(((~ring->prod) & ring->size_mask) >=
701 (MLX4_EN_TX_WQE_MAX_WQEBBS - 1), ("Wrapping around TX ring"));
703 /* Track current inflight packets for performance analysis */
704 AVG_PERF_COUNTER(priv->pstats.inflight_avg,
705 (u32) (ring->prod - ring->cons - 1));
707 /* Track current mbuf packet header length */
708 AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, mb->m_pkthdr.len);
710 /* Grab an index and try to transmit packet */
711 owner_bit = (ring->prod & ring->size) ?
712 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0;
713 index = ring->prod & ring->size_mask;
714 tx_desc = (volatile struct mlx4_en_tx_desc *)
715 (ring->buf + index * TXBB_SIZE);
716 tx_info = &ring->tx_info[index];
717 dseg = &tx_desc->data;
719 /* send a copy of the frame to the BPF listener, if any */
720 if (ifp != NULL && ifp->if_bpf != NULL)
721 ETHER_BPF_MTAP(ifp, mb);
723 /* get default flags */
724 tx_desc->ctrl.srcrb_flags = CTRL_FLAGS;
726 if (mb->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))
727 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
729 if (mb->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP |
730 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
731 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_TCP_UDP_CSUM);
734 if (likely(tx_desc->ctrl.srcrb_flags != CTRL_FLAGS)) {
735 priv->port_stats.tx_chksum_offload++;
739 /* check for VLAN tag */
740 if (mb->m_flags & M_VLANTAG) {
741 tx_desc->ctrl.vlan_tag = cpu_to_be16(mb->m_pkthdr.ether_vtag);
742 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN;
744 tx_desc->ctrl.vlan_tag = 0;
745 tx_desc->ctrl.ins_vlan = 0;
748 if (unlikely(mlx4_is_mfunc(priv->mdev->dev) || priv->validate_loopback)) {
750 * Copy destination MAC address to WQE. This allows
751 * loopback in eSwitch, so that VFs and PF can
752 * communicate with each other:
754 m_copydata(mb, 0, 2, __DEVOLATILE(void *, &tx_desc->ctrl.srcrb_flags16[0]));
755 m_copydata(mb, 2, 4, __DEVOLATILE(void *, &tx_desc->ctrl.imm));
757 /* clear immediate field */
758 tx_desc->ctrl.imm = 0;
761 /* Handle LSO (TSO) packets */
762 if (mb->m_pkthdr.csum_flags & CSUM_TSO) {
764 u32 mss = mb->m_pkthdr.tso_segsz;
767 opcode = cpu_to_be32(MLX4_OPCODE_LSO | MLX4_WQE_CTRL_RR) |
769 ihs = mlx4_en_get_header_size(mb);
770 if (unlikely(ihs > MAX_INLINE)) {
771 ring->oversized_packets++;
775 tx_desc->lso.mss_hdr_size = cpu_to_be32((mss << 16) | ihs);
776 payload_len = mb->m_pkthdr.len - ihs;
777 if (unlikely(payload_len == 0))
780 num_pkts = DIV_ROUND_UP(payload_len, mss);
781 ring->bytes += payload_len + (num_pkts * ihs);
782 ring->packets += num_pkts;
784 /* store pointer to inline header */
786 /* copy data inline */
787 dseg = mlx4_en_store_inline_lso_data(dseg,
790 opcode = cpu_to_be32(MLX4_OPCODE_SEND) |
792 ihs = mlx4_en_get_inline_hdr_size(ring, mb);
793 ring->bytes += max_t (unsigned int,
794 mb->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
796 /* store pointer to inline header */
798 /* copy data inline */
799 dseg = mlx4_en_store_inline_data(dseg,
804 err = bus_dmamap_load_mbuf_sg(ring->dma_tag, tx_info->dma_map,
805 mb, segs, &nr_segs, BUS_DMA_NOWAIT);
806 if (unlikely(err == EFBIG)) {
807 /* Too many mbuf fragments */
808 ring->defrag_attempts++;
809 m = m_defrag(mb, M_NOWAIT);
811 ring->oversized_packets++;
816 err = bus_dmamap_load_mbuf_sg(ring->dma_tag, tx_info->dma_map,
817 mb, segs, &nr_segs, BUS_DMA_NOWAIT);
820 if (unlikely(err != 0)) {
821 ring->oversized_packets++;
824 /* If there were no errors and we didn't load anything, don't sync. */
826 /* make sure all mbuf data is written to RAM */
827 bus_dmamap_sync(ring->dma_tag, tx_info->dma_map,
828 BUS_DMASYNC_PREWRITE);
830 /* All data was inlined, free the mbuf. */
831 bus_dmamap_unload(ring->dma_tag, tx_info->dma_map);
836 /* compute number of DS needed */
837 ds_cnt = (dseg - ((volatile struct mlx4_wqe_data_seg *)tx_desc)) + nr_segs;
840 * Check if the next request can wrap around and fill the end
841 * of the current request with zero immediate data:
843 pad = DIV_ROUND_UP(ds_cnt, DS_FACT);
844 pad = (~(ring->prod + pad)) & ring->size_mask;
846 if (unlikely(pad < (MLX4_EN_TX_WQE_MAX_WQEBBS - 1))) {
848 * Compute the least number of DS blocks we need to
849 * pad in order to achieve a TX ring wraparound:
851 pad = (DS_FACT * (pad + 1));
854 * The hardware will automatically jump to the next
855 * TXBB. No need for padding.
860 /* compute total number of DS blocks */
863 * When modifying this code, please ensure that the following
864 * computation is always less than or equal to 0x3F:
866 * ((MLX4_EN_TX_WQE_MAX_WQEBBS - 1) * DS_FACT) +
867 * (MLX4_EN_TX_WQE_MAX_WQEBBS * DS_FACT)
869 * Else the "ds_cnt" variable can become too big.
871 tx_desc->ctrl.fence_size = (ds_cnt & 0x3f);
873 /* store pointer to mbuf */
875 tx_info->nr_txbb = DIV_ROUND_UP(ds_cnt, DS_FACT);
876 bf_size = ds_cnt * DS_SIZE_ALIGNMENT;
877 bf_prod = ring->prod;
879 /* compute end of "dseg" array */
880 dseg += nr_segs + pad;
882 /* pad using zero immediate dseg */
888 dseg->byte_count = SET_BYTE_COUNT((1U << 31)|0);
891 /* fill segment list */
893 if (unlikely(segs[nr_segs].ds_len == 0)) {
898 dseg->byte_count = SET_BYTE_COUNT((1U << 31)|0);
901 dseg->addr = cpu_to_be64((uint64_t)segs[nr_segs].ds_addr);
902 dseg->lkey = cpu_to_be32(priv->mdev->mr.key);
904 dseg->byte_count = SET_BYTE_COUNT((uint32_t)segs[nr_segs].ds_len);
910 /* write owner bits in reverse order */
911 if ((opcode & cpu_to_be32(0x1F)) == cpu_to_be32(MLX4_OPCODE_LSO))
912 mlx4_en_store_inline_lso_header(dseg_inline, ihs, owner_bit);
914 mlx4_en_store_inline_header(dseg_inline, ihs, owner_bit);
916 /* update producer counter */
917 ring->prod += tx_info->nr_txbb;
919 if (ring->bf_enabled && bf_size <= MAX_BF &&
920 (tx_desc->ctrl.ins_vlan != MLX4_WQE_CTRL_INS_CVLAN)) {
922 /* store doorbell number */
923 *(volatile __be32 *) (&tx_desc->ctrl.vlan_tag) |= cpu_to_be32(ring->doorbell_qpn);
925 /* or in producer number for this WQE */
926 opcode |= cpu_to_be32((bf_prod & 0xffff) << 8);
929 * Ensure the new descriptor hits memory before
930 * setting ownership of this descriptor to HW:
933 tx_desc->ctrl.owner_opcode = opcode;
935 mlx4_bf_copy(((u8 *)ring->bf.reg) + ring->bf.offset,
936 (volatile unsigned long *) &tx_desc->ctrl, bf_size);
938 ring->bf.offset ^= ring->bf.buf_size;
941 * Ensure the new descriptor hits memory before
942 * setting ownership of this descriptor to HW:
945 tx_desc->ctrl.owner_opcode = opcode;
947 writel(cpu_to_be32(ring->doorbell_qpn),
948 ((u8 *)ring->bf.uar->map) + MLX4_SEND_DOORBELL);
959 mlx4_en_transmit_locked(struct ifnet *dev, int tx_ind, struct mbuf *m)
961 struct mlx4_en_priv *priv = netdev_priv(dev);
962 struct mlx4_en_tx_ring *ring;
964 int enqueued, err = 0;
966 ring = priv->tx_ring[tx_ind];
967 if ((dev->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
968 IFF_DRV_RUNNING || priv->port_up == 0) {
970 err = drbr_enqueue(dev, ring->br, m);
977 * If we can't insert mbuf into drbr, try to xmit anyway.
978 * We keep the error we got so we could return that after xmit.
980 err = drbr_enqueue(dev, ring->br, m);
982 /* Process the queue */
983 while ((next = drbr_peek(dev, ring->br)) != NULL) {
984 if (mlx4_en_xmit(priv, tx_ind, &next) != 0) {
986 drbr_advance(dev, ring->br);
988 drbr_putback(dev, ring->br, next);
992 drbr_advance(dev, ring->br);
994 if ((dev->if_drv_flags & IFF_DRV_RUNNING) == 0)
999 ring->watchdog_time = ticks;
1005 mlx4_en_tx_que(void *context, int pending)
1007 struct mlx4_en_tx_ring *ring;
1008 struct mlx4_en_priv *priv;
1009 struct net_device *dev;
1010 struct mlx4_en_cq *cq;
1014 priv = dev->if_softc;
1016 ring = priv->tx_ring[tx_ind];
1018 if (priv->port_up != 0 &&
1019 (dev->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1020 mlx4_en_xmit_poll(priv, tx_ind);
1021 spin_lock(&ring->tx_lock);
1022 if (!drbr_empty(dev, ring->br))
1023 mlx4_en_transmit_locked(dev, tx_ind, NULL);
1024 spin_unlock(&ring->tx_lock);
1029 mlx4_en_transmit(struct ifnet *dev, struct mbuf *m)
1031 struct mlx4_en_priv *priv = netdev_priv(dev);
1032 struct mlx4_en_tx_ring *ring;
1033 struct mlx4_en_cq *cq;
1036 if (priv->port_up == 0) {
1041 /* Compute which queue to use */
1042 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) {
1043 i = (m->m_pkthdr.flowid % 128) % priv->tx_ring_num;
1046 i = mlx4_en_select_queue(dev, m);
1049 ring = priv->tx_ring[i];
1050 if (spin_trylock(&ring->tx_lock)) {
1051 err = mlx4_en_transmit_locked(dev, i, m);
1052 spin_unlock(&ring->tx_lock);
1054 mlx4_en_xmit_poll(priv, i);
1056 err = drbr_enqueue(dev, ring->br, m);
1057 cq = priv->tx_cq[i];
1058 taskqueue_enqueue(cq->tq, &cq->cq_task);
1061 #if __FreeBSD_version >= 1100000
1062 if (unlikely(err != 0))
1063 if_inc_counter(dev, IFCOUNTER_IQDROPS, 1);
1069 * Flush ring buffers.
1072 mlx4_en_qflush(struct ifnet *dev)
1074 struct mlx4_en_priv *priv = netdev_priv(dev);
1075 struct mlx4_en_tx_ring *ring;
1078 if (priv->port_up == 0)
1081 for (int i = 0; i < priv->tx_ring_num; i++) {
1082 ring = priv->tx_ring[i];
1083 spin_lock(&ring->tx_lock);
1084 while ((m = buf_ring_dequeue_sc(ring->br)) != NULL)
1086 spin_unlock(&ring->tx_lock);